DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 6-7, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-5, and 8-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8-9, and 11-14 are of U.S. Patent No. 12079608 in view of Davis and Cambron. See table and rejections below.
Instant Application
12079608 Patent
8. A method comprising:
instantiating, on a target platform comprising one or more processing devices, a machine learning model (MLM) using a plurality of instructions generated in view of a hardware configuration of the target platform; and
processing inference data, using the instantiated MLM, to obtain an inference output, wherein processing the inference data comprises: loading a first portion of the MLM, the first portion comprising a first plurality of parameters of the MLM, to a memory device of the target platform,
performing a first plurality of operations of the MLM using the first plurality of parameters of the MLM, and
loading a second portion of the MLM, the second portion comprising a second plurality of parameters of the MLM, to the memory device of the target platform, wherein loading the second portion of the MLM comprises replacing, in the memory device of the target platform, at least a subset of the first plurality of parameters of the MLM with a subset of the second plurality of parameters of the MLM.
8. A method to deploy a machine learning model (MLM), the method comprising:
instantiating, on an edge computing device (ECD), a MLM using an execution package generated in view of a hardware configuration of the ECD, … and
processing inference data, using the instantiated MLM, to obtain an inference output, wherein processing the inference data comprises: loading a first portion of the MLM, the first portion comprising a first plurality of parameters of the MLM, to the first memory device of the ECD…
performing a first plurality of operations of the MLM using the first plurality of parameters of the MLM, and
loading a second portion of the MLM, the second portion comprising a second plurality of parameters of the MLM, to the first memory device of the ECD, wherein loading the second portion of the MLM comprises replacing, in the second memory device of the ECD, at least a subset of the first plurality of parameters of the MLM with a subset of the second plurality of parameters of the MLM.
9. The method of claim 8 further comprising: performing a second plurality of operations of the MLM using the second plurality of parameters of the MLM; and obtaining the inference output using a first output of the first plurality of operations of the MLM and a second output of the second plurality of operations of the MLM.
9. The method of claim 8 further comprising: performing a second plurality of operations of the MLM using the second plurality of parameters of the MLM; and obtaining the inference output using a first output of the first plurality of operations of the MLM and a second output of the second plurality of operations of the MLM.
11. The method of claim 8, wherein processing the inference data further comprises: applying a first kernel to a first portion of the inference data; applying a second kernel to a second portion of the inference data, wherein the second kernel is obtained by truncating the first kernel to a size of the second portion of the inference data.
11. The method of claim 8, wherein processing the inference data further comprises: applying a first kernel to a first portion of the inference data; applying a second kernel to a second portion of the inference data, wherein the second kernel is obtained by truncating the first kernel to a size of the second portion of the inference data.
12. The method of claim 11, wherein the second portion of the inference data is abutting a boundary of the inference data.
12. The method of claim 11, wherein the second portion of the inference data is abutting a boundary of the inference data.
13. The method of claim 8, wherein processing the inference data further comprises: applying one or more kernels of the MLM, a dimension of each of the one or more kernels being aligned with a dimension of an instruction set of one or more processing devices of the target platform.
13. The method of claim 8, wherein processing the inference data further comprises: applying one or more kernels of the MLM, a dimension of each of the one or more kernels being aligned with a dimension of vectorized instructions of a processor of the ECD.
14. The method of claim 13, wherein a first kernel of the one or more kernels comprises a padding, a number of bits of the padding determined to align a dimension of the first padding with the dimension of the instruction set
14. The method of claim 13, wherein a first kernel of the one or more kernels comprises a padding, a number of bits of the padding determined to align a dimension of the first padding with the dimension of the vectorized instructions.
As per claim 1, 608 Patent teaches:
A method comprising:
obtaining configuration settings of a machine learning model (MLM) (608 Patent, claim 1);
obtaining a hardware configuration of a target platform that comprises one or more processing devices (608 Patent, claim 1);
608 Patent does not expressly teach:
identifying an instruction set of the one or more processing devices of the target platform; and
generating, in view of the configuration settings of the MLM and the hardware configuration of the target platform, a plurality of instructions configured to execute the MLM using the instruction set of the one or more processing devices of the target platform.
However, Davis, discloses:
identifying an instruction set of the one or more processing devices of the target platform (Davis, RESULTS , Silicon Realization—under BRI, an instruction set can be x86 architecture);
and generating, in view of the configuration settings of the MLM and the hardware configuration of the target platform, a plurality of instructions configured to execute the MLM using the instruction set of the one or more processing devices of the target platform (Davis, Figure 3. Neuron-to-neuron mesh routing model--under BRI, a plurality of instructions can be how neurons are mapped to the cores).
Both 608 Patent and Davis pertain to the art of MLM.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Davis’s method to identifying an instruction set and generating a plurality of instructions configured to execute the MLM because identifying an instruction set and generating tailored instructions to execute a machine learning model (MLM) automates workflow synthesis, optimizes hardware-software co-design, and adapts pre-trained intelligence to specialized domain tasks with minimal human intervention
As per claim 2, 608 Patent teaches:
The method of claim 1 (see rejection on claim 1).
608 Patent does not expressly teach:
wherein the configuration settings comprise one or more of: one or more parameters of computational operations associated with the MLM, a size of data operands associated with one or more neural nodes of the MLM, or identification of one or more connections between the one or more neural nodes of the MLM.
However, Davis discloses:
wherein the configuration settings comprise one or more of:
one or more parameters of computational operations associated with the MLM (Davis, Network Connectivity Architecture—under BRI, one or more parameters of computational operations associated with the MLM can be neuron’s synaptic fan-in state), a size of data operands associated with one or more neural nodes of the MLM, or identification of one or more connections between the one or more neural nodes of the MLM.
Both 608 Patent and Davis pertain to the art of MLM.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Davis’s method to use one or more parameters of computational operations associated with the MLM because using parameters from Machine Learning Models (MLMs) as configuration settings allows systems to adapt dynamically to data patterns, reduce hardcoded rules, and optimize runtime performance based on real-time statistical insights.
As per claim 3, 608 Patent teaches:
The method of claim 1 (see rejection on claim 1)
608 Patent does not expressly teach:
further comprising: communicating the plurality of instructions to the target platform.
However, Davis discloses:
communicating the plurality of instructions to the target platform (Davis, Figure 3. Neuron-to-neuron mesh routing model).
Both 608 Patent and Davis pertain to the art of MLM.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Davis’s method to communicate instructions to target platforms because communicating machine learning instructions to target platforms standardizes how models run. It allows different hardware and software to execute AI tasks smoothly without rewriting code for every new system.
As per claim 4, 608 Patent teaches:
The method of claim 1 (See rejection on claim 1).
608 Patent does not expressly teach:
further comprising: providing, to a user, at least a portion of the plurality of instructions; and receiving, from the user, updated configuration settings of the MLM.
However, Cambron discloses:
further comprising:
providing, to a user, at least a portion of the plurality of instructions (Cambron ,col 4, ll 7-10); and
receiving, from the user, updated configuration settings of the MLM (Cambron, col 4, ll 7-10).
Both Cambron and 608 Patent pertain to the art of configuration management.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Cambron’s method to provide and receive user updates because receiving configuration updates from users allows systems to adapt to real-world preferences, catches bugs early through crowd-sourced feedback, improves personalization, and reduces the administrative burden on central IT teams by distributing setup tasks.
As per claim 5, 608 Patent teaches:
The method of claim 1 (see rejection on claim 1).
608 Patent does not expressly teach:
wherein the hardware configuration comprises at least one of: characteristics of the one or more processing devices of the target platform, or characteristics of one or more memory devices of the target platform.
However, Davis discloses:
The method of claim 1 (see rejection on claim 1), wherein the hardware configuration comprises at least one of:
characteristics of the one or more processing devices of the target platform (Davis, Silicon Realization—under BRI, characteristics can be 14-nm FinFET process), or characteristics of one or more memory devices of the target platform.
Both 608 Patent and Davis pertain to the art of MLM.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Davis’s method to use characteristics of the one or more processing devices of the target platform as hardware configuration because using target hardware characteristics as your configuration optimizes software performance by matching code directly to the host CPU, memory, and instruction sets. This eliminates generic overhead and unlocks full processing power.
As per claim 10, 608 Patent teaches:
The method of claim 8 (see rejection on claim 8).
608 Patent does not expressly teach:
wherein he hardware configuration comprises at least one of: characteristics of the one or more processing devices of the target platform, or characteristics of the memory device of the target platform.
However, Davis discloses:
wherein he hardware configuration comprises at least one of: characteristics of the one or more processing devices of the target platform, or characteristics of the memory device of the target platform (see rejection on claim 5).
Both 608 Patent and Davis pertain to the art of MLM.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Davis’s method to use characteristics of the one or more processing devices of the target platform as hardware configuration because using target hardware characteristics as your configuration optimizes software performance by matching code directly to the host CPU, memory, and instruction sets. This eliminates generic overhead and unlocks full processing power.
As per claim 15, see rejection on claim 1.
As per claim 16, see rejection on claim 2.
As per claim 17, see rejection on claim 4.
As per claim 18, see rejection on claim 5.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter.
Claims 1-5, 15-16, and 18 are rejected under 35 U.S.C. 101.
As per claim 1, the claim recites a method, therefore is a process.
“ . . . identifying an instruction set of the one or more processing … generating, in view of the configuration settings of the MLM and the hardware configuration of the target platform, a plurality of instructions … “ These limitations, as drafted, are processes that, under its broadest reasonable interpretation, cover performance of the limitation in the mind but for the recitation of generic computer components. Thus, the claim recites a mental process.
The elements of “obtaining . . . ” amounts to data gathering which is considered to be insignificant extra solution activity (MPEP 2106.05(g); this limitation is also a mere generic transmission and presentation of collected and analyzed data which is considered to be insignificant extra solution activity (MPEP 2106.05(g).
As discussed above, “obtaining . . . ” amounts to data gathering which is considered to be insignificant extra solution activity (MPEP 2106.05(g); this limitation is also a mere generic transmission and presentation of collected and analyzed data which is considered to be insignificant extra solution activity (MPEP 2106.05(g). The claim is ineligible.
As per claim 2, see rejection on claim 1. “… configuration settings comprise one or more of: one or more parameters of computational operations associated with the MLM, a size of data operands associated with one or more neural nodes of the MLM, or identification of one or more connections between the one or more neural nodes of the MLM.… ” is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception - see MPEP 2106.05(d) and Berkheimer Memo. See Davis. The claim is ineligible.
As per claim 3, see rejection on claim 1. “… communicating the plurality of instructions to the target platform .… ” is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception - see MPEP 2106.05(d) and Berkheimer Memo. See Davis. The claim is ineligible.
As per claim 4, see rejection on claim 1. “… providing, to a user, at least a portion of the plurality of instructions; and receiving, from the user, updated configuration settings of the MLM … ” amounts to data gathering which is considered to be insignificant extra solution activity (MPEP 2106.05(g); this limitation is also a mere generic transmission and presentation of collected and analyzed data which is considered to be insignificant extra solution activity (MPEP 2106.05(g).
As per claim 5, see rejection on claim 1. “… wherein the hardware configuration comprises at least one of: characteristics of the one or more processing devices of the target platform, or characteristics of one or more memory devices of the target platform … ” is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception - see MPEP 2106.05(d) and Berkheimer Memo. See Davis. The claim is ineligible.
As per claim 15, see rejection on claim 1.
As per claim 16, see rejection on claim 2.
As per claim 17, see rejection on claim 4.
As per claim 18, see rejection on claim 5.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 15, 16, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Davis et al (Davies, Mike, et al. "Loihi: A neuromorphic manycore processor with on-chip learning." Ieee micro 38.1 (2018): 82-99) (hereinafter Davis).
As per claim 1, Davis teaches:
1. A method comprising:
obtaining configuration settings of a machine learning model (MLM) (Davis, ARCHITECTURE, Network Connectivity Architecture--under BRI, configuration settings of a machine learning model (MLM) can be seven-neuron);
obtaining a hardware configuration of a target platform that comprises one or more processing devices (Davis, ARCHITECTURE, Network Connectivity Architecture--under BRI, a hardware configuration of a target platform that comprises one or more processing devices can be three cores; one or more processing devices can be cores);
identifying an instruction set of the one or more processing devices of the target platform (Davis, RESULTS , Silicon Realization—under BRI, an instruction set can be x86 architecture);
and generating, in view of the configuration settings of the MLM and the hardware configuration of the target platform, a plurality of instructions configured to execute the MLM using the instruction set of the one or more processing devices of the target platform (Davis, Figure 3. Neuron-to-neuron mesh routing model--under BRI, a plurality of instructions can be how neurons are mapped to the cores).
As per claim 2, Davis teaches:
The method of claim 1 (see rejection on claim 1), wherein the configuration settings comprise one or more of:
one or more parameters of computational operations associated with the MLM (Davis, Network Connectivity Architecture—under BRI, one or more parameters of computational operations associated with the MLM can be neuron’s synaptic fan-in state), a size of data operands associated with one or more neural nodes of the MLM, or identification of one or more connections between the one or more neural nodes of the MLM.
As per claim 3, Davis teaches:
The method of claim 1 (see rejection on claim 1), further comprising: communicating the plurality of instructions to the target platform (Davis, Figure 3. Neuron-to-neuron mesh routing model).
As per claim 5, Davis teaches:
The method of claim 1 (see rejection on claim 1), wherein the hardware configuration comprises at least one of:
characteristics of the one or more processing devices of the target platform (Davis, Silicon Realization—under BRI, characteristics can be 14-nm FinFET process), or characteristics of one or more memory devices of the target platform.
As per claim 15, see rejection on claim 1.
As per claim 16, see rejection on claim 2.
As per claim 18, see rejection on claim 5.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Davis in view of Cambron et al (US 7180854 ) (hereinafter Cambron).
As per claim 4, Davis teaches:
The method of claim 1 (see rejection on claim 1).
Davis does not expressly teach:
further comprising:
providing, to a user, at least a portion of the plurality of instructions; and
receiving, from the user, updated configuration settings of the MLM.
However, Cambron discloses:
further comprising:
providing, to a user, at least a portion of the plurality of instructions (Cambron ,col 4, ll 7-10); and
receiving, from the user, updated configuration settings of the MLM (Cambron, col 4, ll 7-10).
Both Cambron and Davis pertain to the art of configuration management.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Cambron’s method to provide and receive user updates because receiving configuration updates from users allows systems to adapt to real-world preferences, catches bugs early through crowd-sourced feedback, improves personalization, and reduces the administrative burden on central IT teams by distributing setup tasks.
As per claim 17, see rejection on claim 4.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 10860760 teaches a method of implementing a learned network on programmable circuits.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLIE SUN whose telephone number is (571)270-5100. The examiner can normally be reached 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Pierre Vital can be reached at (571) 272-4215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHARLIE SUN/Primary Examiner, Art Unit 2198
Prosecution Insights