Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Papers submitted under 35 U.S.C. 119(a)-(d) have been placed of record in the file.
2. Claims 1-15 are presented for examination.
Response to Election
3. Applicant's request for reconsideration of the restriction of the last Office action is persuasive and, therefore, the restriction of that action is withdrawn.
Claim Rejections - 35 USC § 102
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
6. Claims 1-2, 6-11 and 14 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Kim et al. US Pub. No. 20180182449
As per claims 1-2, 7, and 10, Figs. 3-8 of Kim are directed to a bit line sense amplifier comprising: an amplifying circuit (155) connected between a sensing bit line (SABL) and a complementary sensing bit line (SABLB), the amplifying circuit including a plurality of PMOS elements (P_1 and (P_2) and a plurality of NMOS elements (N_1 and N-2); a first offset cancellation circuit (151 and 153) connected between the amplifying circuit and a first memory cell (MC connecting to BL), the first offset cancellation circuit including a first offset element (153) and a first isolation element (151); and a second offset cancellation circuit (152 AND 154) connected between the amplifying circuit and a second memory cell (MC connecting to BLB), the second offset cancellation circuit including a second offset element (154) and a second isolation element (152), wherein the first offset element is connected between the first memory cell and the complementary sensing bit line (Fig. 3) and the second offset element is connected between the second memory cell and the sensing bit line (Fig. 3), wherein the first isolation element is connected between the first memory cell and the sensing bit line and the second isolation element is connected between the second memory cell and the complementary sensing bit line (Fig. 3), and wherein the bit line sense amplifier in a first read operation is configured to: turn on the first offset element, the first isolation, the second offset element, and the second isolation element in a first pre-charging period (S510, Fig. 5 or Fig. 6A or Fig. 8), turn off the first offset element, the first isolation element, the second offset element, and the second isolation element in a first charge sharing period (S530, Fig. 5 or Fig. 6C or Fig. 8) subsequent to the first pre-charging period, and turn on the first offset element and the second offset element and turn off the first isolation element and the second isolation element in a first offset canceling period (S520, Fig. 5 or Fig. 6b or Fig. 8) subsequent to the first charge sharing period.
It is noted that the charge sharing period is before the offset canceling period in the claimed invention while the charge sharing period is after the offset canceling period in Kim’s reference.
However, because the structure suggested by the present invention, Fig. 6 is identical to the reference, Fig. 3, therefore, the function may be inherent or intrinsic to the structure by its property or its characteristic, i.e. the reference is capable of performing the intended use such as the reading operation to the memory cell in series with the capacitive element as the claimed invention. Also see Fig. 16 of the claimed invention is identical to Fig. 8 of the reference for the offset canceling period prior the charge sharing period.
As per claim 6, Fig. 8 of Kim discloses wherein the bit line sense amplifier is configured to charge the bit line, the complementary bit line, the sensing bit line, and the complementary sensing bit line with a pre-charging voltage (t0-t1), and electrically connect the capacitor of the first memory cell (t2-t3)to the bit line in response to charging the bit line, the complementary bit line, the sensing bit line, and the complementary sensing bit line with a pre-charging voltage.
As per claim 8, Fig. 3 of Kim discloses further comprising: a first isolation element (ISO_1) configured to electrically connect the bit line and the sensing bit line in response to an isolation control signal (ISO); and a second isolation element (ISO_2) configured to electrically connect the complementary bit line and the complementary sensing bit line in response to the isolation control signal.
As per claim 9, Fig. 8 of Kim disclose wherein the bit line sense amplifier in the first read operation is configured to further turn off the first isolation element and the second isolation element in the first time period (t1-t2).
As per claim 11, Fig. 8 of Kim discloses wherein the bit line sense amplifier in a second read operation is configured to: turn on the first offset element, the first isolation element, the second offset element, and the second isolation element in a second pre-charging period (t0-t1), turn on the first offset element and the second offset element and turn off the first isolation element and the second isolation element in a second offset canceling period (t1-t2) subsequent to the second pre-charging period, and turn off the first offset element, the first isolation element, the second offset element, and the second isolation element in a second charge sharing period (T2-T3) subsequent to the second offset canceling period.
As per claim 14, Fig. 8 of Kim discloses wherein: the first pre-charging period is the same as the second pre-charging period (for another read operation), and the first charge sharing period is the same as the second charge sharing period (for another read operation).
Allowable Subject matter
7. Claims 3-5, 12-13 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
8. The following is a statement of reasons for the indication of allowable subject matter:
Claims include allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having discloses wherein the first time period that the bit line sense amplifier in the first read operation is configured to turn on the first offset element and the second offset element is longer than a second time period that the bit line sense amplifier in the first read operation is configured to turn on the first offset element and the second offset element in claims 3; further comprising: a pull-up driving circuit including a plurality of PMOS elements electrically connected to each other in parallel, the pull-up driving circuit configured to generate the first sensing driving voltage; and a pull-down driving circuit including a plurality of NMOS elements electrically connected to each other in parallel, the pull-down driving circuit configured to generate the second sensing driving voltage, wherein the number of PMOS elements turned on and the number of NMOS elements turned on in the first read operation are greater than the number of PMOS elements turned on and the number of NMOS elements turned on in the second read operation, respectively in claims 4 and 12; wherein the first offset canceling period is longer than the second offset canceling period in claim 13; wherein a second current flowing through the amplifying circuit in the second offset canceling period is greater than a first current flowing through is configured to flow a first current during the first offset canceling period, and the amplifying circuit in the first offset canceling period in claim 15.
9. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
10. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V HO whose telephone number is (571) 272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Thursday and Friday of the first week of a bi-week and Tuesday and Wednesday of the second week.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/HOAI V HO/Primary Examiner, Art Unit 2827
Prosecution Insights