DETAILED ACTION
This communication is in response to the communication filed on December 16, 2025 in which claims 1-20 are pending in the application. Claims 1, 8, and 14 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
This application claims the benefit of and priority to U.S. Provisional Patent Application No. 63/528,878, titled SYSTEM ARCHITECTURE FOR SUPERCOMPUTER SERVERS, file
July 25, 2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 16, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
This Final Office Action is in response to the applicant’s remarks and arguments filed on December 16, 2025.
No claims were canceled or added. Claims 1, 4-6, 8, 12-14 and 17-19 were amended.
Claims 1-20 remain pending in the application and are being considered on the merits.
Response to Arguments
The applicant’s remarks and/or arguments, filed on December 16, 2025 have been fully considered with the following result(s).
The examiner is entitled to give claim limitations their broadest reasonable interpretation in light of the specification. See MPEP 2111 [R-1] Interpretation of Claims-Broadest Reasonable Interpretation. The applicant always has the opportunity to amend the claims during prosecution,
and broad interpretation by the examiner reduces the possibility that the claim, once issued, will be interpreted more broadly than is justified. In re Prater, 162 USPQ 541,550-51 (CCPA 1969).
Applicant's arguments in the applicant’s remarks and amendments of independent claims 1 and 8, found on pages 6-7 and filed on December 16, 2025, have been fully considered
and are persuasive. Therefore, the previous claim(s) rejection under 35 U.S.C 102 has been withdrawn.
However, upon further consideration, a new ground(s) of rejection is made in view of a newly found prior art: (EP 4179429 A1) issued to Hall et al., and in view of the previously cited prior art(s). Reference Hall discloses the newly added limitation “wherein the processors and the smart memories are enabled to autonomously initiate transactions communicated via the point-to-point interconnect” [The present design includes smart compute resistive RAM to move computations and learning operations from a host system (e.g., CPU, processor, microprocessor) to smart compute resistive memory; Para 0032-0033, 0038, 0053, 0081].
- For further details, please see below claims rejections under 35 USC 103.
Regarding claim 14, Applicant argues that Kruger fails to disclose that memory devices 204 are enabled to initiate transactions autonomously, but rather that the memory devices are accessed by a client.
However, upon further consideration, a new ground(s) of rejection is made in view of a newly found prior art: (US 20220012063 A1) issued to Hall et al., and in view of the previously cited prior art(s). Reference Hall discloses the newly added limitation “wherein the processors and the smart memories are enabled to autonomously initiate transactions communicated via the point-to-point interconnect” [The present design includes smart compute resistive RAM to move computations and learning operations from a host system (e.g., CPU, processor, microprocessor) to smart compute resistive memory; Para 0032-0033, 0038, 0053, 0081].
- For further details, please see below claims rejections under 35 USC 103.
As such, the combination of references discloses the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 8 and 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kruger et al. (US 7,706,255 B1) and Hall et al. (US 20220012063 A1).
As per claim 1, Kruger discloses A system, comprising:
one or more processors [Fig. 2, controller 202, client 206; Fig. 3, clients 302];
one or more smart memories [Fig. 2, memory devices 204]; and
point-to-point interconnect that enables the processors and the smart memories to communicate with each other as peers [FIG. 2, a memory controller circuit 202 provides an interconnection between a plurality of memory devices (RAM) 204 and a plurality of memory clients 206 through a crossbar, or similar switch matrix.].
Kruger does not explicitly teach wherein the processors and the smart memories are enabled to autonomously initiate transactions communicated via the point-to-point interconnect.
Hall teaches wherein the processors and the smart memories are enabled to autonomously initiate transactions communicated via the point-to-point interconnect [Para 0032-0033, The present design includes smart compute resistive RAM to move computations and learning operations from a host system (e.g., CPU, processor, microprocessor) to smart compute resistive memory; Local processing in memory also enables some autonomy in case of poor network and safety; [Para 0038], Communication links 130-1, 130-2, 130-3, and 130-4 (e.g., high speed interconnects, PCIe) provide communications between the I/O circuitry 110, FSM 116, integrated processor 160, smart compute memory management and control circuitry 190, and smart compute memory circuitry 150; [Para 0053], The circuitry 300 provides compute functions for processing data locally within a memory subsystem without utilized a host system (e.g., main CPU 1202, processor 1227); [Para 0081], Communication links 630-1, 630-2, 630-3, and 630-4 (e.g., high speed interconnects, PCIe) provide communications between the I/O circuitry 610, FSM 616, integrated processor 660, smart compute memory management and control circuitry 690, and smart compute memory circuitry 650].
Both Kruger and Hall are in the same field of endeavor as they are both in the memory circuitry and integrated circuit art and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Kruger with the teachings of Hall in order to enable some autonomy by local processing in case of poor network and safety and compute inside the memory enables to conduct certain operation on the fly.
Modification would improve both performance and overall system power by reducing latency and improving performance in Storage Drives by doing some operations native to the Drive instead of sending data from the drive to the host system and then having the host system perform the operation or computation as taught by Hall (Para 0032-0035).
As per claim 4, Kruger discloses the system of claim 1, wherein at least one of the smart memories is enabled to post all writes at least in part by storing metadata information [Para 0047, in order to increase bandwidth speed and avoid ring stop internal data congestion, aggregated ring stop output bandwidth is higher than input bandwidth so that data may be de-queued and sent out from several output queues simultaneously. An output queue arbitration protocol guarantees that the whole data burst will be sent out before any other queue is granted. The interface logic sorts the incoming traffic according to the destination address and traffic priority, and places the data into the appropriate data input queue. All same priority queues in the input queues group are arbitrated using a round-robin algorithm on a clock-by-clock basis on the data burst boundary. High and low priority queues are arbitrated in parallel. Output queues in such a group are arbitrated in a similar fashion as input queues].
As per claim 8, Kruger discloses a method comprising:
a switch fabric communicating data between agents coupled to the switch fabric [Para 0027, the memory controller circuit 202 includes a switching matrix for routing request signals from memory clients to memory devices];
each of the agents providing backpressure information to the switch fabric [Para 0048, whenever the output queue associated with a certain source is overloaded, a back pressure signal is generated];
the switch fabric communicating the backpressure information to the agents [Para 0021, memory controller 202 includes a number of switches, such as a crossbar switching circuit for transmitting memory requests from the memory clients to the memory devices.; Para 0048, whenever the output queue associated with a certain source is overloaded, a back pressure signal is generated]; and
each of the agents responding to the backpressure information from the switch fabric by conditionally disabling providing the data to the switch fabric [Para 0048, whenever the output queue associated with a certain source is overloaded, a back pressure signal is generated. In this case, the associated input queue will be excluded from the arbitration and the rest of the queues in the input group will get extra bandwidth], and
wherein the agents comprise one or more processors and one or more smart memories [Fig. 2, controller 202, memory devices 204, client 206; Fig. 3, clients 302].
Kruger does not explicitly teach wherein the agents are enabled to autonomously initiate transactions communicated via the switch fabric.
Hall teaches wherein the agents are enabled to autonomously initiate transactions communicated via the switch fabric [Para 0032-0033, The present design includes smart compute resistive RAM to move computations and learning operations from a host system (e.g., CPU, processor, microprocessor) to smart compute resistive memory; Local processing in memory also enables some autonomy in case of poor network and safety; [Para 0038], Communication links 130-1, 130-2, 130-3, and 130-4 (e.g., high speed interconnects, PCIe) provide communications between the I/O circuitry 110, FSM 116, integrated processor 160, smart compute memory management and control circuitry 190, and smart compute memory circuitry 150; [Para 0053], The circuitry 300 provides compute functions for processing data locally within a memory subsystem without utilized a host system (e.g., main CPU 1202, processor 1227); [Para 0081], Communication links 630-1, 630-2, 630-3, and 630-4 (e.g., high speed interconnects, PCIe) provide communications between the I/O circuitry 610, FSM 616, integrated processor 660, smart compute memory management and control circuitry 690, and smart compute memory circuitry 650].
Both Kruger and Hall are in the same field of endeavor as they are both in the memory circuitry and integrated circuit art and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Kruger with the teachings of Hall in order to enable some autonomy by local processing in case of poor network and safety and compute inside the memory enables to conduct certain operation on the fly.
Modification would improve both performance and overall system power by reduce latency and improve performance in Storage Drives by doing some operations native to the Drive instead of sending data from the drive to the host system and then having the host system perform the operation or computation (Hall, Para 0032-0035).
As per claim 10, Kruger discloses the method of claim 8, further comprising each of the agents responding to the backpressure information from the switch fabric by conditionally enabling providing the data to the switch fabric [Para 0048, whenever the output queue associated with a certain source is overloaded, a back pressure signal is generated. In this case, the associated input queue will be excluded from the arbitration and the rest of the queues in the input group will get extra bandwidth].
As per claim 11, Kruger discloses the method of claim 8, further comprising each of the agents determining the backpressure information to provide to the switch fabric responsive to fullness of one or more queues of the respective agent [Para 0048, whenever the output queue associated with a certain source is overloaded, a back pressure signal is generated.].
Claim(s) 2-3, 9, 12 and 14-17, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kruger et al. (US 7,706,255 B1), Hall et al. (US 20220012063 A1) and Choi et al. (CN 114328306 A).
As per claim 2, Kruger and Hall disclose the invention as detailed above in claim 1. Kruger further discloses the system of claim 1, further comprising one or more accelerators, and wherein the point-to-point interconnect enables the accelerators to communicate with the processors and the smart memories as peers [FIG. 2, a memory controller circuit 202 provides an interconnection between a plurality of memory devices (RAM) 204 and a plurality of memory clients 206 through a crossbar, or similar switch matrix].
Kruger further discloses Para 0086, the memory controller circuit embodied on a single IC chip described herein may be implemented as functionality programmed into any of a variety of circuitry, including programmable logic devices ("PLDs"), such as field programmable gate arrays ("FPGAs").
Kruger does not specifically discuss an accelerator.
Choi discloses an accelerating module such as FPGA [Page 3, Para 6].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Kruger and Hall to include a memory controller implemented as an FPGA based accelerator as taught by Choi in order to achieve significant performance improvements for specific workloads and offer a good balance of flexibility and performance as is well known in the art.
As per claim 3, Kruger discloses the system of claim 2, wherein the processors, the smart memories, and the accelerators are enabled to communicate and respond to backpressure indicators [Para 0048, a fast response flow control (debit/credit interface) is implemented between each group of input queues and appropriate group of output queues. Whenever the output queue associated with a certain source is overloaded, a back pressure signal is generated].
As per claim 9, Kruger and Hall disclose the invention as detailed above in claim 8 above. Kruger further discloses Para 0086, the memory controller circuit embodied on a single IC chip described herein may be implemented as functionality programmed into any of a variety of circuitry, including programmable logic devices ("PLDs"), such as field programmable gate arrays ("FPGAs").
Kruger and Hall do not specifically teach the method of claim 8, wherein the agents further comprise one or more accelerators.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Kruger and Hall to include a memory controller implemented as an FPGA based accelerator in order to achieve significant performance improvements for specific workloads and offer a good balance of flexibility and performance as is well known in the art.
Claim 12 is rejected as per the rejection of claim 4 above.
As per claim 14, Kruger discloses A system, comprising:
a plurality of agents that comprise one or more processors, one or more smart memories [Fig. 2, controller 202, memory devices 204, client 206; Fig. 3, clients 302], and one or more accelerators; and
a switch fabric that enables the agents to communicate data and backpressure information amongst each other [FIG. 2, a memory controller circuit 202 provides an interconnection between a plurality of memory devices (RAM) 204 and a plurality of memory clients 206 through a crossbar, or similar switch matrix.].
Kruger does not explicitly teach wherein the processors and the smart memories are enabled to autonomously initiate transactions communicated via the point-to-point interconnect.
Hall teaches wherein the processors and the smart memories are enabled to autonomously initiate transactions communicated via the point-to-point interconnect [Para 0032-0033, The present design includes smart compute resistive RAM to move computations and learning operations from a host system (e.g., CPU, processor, microprocessor) to smart compute resistive memory; Local processing in memory also enables some autonomy in case of poor network and safety; [Para 0038], Communication links 130-1, 130-2, 130-3, and 130-4 (e.g., high speed interconnects, PCIe) provide communications between the I/O circuitry 110, FSM 116, integrated processor 160, smart compute memory management and control circuitry 190, and smart compute memory circuitry 150; [Para 0053], The circuitry 300 provides compute functions for processing data locally within a memory subsystem without utilized a host system (e.g., main CPU 1202, processor 1227); [Para 0081], Communication links 630-1, 630-2, 630-3, and 630-4 (e.g., high speed interconnects, PCIe) provide communications between the I/O circuitry 610, FSM 616, integrated processor 660, smart compute memory management and control circuitry 690, and smart compute memory circuitry 650].
Both Kruger and Hall are in the same field of endeavor as they are both in the memory circuitry and integrated circuit art and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Kruger with the teachings of Hall in order to enable some autonomy by local processing in case of poor network and safety and compute inside the memory enables to conduct certain operation on the fly.
Modification would improve both performance and overall system power by reduce latency and improve performance in Storage Drives by doing some operations native to the Drive instead of sending data from the drive to the host system and then having the host system perform the operation or computation (Hall, Para 0032-0035).
The combination of Kruger and Hall does not specifically teach the method of claim 8, wherein the agents further comprise one or more accelerators.
Kruger further discloses Para 0086, the memory controller circuit embodied on a single IC chip described herein may be implemented as functionality programmed into any of a variety of circuitry, including programmable logic devices ("PLDs"), such as field programmable gate arrays ("FPGAs").
Choi discloses an accelerating module such as FPGA [Page 3, Para 6].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Kruger and Hall to include a memory controller implemented as an FPGA based accelerator as taught by Choi in order to achieve significant performance improvements for specific workloads and offer a good balance of flexibility and performance as is well known in the art.
As per claim 15, Kruger discloses the system of claim 14, wherein each of the agents is enabled to determine and provide backpressure information to the switch fabric [Para 0048, whenever the output queue associated with a certain source is overloaded, a back pressure signal is generated].
As per claim 16, Kruger discloses the system of claim 15, wherein each of the agents is responsive to backpressure information from the switch fabric [Para 0048, whenever the output queue associated with a certain source is overloaded, a back pressure signal is generated. In this case, the associated input queue will be excluded from the arbitration and the rest of the queues in the input group will get extra bandwidth].
As per claim 17, Kruger discloses the system of claim 14, wherein at least one of the smart memories is enabled to post all writes [Para 0047, in order to increase bandwidth speed and avoid ring stop internal data congestion, aggregated ring stop output bandwidth is higher than input bandwidth so that data may be de-queued and sent out from several output queues simultaneously. An output queue arbitration protocol guarantees that the whole data burst will be sent out before any other queue is granted. The interface logic sorts the incoming traffic according to the destination address and traffic priority, and places the data into the appropriate data input queue. All same priority queues in the input queues group are arbitrated using a round-robin algorithm on a clock-by-clock basis on the data burst boundary. High and low priority queues are arbitrated in parallel. Output queues in such a group are arbitrated in a similar fashion as input queues].
As per claim 20, Choi teaches wherein the memory components comprise at least one volatile memory component and at least one non-volatile memory component [Page 3, Para 10, at least one storage device 390 may include a non-volatile memory device or some other suitable form of memory].
It is noted that memory components comprising at least one volatile memory component and at least one non-volatile is well known in the art. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Kruger with the teachings of Hall to include memory components comprise at least one volatile memory component and at least one non-volatile memory component as suggested by Choi in order to optimize the performance of the system by providing high speed and low latency of volatile memory during active processing and long-term data retention of non-volatile memory.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kruger et al. (US 7,706,255 B1), Hall et al. (US 20220012063 A1) and Connor et al. (US 11,593,292 B2).
As per claim 5, the combination of Kruger and Hall discloses the claimed invention as detailed above for claims 1 and 4 above. Kruger further discloses referencing the stored metadata information to perform serialization [Para 0047, The interface logic sorts the incoming traffic according to the destination address and traffic priority, and places the data into the appropriate data input queue. All same priority queues in the input queues group are arbitrated using a round-robin algorithm on a clock-by-clock basis on the data burst boundary. Output queues in such a group are arbitrated in a similar fashion as input queues.]
However, the combination does not specifically teach the system of claim 1, wherein at least one of the smart memories is enabled to post writes without regard to physical address, virtual address, and/or metadata associated with an address.
Connor discloses at least one of the smart memories is enabled to post writes without regard to physical address, virtual address, and/or metadata associated with an address [Col. 7, line 37 – Col. 8, line 3, Under the illustrated architecture, a NIC initiating a PCIe memory write transaction is agnostic to where the physical location of the memory cache line(s) that is/are to be written to… The routing of PCIe memory write transaction packets is configured such that packets are forwarded to the NUMA node via which the portion of system memory address space corresponding to the transaction's destination address can be accessed, regardless of whether the initiating device (or the transaction) is logically associated with that NUMA node or another NUMA node]. It is noted that address agnostic typically means that a system or component can operate without being tied to a specific memory address or location as is well known in the art.
Kruger, Hall and Connor are in the same field of endeavor and they are in the computer architecture using peripheral switches art and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Kruger and Hall with the teachings of Connor in order to enable writes without regard to traditional addressing.
Modification would improve and facilitate the handling and forwarding of data received via packets from the network to consumers of that data as taught by Connor (Col. 5, lines 27-30).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kruger et al. (US 7,706,255 B1), Hall et al. (US 20220012063 A1) and Choi et al. (CN 114328306 A) and further in view of Connor et al. (US 11,593,292 B2).
As per claim 18, the combination of Kruger, Hall and Choi discloses the claimed invention as detailed above for claims 14 and 17 above. Kruger further discloses referencing the stored metadata information to perform serialization [Para 0047, The interface logic sorts the incoming traffic according to the destination address and traffic priority, and places the data into the appropriate data input queue. All same priority queues in the input queues group are arbitrated using a round-robin algorithm on a clock-by-clock basis on the data burst boundary. Output queues in such a group are arbitrated in a similar fashion as input queues.]
However, the combination does not specifically teach the system of claim 1, wherein at least one of the smart memories is enabled to post writes without regard to physical address, virtual address, and/or metadata associated with an address.
Connor discloses at least one of the smart memories is enabled to post writes without regard to physical address, virtual address, and/or metadata associated with an address [Col. 7, line 37 – Col. 8, line 3, Under the illustrated architecture, a NIC initiating a PCIe memory write transaction is agnostic to where the physical location of the memory cache line(s) that is/are to be written to… The routing of PCIe memory write transaction packets is configured such that packets are forwarded to the NUMA node via which the portion of system memory address space corresponding to the transaction's destination address can be accessed, regardless of whether the initiating device (or the transaction) is logically associated with that NUMA node or another NUMA node]. It is noted that address agnostic typically means that a system or component can operate without being tied to a specific memory address or location as is well known in the art.
Kruger, Hall, Choi and Connor are in the same field of endeavor and they are in the computer architecture using peripheral switches art and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Kruger, Hall and Choi with the teachings of Connor in order to enable writes without regard to traditional addressing.
Modification would improve and facilitate the handling and forwarding of data received via packets from the network to consumers of that data as taught by Connor (Col. 5, lines 27-30).
Claim(s) 6 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kruger et al. (US 7,706,255 B1), Hall et al. (US 20220012063 A1) and Mosiolek et al. (US20170255565 A1).
As per claim 6, the combination of Kruger and Hall discloses the claimed invention as detailed above for claim 1. The combination of Kruger and Hall does not specifically teach wherein at least one of the smart memories is enabled to map a plurality of non-contiguous physical addresses of one or more memory components into a contiguous physically addressable region.
Mosiolek et al. teaches wherein at least one of the smart memories is enabled to map a plurality of non-contiguous physical addresses of one or more memory components into a contiguous physically addressable region [Para 0040-0041, At 206, the operating system determines that defragmentation of the externally addressable address space is used in order allocate the requested contiguously addressable memory region. In various embodiments, the operating system may be agnostic as to whether a location change command results in the data region being physically moved within the memory 116 (which in some embodiments could include maintaining the source region for eventual overwriting) or whether the memory device 106 performs remapping of a portion of the externally addressable address space to the physical address space (without moving the underlying data stored in memory) in order to allow the operating system to use a different set of addresses to reference the data region.].
Kruger, Hall and Mosiolek are in the same field of endeavor and they are in the computer architecture using peripheral switches art and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Kruger and Hall with the teachings of Mosiolek to include mapping a plurality of non-contiguous physical addresses of one or more memory components into a contiguous physically addressable region in order to reduce the wastage of memory caused by internal and external fragmentation.
Modification would improve efficiency and performance of the system by achieving simplifying memory management, enabling efficient memory allocation, and enhancing security through process isolation as is well known in the art.
Claim 13 is rejected as per the rejection of claim 6 above.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kruger et al. (US 7,706,255 B1), Hall et al. (US 20220012063 A1), Choi et al. (CN 114328306 A) and Mosiolek et al. (US20170255565 A1).
As per claim 19, the combination of Kruger and Hall discloses the claimed invention as detailed above for claim 14. The combination of Kruger, Hall and Choi does not specifically teach wherein at least one of the smart memories is enabled to map a plurality of non-contiguous physical addresses of one or more memory components into a contiguous physically addressable region.
Mosiolek et al. teaches wherein at least one of the smart memories is enabled to map a plurality of non-contiguous physical addresses of one or more memory components into a contiguous physically addressable region [Para 0040-0041, At 206, the operating system determines that defragmentation of the externally addressable address space is used in order allocate the requested contiguously addressable memory region. In various embodiments, the operating system may be agnostic as to whether a location change command results in the data region being physically moved within the memory 116 (which in some embodiments could include maintaining the source region for eventual overwriting) or whether the memory device 106 performs remapping of a portion of the externally addressable address space to the physical address space (without moving the underlying data stored in memory) in order to allow the operating system to use a different set of addresses to reference the data region.].
Kruger, Hall and Mosiolek are in the same field of endeavor and they are in the computer architecture using peripheral switches art and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Kruger, Hall and Choi with the teachings of Mosiolek to include mapping a plurality of non-contiguous physical addresses of one or more memory components into a contiguous physically addressable region in order to reduce the wastage of memory caused by internal and external fragmentation.
Modification would improve efficiency and performance of the system by achieving simplifying memory management, enabling efficient memory allocation, and enhancing security through process isolation as is well known in the art.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kruger et al. (US 7,706,255 B1), Hall et al. (US 20220012063 A1), Mosiolek et al. (US20170255565 A1) and Choi et al. (CN 114328306 A).
As per claim 7, the combination of Kruger, Hall and Mosiolek discloses the claimed invention as detailed above for claim 6. The combination of Kruger, Hall and Mosiolek does not specifically teach discloses the system of claim 6, wherein the memory components comprise at least one volatile memory component and at least one non-volatile memory component.
Choi teaches wherein the memory components comprise at least one volatile memory component and at least one non-volatile memory component [Page 3, Para 10, at least one storage device 390 may include a non-volatile memory device or some other suitable form of memory].
It is noted that memory components comprising at least one volatile memory component and at least one non-volatile is well known in the art. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Kruger with the teachings of Hall to include memory components comprise at least one volatile memory component and at least one non-volatile memory component as suggested by Choi in order to optimize the performance of the system by providing high speed and low latency of volatile memory during active processing and long-term data retention of non-volatile memory.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US20190171565 A1 to Bowen-Huggett teaches physical memory space 100, but additionally shows four regions (explained later herein), each region comprising a physically contiguous set of segments. The four regions of physically continuous segments in the physical memory space are mapped to the addressable space to form a contiguous group of regions [Para 0017-0019].
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Examiner has cited particular columns/paragraphs/sections and line numbers in the references applied and not relied upon to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
When responding to the Office action, applicant is advised to clearly point out the patentable novelty the claims present in view of the state of the art disclosed by the reference(s) cited or the objections made. A showing of how the amendments avoid such references or objections must also be present. See 37 C.F.R. 1.111(c).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Pierre M. Vital whose telephone number is (571)272-4215. The examiner can normally be reached Mon-Fri, 8:00a-4:00p.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dede Zecher can be reached at (571) 272-7771. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
April 21, 2026
/PIERRE VITAL/Supervisory Patent Examiner, Art Unit 2198
Prosecution Insights