DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to the request for continued examination filed 27 April 2026.
Claims 1-20 are pending and have been presented for examination.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 27 April 2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 10 and 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 10 ,19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over ASANO (U.S. Patent Application Publication #2020/0073795) in view of KOO (U.S. Patent Application Publication #2019/0018767) and LI (U.S. Patent #10,748,619).
1. ASANO discloses A device (see [0068]: controller and NAND flash memory), comprising: a plurality of planes of memory cells (see KOO below); and a circuit operable to program data into the memory cells according to a plurality of options (see [0079]: NAND controller) and configured to: receive a command to write data (see [0077]: write command from host), wherein the command does not specify a mode to program the memory cells to write the data (see [0095]: write mode is selected based on write bandwidth, the write command does not specify a mode to program the memory cells); and determine, in response to the command, a combination of: a media layout to store, via a programming operation, an amount of data (see [0095]: based on the write bandwidth, data is written in a first mode or second mode; [0161]: write bandwidth is calculated by the controller by measuring the amount of data received per time period) in first planes selected from the plurality of planes (see KOO below); and first options of the programming operation in the first planes, wherein the amount is based on the first options (see LI below).
KOO discloses the following limitations that are not disclosed by ASANO: a plurality of planes of memory cells (see [0041]: memory die includes a plane, a plane being a group of memory blocks that can be programmed in parallel) and programming data in first planes selected from the plurality of planes (see [0051]: selection of pages to program based on data size). ASANO already discloses operating memory dies in parallel (see ASANO [0108]). KOO discloses a memory architecture that allows for groups of memory blocks to be programmed in parallel, this group of blocks is a plane. A memory device with multiple planes allows for an increase of data throughput (see [0044]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify ASANO to have a plurality of planes of memory cells, as disclosed by KOO. One of ordinary skill in the art would have been motivated to make such a modification to increase the throughput of the memory device, as taught by KOO. ASANO and KOO are analogous/in the same field of endeavor as both references are directed to managing data writes to flash memory.
ASANO discloses determining one option in response to the command. ASANO selects programming in SLC mode or MLC mode as an option based on the write data bandwidth. The claim recites “first options”. LI discloses the following limitations that are not disclosed by ASANO: determine first options of the programming operation in the first planes (see column 5, lines 37-52: parameters loaded into a state machine that are used for performing a memory operation, these parameters specify a number of bits per cell and an address, the parameters are provided with each command sequence; column 20, lines 55-60: parameters for M or N-bit per cell programming; column 21, lines 55-60: back and forth word line programming order). The programming options allow a host to configure a state machine that is part of a memory controller with different programming options. This provides faster testing of a block and application flexibility by an application for storage densities on different word lines (see column 21, lines 60-65).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify ASANO to determine first options for programming, as disclosed by LI. One of ordinary skill in the art would have been motivated to make such a modification to provide flexibility and faster testing of memory blocks, as taught by LI. ASANO and LI are analogous/in the same field of endeavor as both references are directed to selecting options for programming data in a flash memory block.
10. ASANO discloses A method, comprising: programming, by a device (see [0068]: NAND controller and flash memory) having a plurality of planes of memory cells (see KOO below), data into the memory cells according to a plurality of options (see [0143]: write mode based on write data bandwidth; [0078]: logical address of data); receiving, in the device, a command to write data (see [0077]: write command from host); and determining, by the device in response to the command and without the command specifying a mode to program memory cells in executing the command (see [0095]: write mode is selected based on write bandwidth, the write command does not specify a mode to program the memory cells), a combination of: a media layout to store, via a programming operation, an amount of data (see [0095]: based on the write bandwidth, data is written in a first mode or second mode; [0161]: write bandwidth is calculated by the controller by measuring the amount of data received per time period) in first planes selected from the plurality of planes (see KOO below); and first options of the programming operation in the first planes, wherein the amount is based on the first options (see LI below).
KOO discloses the following limitations that are not disclosed by ASANO: a plurality of planes of memory cells (see [0041]: memory die includes a plane, a plane being a group of memory blocks that can be programmed in parallel) and programming data in first planes selected from the plurality of planes (see [0051]: selection of pages to program based on data size). ASANO already discloses operating memory dies in parallel (see ASANO [0108]). KOO discloses a memory architecture that allows for groups of memory blocks to be programmed in parallel, this group of blocks is a plane. A memory device with multiple planes allows for an increase of data throughput (see [0044]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify ASANO to have a plurality of planes of memory cells, as disclosed by KOO. One of ordinary skill in the art would have been motivated to make such a modification to increase the throughput of the memory device, as taught by KOO. ASANO and KOO are analogous/in the same field of endeavor as both references are directed to managing data writes to flash memory.
ASANO discloses determining one option in response to the command. ASANO selects programming in SLC mode or MLC mode as an option based on the write data bandwidth. The claim recites “first options”. LI discloses the following limitations that are not disclosed by ASANO: determine first options of the programming operation in the first planes (see column 5, lines 37-52: parameters loaded into a state machine that are used for performing a memory operation, these parameters specify a number of bits per cell and an address, the parameters are provided with each command sequence; column 20, lines 55-60: parameters for M or N-bit per cell programming; column 21, lines 55-60: back and forth word line programming order). The programming options allow a host to configure a state machine that is part of a memory controller with different programming options. This provides faster testing of a block and application flexibility by an application for storage densities on different word lines (see column 21, lines 60-65).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify ASANO to determine first options for programming, as disclosed by LI. One of ordinary skill in the art would have been motivated to make such a modification to provide flexibility and faster testing of memory blocks, as taught by LI. ASANO and LI are analogous/in the same field of endeavor as both references are directed to selecting options for programming data in a flash memory block.
19. ASANO discloses A non-transitory computer storage medium storing instructions (see [0263]: processor executes instructions stored in a memory) which, when executed in a device (see [0068]: NAND controller and flash memory) having a plurality of planes of memory cells (see KOO below), causes the device to perform a method, comprising: programming data into the memory cells according to a plurality of options (see [0143]: write mode based on write data bandwidth; [0078]: logical address of data); receiving a command to write data (see [0077]: write command from host) without specifying a mode to program the memory cells in execution of the command (see [0095]: write mode is selected based on write bandwidth, the write command does not specify a mode to program the memory cells); and determining, in response to the command, a combination of: a media layout to store, via a programming operation, an amount of data (see [0095]: based on the write bandwidth, data is written in a first mode or second mode; [0161]: write bandwidth is calculated by the controller by measuring the amount of data received per time period) in first planes selected from the plurality of planes (see KOO below); and first options of the programming operation in the first planes, wherein the amount is based on the first options (see LI below).
KOO discloses the following limitations that are not disclosed by ASANO: a plurality of planes of memory cells (see [0041]: memory die includes a plane, a plane being a group of memory blocks that can be programmed in parallel) and programming data in first planes selected from the plurality of planes (see [0051]: selection of pages to program based on data size). ASANO already discloses operating memory dies in parallel (see ASANO [0108]). KOO discloses a memory architecture that allows for groups of memory blocks to be programmed in parallel, this group of blocks is a plane. A memory device with multiple planes allows for an increase of data throughput (see [0044]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify ASANO to have a plurality of planes of memory cells, as disclosed by KOO. One of ordinary skill in the art would have been motivated to make such a modification to increase the throughput of the memory device, as taught by KOO. ASANO and KOO are analogous/in the same field of endeavor as both references are directed to managing data writes to flash memory.
ASANO discloses determining one option in response to the command. ASANO selects programming in SLC mode or MLC mode as an option based on the write data bandwidth. The claim recites “first options”. LI discloses the following limitations that are not disclosed by ASANO: determine first options of the programming operation in the first planes (see column 5, lines 37-52: parameters loaded into a state machine that are used for performing a memory operation, these parameters specify a number of bits per cell and an address, the parameters are provided with each command sequence; column 20, lines 55-60: parameters for M or N-bit per cell programming; column 21, lines 55-60: back and forth word line programming order). The programming options allow a host to configure a state machine that is part of a memory controller with different programming options. This provides faster testing of a block and application flexibility by an application for storage densities on different word lines (see column 21, lines 60-65).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify ASANO to determine first options for programming, as disclosed by LI. One of ordinary skill in the art would have been motivated to make such a modification to provide flexibility and faster testing of memory blocks, as taught by LI. ASANO and LI are analogous/in the same field of endeavor as both references are directed to selecting options for programming data in a flash memory block.
20. The non-transitory computer storage medium of claim 19, wherein the first options are selected from: programming a page in a single level cell (SLC) mode; programming the page in a multi-level cell (MLC) mode; programming the page in a triple level cell (TLC) mode; programming the page in a quad-level cell (QLC) mode (see ASANO [0051], [0059]); programming the page using a single pass programming technique; or programming the page using a multi-pass programming technique; or any combination thereof (see LI column 21, lines 55-65: some word lines are programmed in a single pass and others are programmed in a multi-pass).
Claim(s) 2-9 and 11-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over ASANO (U.S. Patent Application Publication #2020/0073795), KOO (U.S. Patent Application Publication #2019/0018767) and LI (U.S. Patent #10,748,619) as applied to claims 1, 10, 19 and 20 above, and further in view of LIN (U.S. Patent Application Publication #2013/0262745).
2. The device of claim 1 (see ASANO above), wherein the first planes are selected based on a determination that the first planes are available to program data in parallel for the command (see LIN below).
LIN discloses the following limitations that are not disclosed by ASANO: wherein the first planes are selected based on a determination that the first planes are available to program data in parallel for the command (see [0041]: re-order commands in the queue to allow for parallel execution). Commands can be performed more rapidly because of parallel execution in different planes (see [0039]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify ASANO to select planes available to program data in parallel, as disclosed by LIN. One of ordinary skill in the art would have been motivated to make such a modification to perform the commands more rapidly, as taught by LIN. ASANO and LIN are analogous/in the same field of endeavor as both references are directed to programming data in parallel in a memory system.
3. The device of claim 2, wherein the command identifies a size of data to be written into the device (see ASANO [0161]: write amount); and the circuit is further configured to determine the media layout and the first options based on matching the amount to the size (see ASANO [0162]-[0167]: write mode is selected based on the amount of data received within the time period).
4. The device of claim 3, wherein the circuit is further configured to receive, in response to the command, data to be programmed based on the amount determined for the media layout without buffering excessive data not to be programmed during the programming operation (see ASANO [0089]: selection of write mode to reduce the amount of data stored in the buffer).
5. The device of claim 3, wherein the programming operation is an atomic write operation (see ASANO [0080]-[0083]: host receives a write complete response when data is stored in DRAM, the DRAM is protected from power loss).
6. (Original) The device of claim 5, wherein each of the first options is selected from: programming a page in a single level cell (SLC) mode; programming the page in a multi-level cell (MLC) mode; programming the page in a triple level cell (TLC) mode; or programming the page in a quad-level cell (QLC) mode (see ASANO [0051], [0059]).
7. The device of claim 6, wherein each of the first options is further selected from: programming the page using a single pass programming technique; or programming the page using a multi-pass programming technique (see LI column 21, lines 55-65: some word lines are programmed in a single pass and others are programmed in a multi-pass).
8. The device of claim 7, wherein the first options includes: programming a first page in the first planes using the single pass programming technique; and programming a second page in the first planes using the multi-pass programming technique (see LI column 21, lines 55-65: some word lines are programmed in a single pass and others are programmed in a multi-pass).
9. The device of claim 7, wherein the first options includes programming two pages in the first planes using at least two different modes of: the single level cell (SLC) mode; the multi-level cell (MLC) mode; the triple level cell (TLC) mode; and the quad-level cell (QLC) mode (see ASANO [0096]-[0098]: as the write bandwidth changes the mode of programming will change, this will result in data being programmed with different densities in the memory planes).
11. The method of claim 10 (see ASANO above), wherein the first planes are selected based on a determination that the first planes are available to program data in parallel for the command (see LIN below).
LIN discloses the following limitations that are not disclosed by ASANO: wherein the first planes are selected based on a determination that the first planes are available to program data in parallel for the command (see [0041]: re-order commands in the queue to allow for parallel execution). Commands can be performed more rapidly because of parallel execution in different planes (see [0039]).
It would have been obvious, before the effective filing date of the claimed invention, to a person having ordinary skill in the art to which said subject matter pertains to modify ASANO to select planes available to program data in parallel, as disclosed by LIN. One of ordinary skill in the art would have been motivated to make such a modification to perform the commands more rapidly, as taught by LIN. ASANO and LIN are analogous/in the same field of endeavor as both references are directed to programming data in parallel in a memory system.
12. The method of claim 11, wherein the command identifies a size of data to be written into the device (see ASANO [0161]: write amount); and the media layout and the first options are determined based on matching the amount to the size (see ASANO [0162]-[0167]: write mode is selected based on the amount of data received within the time period).
13. The method of claim 12, further comprising: receiving, by the device in response to the command, data to be programmed based on the amount determined for the media layout without buffering excessive data not to be programmed during the programming operation (see ASANO [0089]: selection of write mode to reduce the amount of data stored in the buffer).
14. The method of claim 12, wherein the programming operation is an atomic write operation (see ASANO [0080]-[0083]: host receives a write complete response when data is stored in DRAM, the DRAM is protected from power loss).
15. The method of claim 14, wherein each of the first options is selected from: programming a page in a single level cell (SLC) mode; programming the page in a multi-level cell (MLC) mode; programming the page in a triple level cell (TLC) mode; or programming the page in a quad-level cell (QLC) mode (see ASANO [0051], [0059]).
16. The method of claim 15, wherein each of the first options is further selected from: programming the page using a single pass programming technique; or programming the page using a multi-pass programming technique (see LI column 21, lines 55-65: some word lines are programmed in a single pass and others are programmed in a multi-pass).
17. The method of claim 16, wherein the first options includes: programming a first page in the first planes using the single pass programming technique; and programming a second page in the first planes using the multi-pass programming technique (see LI column 21, lines 55-65: some word lines are programmed in a single pass and others are programmed in a multi-pass).
18. The method of claim 16, wherein the first options includes programming two pages in the first planes using at least two different modes of: the single level cell (SLC) mode; the multi-level cell (MLC) mode; the triple level cell (TLC) mode; and the quad-level cell (QLC) mode (see ASANO [0096]-[0098]: as the write bandwidth changes the mode of programming will change, this will result in data being programmed with different densities in the memory planes).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
KANNO [10,861,580] discloses parallel writes to multiple planes in a memory device. [Claim 7]
HUNG [2019/0018598] discloses dynamically switching between write modes for flash memory based on the number of spare blocks and the size of the write data. [0022]-[0028]
KIMURA [2018/0267719]: discloses selection of a write mode for flash memory based on a type of data received. [0076]-[0087]
KIM [2013/0275657] discloses the benefits of multi-plane writing. [0066]
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD J DUDEK JR whose telephone number is (571)270-1030. The examiner can normally be reached Monday - Friday, 8:00A-4:00P.
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/EDWARD J DUDEK JR/Primary Examiner, Art Unit 2132
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