DETAILED ACTION
This action is responsive to the application filed 25 Jul 2024. Claims 1-21 are pending. Claims 1, 11, and 17 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Application Title
The Examiner proposes the below Application Title change in accordance with MPEP 606.01 and MPEP 1302.04(a) to improve the descriptive nature of the title. The Applicant can suggest an alternative title if desired. The Application Title should be changed to the following:
“WORD LINE VOLTAGE CONTROL USING TRANSISTOR SENSING”
No action is required by the applicant. If an allowance is processed, the Examiner will change the name as part of the Examiner’s Amendment process.
Allowable Subject Matter
Claim 21 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim(s) 10 and 16 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim(s) 10 and 16 state(s), “the second voltage comprises the first voltage and a third voltage associated with activating the second stage of decoding circuitry.” It is indefinite how a “voltage” comprises another voltage. Voltages can be driven by voltages; voltages can be equal to other voltages; voltages can be based on other voltages; voltages can be added or subtracted from other voltages. It is unknown and indefinite how a voltage is comprised of other voltages.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 8 – 12, 14, and 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by YU, H., U.S. Patent Application Publication 2024/0136008 (“YU”).
Regarding claim 1, YU teaches:
A memory device, comprising: a memory array comprising a plurality of word lines operable to couple with a plurality of memory cells; and decoding circuitry coupled with the memory array and configured to activate the plurality of word lines, the decoding circuitry comprising: (YU, fig 5, 6, “[0013] FIG. 1 is a schematic diagram of a memory device 100 in accordance with some embodiments. The memory device 100 may include a memory array 110, a reference voltage generator 120, a driver circuit 130 and a memory controller 140.”; a memory device with a controller, voltage generator, drivers, plural wordlines, plural bitlines, and memory cells).
one or more first transistors coupled with one or more word lines of the plurality of word lines and configured to a sense a first voltage associated with the one or more word lines; (YU, fig 5, 6, “[0037] FIG. 5 is a schematic diagram illustrating a driver circuit 130 in accordance with some embodiments. The reference voltage Vref that is inputted to the driver circuit 130 is generated based on at least one of the reference signals Vrefl or Vref2. … the driver circuit 130 may generate at least one of the word line voltage or the bit line voltage for the at least one memory cell based on at least one of the threshold voltage of the at least one memory cell. [0038] In some embodiments, the driver circuit 130 includes an operational amplifier 132, a transistor 134, a voltage divider circuit 136 and a word line driver 138.”; a transistor 134 that is coupled to the wordline driver 138).
a first stage of the decoding circuitry coupled with the one or more first transistors and configured to: compare the first voltage with a target word line activation voltage; and (YU, fig 5, 6, “[0038] The operational amplifier 132 may receive the reference signal Vref and a feedback voltage V from an output of the transistor 134 through the voltage divider circuit 136. The operational amplifier 132 is configured to generate an error signal that represents a difference between the reference signal Vref and the feedback voltage V.”; a “first stage” comprising the transistor 134 and op amp 132; the op amp compares the incoming word line voltage to a reference voltage).
output, to a second stage of the decoding circuitry, a second voltage based at least in part on comparison of the first voltage with the target word line activation voltage; and (YU, fig 5, 6, “[0038] The generated error signal is provided to a control terminal of the transistor 134 to control operations of the transistor 134. In some embodiments, the transistor 134 is configured to generate the at least one of the word line voltage V RWL or the bit line voltage V RBL based on the error signal outputted by the operational amplifier 132.”; the output of the op amp is fed back into transistor 134 which transmits the V RWL, the word line voltage to the word line driver 138 as the second stage).
a second stage of the decoding circuitry coupled with the first stage of the decoding circuitry and the one or more word lines, the second stage of the decoding circuitry configured to activate the one or more word lines based at least in part on the second voltage. (YU, fig 5, 6, “[0041] The word line driver 138 is coupled to the output of the transistor 134 to receive the word line voltage V RWL or the bit line voltage V RBv and is configured to drive at least one memory cells of a memory array (e.g., memory array 110 in FIG. 1) using the word line voltage V RWL or the bit line voltage V RBL·”; the word line driver 138 (second stage) is controlled by the op amp 132 (first stage) to drive the word line voltages (activate a word line)).
Regarding claim 8, YU teaches The memory device of claim 1, wherein the second voltage is associated with activating one or more of the first stage of the decoding circuitry, a second stage of the decoding circuitry, or the one or more word lines. (YU, fig 5, 6, “[0038] The generated error signal is provided to a control terminal of the transistor 134 to control operations of the transistor 134. In some embodiments, the transistor 134 is configured to generate the at least one of the word line voltage V RWL or the bit line voltage V RBL based on the error signal outputted by the operational amplifier 132.”; the output of the op amp is fed back into transistor 134 which transmits the V RWL, the word line voltage to the word line driver 138 as the second stage; that the “second voltage” output from the op amp is “associated with’ both with activating the first op amp and driving the second stage).
Regarding claim 9, YU teaches The memory device of claim 1, wherein the plurality of word lines are operable to activate the plurality of memory cells based at least in part on the second voltage. (YU, fig 2, 3, “[0020] In some embodiments, the driver circuit 130 is coupled to the reference voltage generator 120, and is configured to generate at least one of a bit line voltage or a word line voltage based on the reference signal Vref. The generated bit line voltage is applied to selected bit lines of the memory array 110 when performing the memory operations. The generated word line voltage is applied to the selected word lines when performing the memory operations.”; that the voltage drive can be used to activate plural word lines).
Regarding claim 10, YU teaches The memory device of claim 1, wherein the second voltage comprises the first voltage and a third voltage associated with activating the second stage of decoding circuitry. (YU, fig 5, 6, “[0041] The word line driver 138 is coupled to the output of the transistor 134 to receive the word line voltage V RWL or the bit line voltage V RBv and is configured to drive at least one memory cells of a memory array (e.g., memory array 110 in FIG. 1) using the word line voltage V RWL or the bit line voltage V RBL·”; the word line driver 138 (second stage) is controlled by the op amp 132 (first stage and first voltage) to drive the word line voltages (activate a word line); that the word lines are driven to a third voltage out of op amp 138).
Regarding claim 11, YU teaches:
A method by a memory device, comprising: (YU, fig 5, 6, “[0013] FIG. 1 is a schematic diagram of a memory device 100 in accordance with some embodiments. The memory device 100 may include a memory array 110, a reference voltage generator 120, a driver circuit 130 and a memory controller 140.”; a memory device with a controller, voltage generator, drivers, plural wordlines, plural bitlines, and memory cells).
sensing, by one or more first transistors, a first voltage associated with one or more word lines of a memory array; (YU, fig 5, 6, “[0037] FIG. 5 is a schematic diagram illustrating a driver circuit 130 in accordance with some embodiments. The reference voltage Vref that is inputted to the driver circuit 130 is generated based on at least one of the reference signals Vrefl or Vref2. … the driver circuit 130 may generate at least one of the word line voltage or the bit line voltage for the at least one memory cell based on at least one of the threshold voltage of the at least one memory cell. [0038] In some embodiments, the driver circuit 130 includes an operational amplifier 132, a transistor 134, a voltage divider circuit 136 and a word line driver 138.”; a transistor 134 that is coupled to the wordline driver 138).
comparing, by a first stage of decoding circuitry based at least in part on the first voltage, the first voltage with a target word line activation voltage; and (YU, fig 5, 6, “[0038] The operational amplifier 132 may receive the reference signal Vref and a feedback voltage V from an output of the transistor 134 through the voltage divider circuit 136. The operational amplifier 132 is configured to generate an error signal that represents a difference between the reference signal Vref and the feedback voltage V.”; a “first stage” comprising the transistor 134 and op amp 132; the op amp compares the incoming word line voltage to a reference voltage).
outputting, by the first stage of decoding circuitry based at least in part on comparing the first voltage with a target word line activation voltage, a second voltage to a second stage of decoding circuitry, (YU, fig 5, 6, “[0038] The generated error signal is provided to a control terminal of the transistor 134 to control operations of the transistor 134. In some embodiments, the transistor 134 is configured to generate the at least one of the word line voltage V RWL or the bit line voltage V RBL based on the error signal outputted by the operational amplifier 132.”; the output of the op amp is fed back into transistor 134 which transmits the V RWL, the word line voltage to the word line driver 138 as the second stage).
the second voltage associated with activating one or more of the first stage of decoding circuitry, the second stage of decoding circuitry, or the one or more word lines of the memory array. (YU, fig 5, 6, “[0041] The word line driver 138 is coupled to the output of the transistor 134 to receive the word line voltage V RWL or the bit line voltage V RBv and is configured to drive at least one memory cells of a memory array (e.g., memory array 110 in FIG. 1) using the word line voltage V RWL or the bit line voltage V RBL·”; the word line driver 138 (second stage) is controlled by the op amp 132 (first stage) to drive the word line voltages (activate a word line)).
Regarding claim 12, YU teaches:
The method of claim 11, further comprising: transmitting, from the one or more first transistors to the first stage of decoding circuitry, the first voltage based at least in part on sensing the first voltage, (YU, fig 5, 6, “[0037] FIG. 5 is a schematic diagram illustrating a driver circuit 130 in accordance with some embodiments. The reference voltage Vref that is inputted to the driver circuit 130 is generated based on at least one of the reference signals Vrefl or Vref2. … the driver circuit 130 may generate at least one of the word line voltage or the bit line voltage for the at least one memory cell based on at least one of the threshold voltage of the at least one memory cell. [0038] In some embodiments, the driver circuit 130 includes an operational amplifier 132, a transistor 134, a voltage divider circuit 136 and a word line driver 138.”; a transistor 134 that is coupled to the wordline driver 138, the transistor senses the voltage input at the top of transistor 134 and at the top of the voltage splitter R1/ R2 from the V-rwl).
wherein comparing the first voltage with the target word line activation voltage is based at least in part on receiving the first voltage at the first stage of decoding circuitry. (YU, fig 5, 6, “[0038] The operational amplifier 132 may receive the reference signal Vref and a feedback voltage V from an output of the transistor 134 through the voltage divider circuit 136. The operational amplifier 132 is configured to generate an error signal that represents a difference between the reference signal Vref and the feedback voltage V.”; a “first stage” comprising the transistor 134 and op amp 132; the op amp compares the incoming word line voltage from the bottom of transistor 134 with a VREF reference voltage; the hi/ low nature of the voltage at R1/ R2 is used to drive the comparator 132).
Regarding claim 14, YU teaches The method of claim 11, further comprising: activating, by the second stage of decoding circuitry, the one or more word lines based at least in part on receiving the second voltage from the first stage of decoding circuitry. (YU, fig 5, 6, “[0041] The word line driver 138 is coupled to the output of the transistor 134 to receive the word line voltage V RWL or the bit line voltage V RBv and is configured to drive at least one memory cells of a memory array (e.g., memory array 110 in FIG. 1) using the word line voltage V RWL or the bit line voltage V RBL·”; the word line driver 138 (second stage) is controlled by the op amp 132 (first stage) to drive the word line voltages (activate a word line) based on the second voltage received from the op amp 132).
Regarding claim 16, YU teaches The method of claim 11, wherein the second voltage comprises the first voltage and a third voltage associated with activating the second stage of decoding circuitry. (YU, fig 5, 6, “[0041] The word line driver 138 is coupled to the output of the transistor 134 to receive the word line voltage V RWL or the bit line voltage V RBv and is configured to drive at least one memory cells of a memory array (e.g., memory array 110 in FIG. 1) using the word line voltage V RWL or the bit line voltage V RBL·”; the word line driver 138 (second stage) is controlled by the op amp 132 (first stage and first voltage) to drive the word line voltages (activate a word line); that the word lines are driven to a third voltage out of op amp 138).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 2 – 5, 7, 13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over YU in view of Ooishi, et al, U.S. Patent Application Publication 2004/0027908 (“Ooishi”).
Regarding claim 2, YU teaches the memory device of claim 1.
YU teaches wherein the first stage of the decoding circuitry comprises: an amplifier coupled with the one or more first transistors, the amplifier configured to output the second voltage based at least in part on the comparison of the first voltage and the target word line activation voltage; and (YU, fig 5, 6, “[0038] The operational amplifier 132 may receive the reference signal Vref and a feedback voltage V from an output of the transistor 134 through the voltage divider circuit 136. The operational amplifier 132 is configured to generate an error signal that represents a difference between the reference signal Vref and the feedback voltage V. [0041] A structure of the word line drive 138 is not limited in the disclosure. Any circuit structure that may drive the word lines of a memory device using the at least one of the word line voltage V RWL or the line voltage V RBL falls within the scope of the disclosure.”; a “first stage” comprising the transistor 134 and op amp 132; the op amp compares the incoming word line voltage to a reference voltage in the first stage, that the word line driver 138 can be “any circuit structure”).
YU does not explicitly teach a second transistor coupled with an output of the amplifier and the second stage of the decoding circuitry, the second transistor configured to supply the second voltage to the second stage of the decoding circuitry.
Ooishi teaches a second transistor coupled with an output of the amplifier and the second stage of the decoding circuitry, the second transistor configured to supply the second voltage to the second stage of the decoding circuitry. (Ooishi, fig 2, 3, “[0088] Word line driver 82 includes a P channel MOS transistor 83 connected between a power supply voltage Vcc# and one end of a corresponding word line WL, and an N channel MOS transistor 84 connected between ground voltage GND and that one end of the corresponding word line WL.”; that wordline drivers in semiconductor devices routinely incorporate transistors).
In view of the teachings of Ooishi it would have been obvious for a person of ordinary skill in the art to apply the teachings of Ooishi to YU before the effective filing date of the claimed invention in order to teach memory circuits. The teachings of Ooishi, in the same or in a similar field of endeavor with YU, can combine Ooishi’s explicit transistors in wordline drivers and YU implied transistors in a wordline driver. The two wordline drivers merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 3, YU, as modified by Ooishi, teaches the memory device of claim 2.
Ooishi further teaches wherein the second transistor is further configured to: output the second voltage to the second stage of the decoding circuitry based at least in part on a supply voltage applied to a source of the second transistor and the second voltage applied to a gate of the second transistor. (Ooishi, fig 2, 3, “[0088] Word line driver 82 includes a P channel MOS transistor 83 connected between a power supply voltage Vcc# and one end of a corresponding word line WL, and an N channel MOS transistor 84 connected between ground voltage GND and that one end of the corresponding word line WL. Transistors 83 and 84 each have the gate receiving a corresponding decode signal Rd. In the selected memory cell row, transistor 83 is turned on while transistor 84 is turned off to connect word line WL to supply voltage Vcc# and activate the word line to H level. In each of other memory cell rows, transistor 84 is turned on and transistor 83 is turned off to connect word line WL to ground voltage GND and inactivate the word line to L level.”; that wordline drivers in semiconductor devices routinely incorporate transistors; that the input from the claimed first stage can be tied to a gate of said transistors 83 and 84, that the drain and source can be connected to a power source and gnd respectively).
In view of the teachings of Ooishi it would have been obvious for a person of ordinary skill in the art to apply the teachings of Ooishi to YU before the effective filing date of the claimed invention in order to teach memory circuits. The teachings of Ooishi, in the same or in a similar field of endeavor with YU, can combine Ooishi’s explicit transistors in wordline drivers and YU implied transistors in a wordline driver. The two wordline drivers merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 4, YU, as modified by Ooishi, teaches the memory device of claim 2.
Ooishi further teaches wherein the amplifier is further configured to: store an indication of the second voltage. (Ooishi, fig 2, 3, “[0086] Referring to FIG. 3, address latch circuit 15a includes a plurality of latch units 90 respectively provided correspondingly to the bits of row address RA. Each latch unit 90 takes in a corresponding bit of row address RA in response to an activation edge of clock signal CLK to temporarily hold that bit. Word line selection unit 81a decodes the bits of row address RA that are held by respective latch units 90 to generate a decode signal Rd# corresponding to the reference cell row and a decode signal Rd corresponding to each memory cell row.”; that a latch can take the incoming signal for the wordline, that the incoming signal for the wordline can be used to drive the wordline to the specific decoded data level, that the latch stores this data for the word line, and that the second stage can drive the word line).
In view of the teachings of Ooishi it would have been obvious for a person of ordinary skill in the art to apply the teachings of Ooishi to YU before the effective filing date of the claimed invention in order to teach memory circuits. The teachings of Ooishi, in the same or in a similar field of endeavor with YU, can combine Ooishi’s explicit transistors in wordline drivers and YU implied transistors in a wordline driver. The two wordline drivers merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 5, YU, as modified by Ooishi, teaches the memory device of claim 2.
Ooishi further teaches wherein the second transistor comprises a PMOS transistor. (Ooishi, fig 2, 3, “[0088] Word line driver 82 includes a P channel MOS transistor 83 connected between a power supply voltage Vcc# and one end of a corresponding word line WL, and an N channel MOS transistor 84 connected between ground voltage GND and that one end of the corresponding word line WL.”; that wordline drivers in semiconductor devices routinely incorporate transistors; that Ooishi incorporates a PMOS and NMOS to drive the wordlines).
In view of the teachings of Ooishi it would have been obvious for a person of ordinary skill in the art to apply the teachings of Ooishi to YU before the effective filing date of the claimed invention in order to teach memory circuits. The teachings of Ooishi, in the same or in a similar field of endeavor with YU, can combine Ooishi’s explicit transistors in wordline drivers and YU implied transistors in a wordline driver. The two wordline drivers merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 7, YU teaches the memory device of claim 1.
YU teaches wherein the decoding circuitry further comprises: a plurality of first transistors, wherein the one or more first transistors are one of the plurality of first transistors, and (YU, fig 5, 6, “[0038] The operational amplifier 132 may receive the reference signal Vref and a feedback voltage V from an output of the transistor 134 through the voltage divider circuit 136. The operational amplifier 132 is configured to generate an error signal that represents a difference between the reference signal Vref and the feedback voltage V.”; a “first stage” comprising the transistor 134 and op amp 132; the op amp compares the incoming word line voltage to a reference voltage).
YU does not explicitly teach wherein the plurality of first transistors are associated with a row or column of the second stage of the decoding circuitry.
Ooishi teaches wherein the plurality of first transistors are associated with a row or column of the second stage of the decoding circuitry. (Ooishi, fig 2, 3, “0083 Row selection circuit 11a includes word line driver 82 for odd-numbered rows and a word line selection unit 80a, while row selection circuit 12a includes word line drivers 82 for even-numbered rows, a word line driver 82R related to reference word line RWL and a word line selection unit 81a. In this way, word line drivers 82 are arranged in each row Selection unit for every other rows and thus efficient arrangement of circuit components in each of row selection circuits 11a and 11b is possible.”; that at least two sets of drivers, each comprising a first and second stage can be present on a single array to drive both even and odd word lines of the array. Note: Applicant has not limited the “plurality of first transistors” to a single array, or a single block of a memory. Any art comprising multiple blocks, each with a single wordline driver could have been used as a basis for rejection).
In view of the teachings of Ooishi it would have been obvious for a person of ordinary skill in the art to apply the teachings of Ooishi to YU before the effective filing date of the claimed invention in order to teach memory circuits. The teachings of Ooishi, in the same or in a similar field of endeavor with YU, can combine Ooishi’s explicit dual sets of wordline drivers and YU implied transistors in a wordline driver. The two wordline drivers merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 13, YU teaches the method of claim 11.
YU teaches wherein outputting the second voltage to the second stage of the decoding circuitry (YU, fig 5, 6, “[0038] The operational amplifier 132 may receive the reference signal Vref and a feedback voltage V from an output of the transistor 134 through the voltage divider circuit 136. The operational amplifier 132 is configured to generate an error signal that represents a difference between the reference signal Vref and the feedback voltage V. [0041] A structure of the word line drive 138 is not limited in the disclosure. Any circuit structure that may drive the word lines of a memory device using the at least one of the word line voltage V RWL or the line voltage V RBL falls within the scope of the disclosure.”; a “first stage” comprising the transistor 134 and op amp 132; the op amp compares the incoming word line voltage to a reference voltage in the first stage, that the word line driver 138 can be “any circuit structure”).
YU does not explicitly teach is based at least in part on a supply voltage applied to a source of a second transistor and the second voltage applied to a gate of the second transistor.
Ooishi teaches is based at least in part on a supply voltage applied to a source of a second transistor and the second voltage applied to a gate of the second transistor. (Ooishi, fig 2, 3, “[0088] Word line driver 82 includes a P channel MOS transistor 83 connected between a power supply voltage Vcc# and one end of a corresponding word line WL, and an N channel MOS transistor 84 connected between ground voltage GND and that one end of the corresponding word line WL.”; that wordline drivers in semiconductor devices routinely incorporate transistors).
In view of the teachings of Ooishi it would have been obvious for a person of ordinary skill in the art to apply the teachings of Ooishi to YU before the effective filing date of the claimed invention in order to teach memory circuits. The teachings of Ooishi, in the same or in a similar field of endeavor with YU, can combine Ooishi’s explicit transistors in wordline drivers and YU implied transistors in a wordline driver. The two wordline drivers merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 15, YU teaches the method of claim 11.
YU does not explicitly teach further comprising: storing an indication of the second voltage based at least in part on comparing the first voltage with the target word line activation voltage.
Ooishi teaches further comprising: storing an indication of the second voltage based at least in part on comparing the first voltage with the target word line activation voltage. (Ooishi, fig 2, 3, “[0086] Referring to FIG. 3, address latch circuit 15a includes a plurality of latch units 90 respectively provided correspondingly to the bits of row address RA. Each latch unit 90 takes in a corresponding bit of row address RA in response to an activation edge of clock signal CLK to temporarily hold that bit. Word line selection unit 81a decodes the bits of row address RA that are held by respective latch units 90 to generate a decode signal Rd# corresponding to the reference cell row and a decode signal Rd corresponding to each memory cell row.”; that a latch can take the incoming signal for the wordline, that the incoming signal for the wordline can be used to drive the wordline to the specific decoded data level, that the latch stores this data for the word line, and that the second stage can drive the word line).
In view of the teachings of Ooishi it would have been obvious for a person of ordinary skill in the art to apply the teachings of Ooishi to YU before the effective filing date of the claimed invention in order to teach memory circuits. The teachings of Ooishi, in the same or in a similar field of endeavor with YU, can combine Ooishi’s explicit transistors in wordline drivers and YU implied transistors in a wordline driver. The two wordline drivers merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over YU in view of Lee, et al, U.S. Patent Application Publication 20220068381 (“Lee”).
YU teaches the memory device of claim 1.
YU does not explicitly teach wherein: the one or more first transistors each comprise a thin film transistor; and the second stage of the decoding circuitry comprises a plurality of thin film transistors.
Lee teaches wherein: the one or more first transistors each comprise a thin film transistor; and the second stage of the decoding circuitry comprises a plurality of thin film transistors. (Lee, fig 3, “[0027] Referring still to FIG. 3, and in greater detail, the WL driver 108 includes transistors MP0, MP1, MP2, MP3, MP4, MN1, MN2, MN3, MN4, MN5, and MN6, and an inverter 302. [0038] As mentioned above, each of the transistors of the WL driver 108 includes a thin-oxide transistor, which can provide better performance but may be subjected to oxide breakdown while a voltage across the respective oxide becomes substantially large. Using the configuration as shown in FIG. 3, although a relative large voltage (e.g., 2 volts of the WL signal 321) is provided through the transistors at the output stage of the WL driver 108 (e.g., transistors MP2 and MP4), such transistors may still be immune from the oxide breakdown.”; that TFTs can be configured from PMOS and NMOS transistors to create a wordline driver; that the wordline driver can solely comprise TFT transistors).
In view of the teachings of Lee it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lee to YU before the effective filing date of the claimed invention in order to teach memory circuits. The teachings of Lee, in the same or in a similar field of endeavor with YU, can combine Lee’s explicit transistors in multiple wordline drivers and YU’s implied transistors in a wordline driver. The two wordline drivers merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claims 17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over YU in view of Ooishi and Lee.
Regarding claim 17, YU teaches:
A memory device, comprising: a set of memory cells in a tier, each memory cell in the set of memory cells coupled with a common word line and a respective pillar of a set of pillars; decoding circuitry positioned below the set of memory cells and comprising a set of transistors; (YU, fig 5, 6, “[0013] FIG. 1 is a schematic diagram of a memory device 100 in accordance with some embodiments. The memory device 100 may include a memory array 110, a reference voltage generator 120, a driver circuit 130 and a memory controller 140. The memory array 110 includes a plurality of memory cells MC11 through MCnm that are coupled to a plurality of word lines WL1 through WLm, a plurality of bit lines BL1 through BLn and a plurality of source lines SL1 through SLn, where m and n are positive integers”; a memory device with a controller, voltage generator, drivers, plural wordlines, plural bitlines (pillars), and memory cells. Note: the “common word line” here is the source arriving from the voltage generator that is “coupled” to the word lines using the transistors 134 as shown below).
the first subset of transistors configured to activate the common word line based at least in part on a first voltage output from the second transistor; and (YU, fig 5, 6, “[0038] The operational amplifier 132 may receive the reference signal Vref and a feedback voltage V from an output of the transistor 134 through the voltage divider circuit 136. The operational amplifier 132 is configured to generate an error signal that represents a difference between the reference signal Vref and the feedback voltage V.”; a “first stage” comprising the transistor 134 and op amp 132; the op amp compares the incoming word line voltage to a reference voltage).
a second subset of transistors of the set of transistors, (YU, fig 5, 6, “[0041] The word line driver 138 is coupled to the output of the transistor 134 to receive the word line voltage V RWL or the bit line voltage V RBv and is configured to drive at least one memory cells of a memory array (e.g., memory array 110 in FIG. 1) using the word line voltage V RWL or the bit line voltage V RBL·”; the word line driver 138 (second stage) is controlled by the op amp 132 (first stage) to drive the word line voltages (activate a word line)).
YU does not explicitly teach:
a first subset of transistors of the set of transistors, each transistor of the first subset of transistors coupled with the common word line and a second transistor,
each transistor of the second subset of transistors coupled with the common word line and an amplifier, the second subset of transistors configured to provide a second voltage of the common word line to the amplifier.
Ooishi teaches each transistor of the second subset of transistors coupled with the common word line and an amplifier, the second subset of transistors configured to provide a second voltage of the common word line to the amplifier. (Ooishi, fig 2, 3, “[0088] Word line driver 82 includes a P channel MOS transistor 83 connected between a power supply voltage Vcc# and one end of a corresponding word line WL, and an N channel MOS transistor 84 connected between ground voltage GND and that one end of the corresponding word line WL.”; that wordline drivers in semiconductor devices routinely incorporate transistors; that Ooishi incorporates a PMOS and NMOS to drive the wordlines; that the driver takes the second voltage from YU’s comparator and use a second set of transistors to provide the word line voltage to the word lines).
In view of the teachings of Ooishi it would have been obvious for a person of ordinary skill in the art to apply the teachings of Ooishi to YU before the effective filing date of the claimed invention in order to teach memory circuits. The teachings of Ooishi, in the same or in a similar field of endeavor with YU, can combine Ooishi’s explicit transistors in wordline drivers and YU implied transistors in a wordline driver. The two wordline drivers merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Lee teaches a first subset of transistors of the set of transistors, each transistor of the first subset of transistors coupled with the common word line and a second transistor, (Lee, fig 3, “[0027] Referring still to FIG. 3, and in greater detail, the WL driver 108 includes transistors MP0, MP1, MP2, MP3, MP4, MN1, MN2, MN3, MN4, MN5, and MN6, and an inverter 302. [0038] As mentioned above, each of the transistors of the WL driver 108 includes a thin-oxide transistor, which can provide better performance but may be subjected to oxide breakdown while a voltage across the respective oxide becomes substantially large. Using the configuration as shown in FIG. 3, although a relative large voltage (e.g., 2 volts of the WL signal 321) is provided through the transistors at the output stage of the WL driver 108 (e.g., transistors MP2 and MP4), such transistors may still be immune from the oxide breakdown.”; that TFTs can be configured from PMOS and NMOS transistors to create a wordline driver; that the wordline driver can solely comprise TFT transistors).
In view of the teachings of Lee it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lee to YU before the effective filing date of the claimed invention in order to teach memory circuits. The teachings of Lee, in the same or in a similar field of endeavor with YU, can combine Lee’s explicit transistors in multiple wordline drivers and YU’s implied transistors in a wordline driver. The two wordline drivers merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 19, YU, as modified by Ooishi and Lee, teaches the memory device of claim 17.
Lee further teaches wherein: the second subset of transistors are associated with a row of the set of transistors, and the row of transistors extends along a direction parallel to a row of the set of memory cells. (Lee, fig 1, 3, “[0021] For example in FIG. 1, the memory cell 102-1 is coupled to the BL driver 106 through a pair of BL 116-1 and WL 118-1, which are one of a number of BLs (116-1, 116-2, 116-3 … 116-N) and one of a number of WLs (118-1, 118-2, 118-3 … 118-M), respectively, wherein N may correspond to a number of the columns of the memory array 102 and M may correspond to a number of the rows of the memory array 102.”; that a memory array can comprise multiple transistors associated with the wordline drivers in a memory array; that transistors can be used to construct a BL and WL driver respectively).
In view of the teachings of Lee it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lee to YU before the effective filing date of the claimed invention in order to teach memory circuits. The teachings of Lee, in the same or in a similar field of endeavor with YU, can combine Lee’s explicit transistors in multiple wordline drivers and YU’s implied transistors in a wordline driver. The two wordline drivers merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 20, YU, as modified by Ooishi and Lee, teaches the memory device of claim 17.
Lee further teaches wherein: the second subset of transistors are associated with a column of the set of transistors, and the column of transistors extends along a direction parallel to a column of the set of memory cells. (Lee, fig 1, 3, “[0021] For example in FIG. 1, the memory cell 102-1 is coupled to the BL driver 106 through a pair of BL 116-1 and WL 118-1, which are one of a number (116-1, 116-2, 116-3 … 116-N) and one of a number of WLs (118-1, 118-2, 118-3 … 118-M), respectively, wherein N may correspond to a number of the columns of the memory array 102 and M may correspond to a number of the rows of the memory array 102.”; that a memory array can comprise multiple transistors associated with the wordline drivers in a memory array; that transistors can be used to construct a BL and WL driver respectively).
In view of the teachings of Lee it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lee to YU before the effective filing date of the claimed invention in order to teach memory circuits. The teachings of Lee, in the same or in a similar field of endeavor with YU, can combine Lee’s explicit transistors in multiple wordline drivers and YU’s implied transistors in a wordline driver. The two wordline drivers merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over YU, as modified by Ooishi and Lee, in view of Samachisa, et al, U.S. Patent Application Publication 20120147650 (“Samachisa”).
YU, as modified by Ooishi and Lee, teaches the memory device of claim 17.
YU, as modified by Ooishi and Lee, does not explicitly teach wherein the first subset of transistors are coupled with the set of memory cells based at least in part on one or more through silicon vias extending between the decoding circuitry and the set of memory cells.
Samachisa teaches wherein the first subset of transistors are coupled with the set of memory cells based at least in part on one or more through silicon vias extending between the decoding circuitry and the set of memory cells. (Samachisa, fig 26B, 27, “[0358] Each word line comb is switchably connected to a corresponding metal global word line via a via configuration similar to that shown in FIG. 26B and FIG. 27. Typically, access by the via to the different layers of word line comb is by terracing the different layers as shown in FIG. 26B. Then each word line comb is connected via a via configuration to a metal pad on the substrate of the CMOS.”; that word line layers are typically stacked on a substrate; that the access to the wordlines can be through a via to the substrate; that the wordlines can be connected vertically as shown in fig 7 to a string of memory cells, addressable by wordlines and bitlines).
In view of the teachings of Samachisa it would have been obvious for a person of ordinary skill in the art to apply the teachings of Samachisa to YU before the effective filing date of the claimed invention in order to teach memory circuits. The teachings of Samachisa, in the same or in a similar field of endeavor with YU, can combine Samachisa’s explicit memory cell construction with substrates, via, transistors, and memory cells with YU’s implied memory array construction. The two memory arrays merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Conclusion
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825