DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of a claim for foreign priority to application CN202311091273.7 under 35 U.S.C. § 119(a)-(d) or (f).
Claim Objections
Claim 18 objected to because of the following informality: claim 18 recites "the second edge of the edge" but earlier refers to "a first edge" and "a second edge
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-8, 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over Yan et al. US 2021/0020755 A1 (hereinafter Yan) in view of Park et al. KR 2014/0170588 A (hereinafter Park).
Regarding claim 1, Yan discloses: An electronic device (Yan, array substrate 600, "the array substrate 600 comprises a thin film transistor (for example, a thin film transistor 100/200/300/400/500) provided according to any one of the above embodiments" [Para. 0066, Fig. 6]), comprising:
a substrate (Yan, substrate 101 [Fig. 6]);
a light-shielding layer disposed on the substrate (Yan, "light shielding layer 110 on one side of the substrate 101" [Para. 0078]);
a first insulating layer disposed on the light-shielding layer (Yan, "buffer layer 109 located on one side of the substrate 101 and covering the light shielding layer 110" [Para. 0078]);
a semiconductor layer disposed on the first insulating layer (Yan, "active layer 102 is formed on one side of the buffer layer 109 away from the substrate 101" [Para. 0078]);
a second insulating layer disposed on the semiconductor layer and having a hole (Yan, "gate dielectric layer 107 is formed on one side of the active layer 102 away from the substrate 101" {Para. 0079]…"second opening 20 exposes a part of the active layer 102" [Para. 0087, Fig. 9F]),
wherein the hole exposes a portion of the first insulating layer (Yan, "second opening 20 may extend into the buffer layer 109" [Para. 0088]);
and a drain connected to the semiconductor layer through the hole (Yan, "drain 106 is located in the second opening 20, and in contact with the active layer 102" [Para. 0087]).
Yan does not disclose that the first minimum distance exists between the portion of the first insulating layer and the light-shielding layer, the second minimum distance exists between the semiconductor layer and the light-shielding layer, and the ratio of the first minimum distance to the second minimum distance is greater than or equal to 0.1 and less than or equal to 1.0.
However, Park, in the same field of endeavor, teaches an electronic device wherein
a first minimum distance exists between the portion of the first insulating layer and the light-shielding layer (Park, "the lower ends of the source sink hole ssh and the drain sink hole dsh are formed to be spaced apart from the light blocking layer ls by a predetermined distance t3" [Para. 0064]),
a second minimum distance exists between the semiconductor layer and the light-shielding layer (Park, t2 [Fig. 11]),
and a ratio of the first minimum distance to the second minimum distance is greater than or equal to 0.1 and less than or equal to 1.0 (Park, "the separation distance t3 is preferably 1000 å to 2000 å" [Para. 0064] and "the buffer layer bf may be formed to have a thickness t2 of 3000 å to 6000 å" [Para. 0063]. As such, a range of 0.167 to 0.667 is taught by Park.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Yan with the teachings of Park, arriving at the Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so is expressly recognized by Park: “the distance t3 between the lower ends of the source sink hole ssh and the drain sink hole dsh and the light blocking layer ls may be a minimum distance between the source/drain electrodes s and d and the light blocking layer ls that is not short-circuited” [Para. 0064]. The obvious combination is hereinafter referred to as modified Yan.
Regarding claim 2, Park further discloses an electronic device: wherein a thickness of the first insulating layer is greater than or equal to 500 angstroms and less than or equal to 3000 angstroms (Park, "[t]he thickness of the buffer layer 3000~6000å" [Para. 0041]).
Therefore, the claimed range for the thickness of the first insulating layer would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention over the range disclosed in Park because where “the claimed range overlaps the range disclosed by the prior art,” a prima facie case of obviousness exists. See MPEP 2144.05 and In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976).
Regarding claim 3, Yan further discloses an electronic device: wherein in a direction, an edge of the drain protrudes from the light-shielding layer by a first distance (Yan, first portion 116 of drain 106 protrudes from the light shielding layer 110 in Fig. 6 by a first distance. Please refer to the figure below annotated with the corresponding distance element D1 from Applicant.).
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Regarding claim 4, Yan discloses the lateral protrusion of first portion 116 from the light shielding layer 110 but does not expressly disclose that the first distance is greater than or equal to 0.2 micrometers. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to select a protrusion distance of at least 0.2 micrometers as a suitable layout margin based on the alignment and photolithographic tolerances of the fabrication process. The amount by which the drain extends beyond the light-shielding layer is a result-effective layout variable because adjusting that distance predictably affects the available alignment margin and the likelihood that process deviations will produce undesired exposure or electrical contact between conductive features. Selection of a workable value, including at least 0.2 micrometers, would therefore have involved no more than routine optimization of Yan’s disclosed geometry, with a reasonable expectation of obtaining a reliable transistor structure.
Regarding claim 5, Yan further discloses an electronic device: wherein in a direction, an edge of the drain protrudes from an edge of the hole by a second distance (Yan, first portion 116 of drain 106 protrudes from the edge of opening 20 in Fig. 6 by a second distance. Please refer to the figure below annotated with the corresponding distance elements D2 and W from Applicant.).
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Regarding claim 6, Yan discloses the lateral protrusion of first portion 116 from edge of opening 20 but does not expressly disclose that the second distance is greater than or equal to 0.3 micrometers. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to select a second distance of at least 0.3 micrometers based on the desired contact area and the photolithographic tolerances of the fabrication process. The amount by which the drain extends across the opening is a result-effective variable because increasing the extension predictably increases contact coverage and tolerance for mask misalignment, thereby reducing the likelihood of a disconnected contact. As such, selecting a suitable extension, including at least 0.3 micrometers, would therefore have involved no more than routine optimization of Yan’s disclosed geometry, with a reasonable expectation of obtaining a reliable transistor structure.
Regarding claim 7, Yan further discloses an electronic device: wherein the hole has a width in the direction (Yan, Fig. 6 illustrates opening 20 having a width in the direction. Please refer to the figure above annotated with the corresponding distance elements from Applicant.),
and a difference between the width and the second distance is greater than or equal to 0 and less than or equal to half of the width (Yan, “the first portion 116 of the drain 106 is in contact with the bottom surface and the side surface(s) of the second recess” [Para. 0057]. As such, Yan teaches the distance between the width and the second distance to be equal to 0.).
Regarding claim 8, Yan further discloses an electronic device: wherein the light-shielding layer is partially overlapped with the hole (Yan, light shielding layer 110 partially overlaps second opening 20 [Figs. 6, 9F]).
Regarding claim 10, Yan further discloses an electronic device: wherein in a direction, an edge of the semiconductor layer protrudes from an edge of the drain by a third distance (Yan, active layer 102 protrudes from the right edge of first portion 116 in a direction [Fig. 6]).
Regarding claim 11, Yan further discloses an electronic device: further comprising a scan line disposed on the substrate, wherein a portion of the scan line forms a gate (Yan, gate 108 [Fig. 6]),
and the second insulating layer is disposed between the gate and the semiconductor layer (Yan, "gate 108 is formed on one side of the gate dielectric layer 107 away from the active layer 102" [Para. 0079]).
Regarding claim 12, Yan further discloses an electronic device: wherein the light-shielding layer is at least partially overlapped with the scan line (Yan, Fig. 6 illustrates gate 108 overlapped with light shielding layer 110.).
Regarding claim 13, Yan further discloses an electronic device: wherein in a direction, a width of the light-shielding layer is greater than a width of the scan line (Yan, Fig. 6 illustrates the width of light shielding layer 110 being greater than gate 108 in a direction.).
Regarding claim 14, Yan further discloses an electronic device: further comprising a third insulating layer disposed on the second insulating layer (Yan, interlayer dielectric layer 103 and interlayer dielectric layer 105 [Fig. 6])
and disposed between the gate and the drain (Yan, "interlayer dielectric layer 103 may be located on one side of the gate dielectric layer 107 away from the substrate 101" [Para. 0081]. Fig. 6 illustrates interlayer dielectric layer 103 separating gate 108 and first portion 116 of drain 106.).
Regarding claim 15, Yan further discloses an electronic device: further comprising: a fourth insulating layer disposed on the drain and the third insulating layer (Yan, "planarization layer 201 is located on one side of the second interlayer dielectric layer 105" [Para. 0068]. Fig. 6 illustrates planarization layer 201 being disposed on second portion 126 of drain 106 as well.),
wherein the fourth insulating layer has another hole (Yan, opening 211 [Fig. 6]),
and the another hole exposes a portion of the drain (Yan, "planarization layer 201 defines an opening 211 that exposes a part of the second portion 126 of the drain 106" [Para. 0068]);
and a conductive layer disposed on the fourth insulating layer (Yan, "first electrode 202 is located on the bottom and the sidewall of the opening 211, and the other part of the first electrode 202 is located on the planarization layer 201" [Para. 0069])
and electrically connected to the drain through the another hole (Yan, "first electrode 202 is at least partially located in the opening 211, and in contact with the second portion 126" [Para. 0069]).
Claims 9 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over modified Yan as applied to claim 1 above, and further in view of Xu et al. US 2023/0108752 A1 (hereinafter Xu).
Regarding claim 9, Xu discloses an electronic device: wherein a projection of the hole on the substrate is located within a projection of the light-shielding layer on the substrate (Xu, Fig. 5A illustrates first contact hole 251's projection on the substrate being encompassed by light-shielding structure 122's projection on the base substrate.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of modified Yan with the teachings of Xu, arriving at the Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so is expressly recognized by Xu because "[i]n this way, the first drain electrode in the conductive layer can be connected with the first recessed portion through the first contact hole" [Para. 0349] wherein “[t]he conductive light-shielding structure includes a first main body portion and a first recessed portion” [Abs.].
Regarding claim 17, Xu further discloses an electronic device: wherein the portion of the first insulating layer exposed by the hole has a concave surface (Xu, third sub side wall 2516 of first contact hole 251 has a concave surface in buffer layer 130 [Fig. 6B]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of modified Yan with the teachings of Xu, arriving at the Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so is expressly recognized by Xu:
"In this way, in a case that the light shielding performance of the first recessed portion is reduced due to its thinning, since the concave structure has at least two inclined surfaces, the concave structure can reflect light passing through the first recessed portion. In addition, since the concave structure itself is a microstructure, the concave structure can also scatter light passing through the first recessed portion, so that the light passing through the first recessed portion is further prevented from affecting the normal display of the display substrate" [Para. 0333].
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over modified Yan as applied to claim 15 above, and further in view of Gui et al. US 2022/0320212 A1 (hereinafter Gui).
Regarding claim 16, Gui discloses an electronic device: further comprising a light-shielding element disposed on the conductive layer (Gui, "the fifth conductive layer 90 includes a data line 64 and a light-shielding layer 902" [Para. 0134, Figs. 12-13]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of modified Yan with the teachings of Gui, arriving at the Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so is expressly recognized by Gui because “[w]ith a design of the light-shielding layer 902, the active layer 20a of the first transistor T1 and the active layer 20b of the second transistor T2 may be protected from external light, which is beneficial to maintaining a stable performance of the first transistor and the second transistor" [Para. 0136].
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over modified Yan as applied to claim 1 above, and further in view of Long et al. US 2025/0124868 A1 (hereinafter Long).
Regarding claim 18, Long discloses an electronic device: wherein the hole has a first edge and a second edge that are located at opposite ends in a direction (Long, second via hole H2 [Fig. 12A]),
the first edge is located at a boundary between the second insulating layer and the semiconductor layer (Long, bottom-left corner of H2 is located at the boundary of active layer 1141 and gate insulation layer 113 [Fig. 12A]),
and the second edge of the edge is located at a boundary between the second insulating layer and the first insulating layer (Long, bottom-right corner of H2 is located at the boundary of buffer layer 112 and gate insulation layer 113 through grooved region 1172 [Figs. 11, 12A]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of modified Yan with the teachings of Long, arriving at the Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for the disclosed geometry is expressly stated by Long because “a channel current of the first transistor T1 is reduced while keeping the channel shape/width-to-length ratio of the first transistor T1 unchanged” [Para. 0150].
Regarding claim 19, Long further discloses an electronic device: wherein a distance exists between an edge of the drain and the second edge of the hole in the direction (Long, second electrode 1144 is electrically connected to second via hole H2 where “the second electrode may be a drain electrode” [Para. 0128]).
Regarding claim 20, Long further discloses an electronic device: wherein the hole has a width in the direction (Long, second via hole H2 has a width in the direction of opposing edges [Fig. 12A]),
and the distance is less than or equal to half of the width (Long, second via hole H2 is filled with conductive material. As such, the distance is equal to zero.).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GERALD H BISSELL whose telephone number is (571) 272-0834. The examiner can normally be reached Mon - Fri 0800 - 1600.
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/GERALD H. BISSELL/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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