Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This is in response to the amendments filed on 09/30/2025. Claims 1-3 and 5-7. Claims 1-3 and 5-7 are currently pending and have been considered below.
Response to Arguments
Claims 1 and 6 have been amended and therefore the rejections under U.S.C 112 are withdrawn.
Applicant’s arguments with respect to claims 1-3 and 5-6 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Opferman(US Publication No. 2019/0042258 A1) in view of Gunti(US Publication No. 2017/0372074 A1) in further view of Gu (US Publication No. 20060174300 A1) and in further view of Strong(US Publication No. 20200082089 A1).
Regarding Claim 1:
Opferman discloses:
An information processing device comprising: a first CPU core of the first processor; and(Opferman, FIG. 1, Abstract, a processor core supporting a heterogenous system, [0023], a computer or other information processing system. For example, core 100 in FIG. 1 may correspond to or be included in any of core 49 );
a second CPU core of the first processor having an operating frequency higher than that of the first CPU core((Opferman, [0048], Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: 1) a general purpose in-order core intended for general-purpose computing; 2) a high-performance general purpose out-of-order core intended for general-purpose computing; 3);
Opferman does not disclose:
the first CPU core is configured to, by executing the, initial program loader program, perform a a first verification process of verifying the deployment program based on the first electronic signature
the second CPU core is configured to, by executing the deployment program, perform a second verification process of verifying the compressed file based on the second electronic signature
Gunti discloses:
the first CPU core is configured to, by executing the, initial program loader program, perform a a first verification process of verifying the deployment program based on the first electronic signature(Gunti, [0012], The process of securely booting computer system 100 is illustrated in a flow diagram shown in FIG. 3. Portions of FIG. 1, in particular contents of system memory 122, schematically depict the process of booting computer system 100… the public key of a trusted entity will be used in verifying a boot loader, in particular a digital signature (shown as ‘sig’ in FIG. 1) that is appended to the boot loader (or otherwise made available to the boot firmware for retrieval and verification))
the second CPU core is configured to, by executing the deployment program, perform a second verification process of verifying the compressed file based on the second electronic signature (Gunti, [0016], Boot loader 149 upon being launched performs digital signature verification on the kernel which is encapsulated in Package 1 of boot image 150 (step 314) and on the verifier which is also encapsulated in Package 1 of boot image 150 (step 316). The digital signature verification on the kernel and the verifier is carried out in the same manner as described above at step 308 for boot loader 149,).
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Opferman’s Processor core supporting a heterogeneous system instruction set architecture by enhancing Opferman’s systems for a processor core supporting a heterogenous system to ensure that a computer system is securely booted by executing a boot firmware as taught by Gunti in order to ensure that each subsequent, larger module is only executed if the preceding, smaller module has successfully validated it.
The motivation is to establish a robust, hierarchical chain of trust to prevent unauthorized or malicious code from being executed on a device by significantly improving system security within the boot process.
Opferman in view of Gunti does not disclose:
a compressed file having a second capacity size larger than the first capacity size
Gu discloses:
a compressed file having a second capacity size larger than the first capacity size(Gu, [0028], The CRAMFS image 114C can include compressed and uncompressed files. [0031], The SFS differencing 200 determines 206 differences between content of the images by determining differences between the portions of each of the original image and the new image.);
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Opferman in view of Gunti’s Processor core supporting a heterogeneous system instruction set architecture by enhancing Opferman in view of Gunti’s systems for a processor core supporting a heterogenous system to ensure that a computer system is securely booted by executing a boot firmware as taught by Gu in order to enhance memory utilization and reduce storage and bandwidth requirements during boot
The motivation is to ensure that larger executable system images are stored and transferred in compressed form, thereby reducing memory footprint and improving system efficiency while maintain the ability to deploy such images through a smaller loader program.
Opferman in view of Gunti in further view of Strong disclose:
a main board having a first processor and a first memory, the main board being configured to communicate with a sub board having a second processor and a second memory, the main board including
the first memory storing: an initial program loader program
a deployment program having a first capacity size
a first electronic signature
and a second electronic signature
a booting process of the main board is completed after the first and second verification processes are successful
Strong discloses:
a main board having a first processor and a first memory, the main board being configured to communicate with a sub board having a second processor and a second memory, the main board including(Strong, [0030], The memory controller 215 can include a processor configured to execute instructions stored in a local memory similar to the memory controller 115 of FIG. 1. The memory controller 215 can be coupled to other memory components such DRAM 242. [0028], The memory controller 215 may correspond to the controller 115 in FIG. 1, and the microcontroller 216 may correspond to the microcontroller 116. [0032], In a boot process for the memory sub-system 210, the memory controller 215 can read a PBL in a read-only memory (ROM) 223. Alternatively, the PBL may optionally reside in EEPROM 226 coupled to the 12C bus)
the first memory storing: an initial program loader program (Strong, [0012], When a memory sub-system, such as a SSD, is powered, a boot process is initiated in the SSD to enable loading of an operating system within the memory sub-system. In a boot process for a memory sub-system, a memory controller can read a set of instructions, which are typically code resident in a read-only memory (ROM). The resident code is small firmware (FW) program referred to as a primary boot loader (PBL));
a deployment program having a first capacity size (Strong, [0031], the memory controller 215, a serial peripheral interface (SPI) NOR boot device 222 having a SPI connection 242 to the memory controller 215, and light emitting diodes (LEDs) 233 having a general purpose input/output (GPIO) connection 243 to the memory controller 215. The SPI NOR Boot Device 222 is a nonvolatile memory that can stores a SBL for memory sub-system 210.);
a first electronic signature(Strong,[0040], The cryptographic verification can include a RSA signature verification. RSA is a cryptosystem in which an encryption key public and is different from the decryption key, which is kept private. A public key is created and published based on two large prime numbers along with an auxiliary value, where the prime numbers are kept secret. Other cryptographic techniques can be used to implement a secure mechanism for a secure boot process.);
and a second electronic signature(Strong, [0033], cryptographic verification of FW during device boot, a secure boot prevents the host 220 from downloading FW using the PBL, because the FW may not be digitally signed and would be untrusted, and disables debug interfaces that could be used to download untrusted FW onto the device. In addition, an embodiment of a secure boot could also support digital signature verification when the host 220)
a booting process of the main board is completed after the first and second verification processes are successful (Strong, [0029], The memory sub-system 210 can be configured as a memory sub-system. The host 220 can communicate with the memory sub-system 210 through an interface 221, such as but not limited to a PCIe host interface, [0033], The boot process for the memory sub-system 210, the memory controller 215 and the microcontroller 216 can operate together to provide a secure boot mode. In some embodiments, a secure boot includes a process where FW is cryptographically verified from memory sub-system 210 power on until the main FW is executing. Supporting secure boot assumes that the boot process starts with a root of trust.).
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Opferman in view of Gunti in further view of Gu’s Processor core supporting a heterogeneous system instruction set architecture by enhancing Opferman in view of Gunti in further view of Gu’s systems for a processor core supporting a heterogenous system to ensure that a computer system is securely booted by executing a boot firmware as taught by Strong to ensure secure and efficient booting of a multi-processor system
The motivation is to ensure secure boot operation in a multi-processor system while optimizing memory usage and performance through the use of compressed executable images and staged signature verification.
Regarding Claim 2:
The information processing device according to claim 1, Opferman in view of Gunti in view of Gunti in further view of Gu and in further view of Strong disclose wherein the first memory is a RAM, and the second CPU core is configured to perform a process of deploying the compressed file into the RAM.
Gu discloses:
wherein the first memory is a RAM, and the second CPU core is configured to perform a process of deploying the compressed file into the RAM (Gu, Abstract, the new CRAMFS image in a block in host device RAM [0077], The method of an embodiment comprises updating a target SFS image of the client device using information of the delta file by reconstructing all portions of the new image in a device block in random access memory of the host device and writing the device block into read-only memory of the host device.).
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Opferman in view of Gunti’s Processor core supporting a heterogeneous system instruction set architecture by enhancing Opferman in view of Gunti’s systems for a processor core supporting a heterogenous system to ensure CRAMFS images into portions using CRAMFS file system structure information as taught by Gu in order to ensure that only authenticated, trusted code is loaded into executable memory, preventing unauthorized or malicious code execution.
The motivation is to ensure that the compressed file has not been tampered with and comes from a legitimate source, protecting against supply chain attacks where a malicious file is inserted into a trusted update.
Regarding Claim 5:
The information processing device according to claim 1, Opferman in view of Gunti in further view of Gu and in further view of Strong disclose wherein the first CPU core and the second CPU core are mixedly mounted on an SoC element(Opferman, [0063], The cores 502A-N may be homogenous or heterogeneous in terms of architecture instruction set; that is, two or more of the cores 502A-N may be capable of execution the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set).
Regarding Claim 6:
Opferman discloses:
A robot controller comprising: a first CPU core of the first processor(Opferman, FIG. 1, Abstract, a processor core supporting a heterogenous system, [0021], In some such systems, different cores may have different ISAs. Therefore, a system may include a first core with hardware, hardwiring, microcode, control logic, and/or other micro-architecture designed to execute particular instructions according to a particular ISA (or extensions to or other subset of an ISA), and the system may also include a second core without such micro-architecture. [0023], a computer or other information processing system. For example, core 100 in FIG. 1 may correspond to or be included in any of core 49 );
a second CPU core of the first processor having an operating frequency higher than that of the first CPU core(Opferman, [0048], Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: 1) a general purpose in-order core intended for general-purpose computing; 2) a high-performance general purpose out-of-order core intended for general-purpose computing; 3);
Opferman does not disclose:
the first CPU core is configured to, by executing the, initial program loader program, perform a first verification process of verifying the deployment program based on the first electronic signature
the second CPU core is configured to, by executing the deployment program, perform a a second verification process of verifying the compressed file based on the second electronic signature
Gunti discloses:
the first CPU core is configured to, by executing the, initial program loader program, perform a first verification process of verifying the deployment program based on the first electronic signature (Gunti, [0012], The process of securely booting computer system 100 is illustrated in a flow diagram shown in FIG. 3. Portions of FIG. 1, in particular contents of system memory 122, schematically depict the process of booting computer system 100… the public key of a trusted entity will be used in verifying a boot loader, in particular a digital signature (shown as ‘sig’ in FIG. 1) that is appended to the boot loader (or otherwise made available to the boot firmware for retrieval and verification))
the second CPU core is configured to, by executing the deployment program, perform a a second verification process of verifying the compressed file based on the second electronic signature(Gunti, [0016], Boot loader 149 upon being launched performs digital signature verification on the kernel which is encapsulated in Package 1 of boot image 150 (step 314) and on the verifier which is also encapsulated in Package 1 of boot image 150 (step 316). The digital signature verification on the kernel and the verifier is carried out in the same manner as described above at step 308 for boot loader 149,).
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Opferman’s Processor core supporting a heterogeneous system instruction set architecture by enhancing Opferman’s systems for a processor core supporting a heterogenous system to ensure that a computer system is securely booted by executing a boot firmware as taught by Gunti in order to ensure that each subsequent, larger module is only executed if the preceding, smaller module has successfully validated it.
The motivation is to establish a robust, hierarchical chain of trust to prevent unauthorized or malicious code from being executed on a device by significantly improving system security within the boot process.
Opferman in view of Gunti does not disclose:
a compressed file having a second capacity size larger than the first capacity size
Gu discloses:
a compressed file having a second capacity size larger than the first capacity size(Gu, [0028], The CRAMFS image 114C can include compressed and uncompressed files. [0031], The SFS differencing 200 determines 206 differences between content of the images by determining differences between the portions of each of the original image and the new image.).
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Opferman in view of Gunti’s Processor core supporting a heterogeneous system instruction set architecture by enhancing Opferman in view of Gunti’s systems for a processor core supporting a heterogenous system to ensure that a computer system is securely booted by executing a boot firmware as taught by Gu in order to enhance memory utilization and reduce storage and bandwidth requirements during boot
The motivation is to ensure that larger executable system images are stored and transferred in compressed form, thereby reducing memory footprint and improving system efficiency while maintain the ability to deploy such images through a smaller loader program.
Opferman in view of Gunti in further view of Gu in further view of Strong disclose:
a main board having a first processor and a first memory, the main board being configured to communicate with a sub board having a second processor and a second memory, the first and second processors being configured to control motion of a robot, the main board including
the first memory storing: an initial program loader program
the first memory storing: an initial program loader program
a deployment program having a first capacity size
a first electronic signature
electronic signature
a booting process of the main board is completed after the first and second verification processes are successful
Strong discloses:
a main board having a first processor and a first memory, the main board being configured to communicate with a sub board having a second processor and a second memory, the first and second processors being configured to control motion of a robot, the main board including(Strong, [0030], The memory controller 215 can include a processor configured to execute instructions stored in a local memory similar to the memory controller 115 of FIG. 1. The memory controller 215 can be coupled to other memory components such DRAM 242. [0028], The memory controller 215 may correspond to the controller 115 in FIG. 1, and the microcontroller 216 may correspond to the microcontroller 116. [0032], In a boot process for the memory sub-system 210, the memory controller 215 can read a PBL in a read-only memory (ROM) 223. Alternatively, the PBL may optionally reside in EEPROM 226 coupled to the 12C bus):
the first memory storing: an initial program loader program (Strong, [0012], When a memory sub-system, such as a SSD, is powered, a boot process is initiated in the SSD to enable loading of an operating system within the memory sub-system. In a boot process for a memory sub-system, a memory controller can read a set of instructions, which are typically code resident in a read-only memory (ROM). The resident code is small firmware (FW) program referred to as a primary boot loader (PBL));
a deployment program having a first capacity size (Strong, [0031], the memory controller 215, a serial peripheral interface (SPI) NOR boot device 222 having a SPI connection 242 to the memory controller 215, and light emitting diodes (LEDs) 233 having a general purpose input/output (GPIO) connection 243 to the memory controller 215. The SPI NOR Boot Device 222 is a nonvolatile memory that can stores a SBL for memory sub-system 210.);
a first electronic signature(Strong,[0040], The cryptographic verification can include a RSA signature verification. RSA is a cryptosystem in which an encryption key public and is different from the decryption key, which is kept private. A public key is created and published based on two large prime numbers along with an auxiliary value, where the prime numbers are kept secret. Other cryptographic techniques can be used to implement a secure mechanism for a secure boot process.);
and a second electronic signature(Strong, [0033], cryptographic verification of FW during device boot, a secure boot prevents the host 220 from downloading FW using the PBL, because the FW may not be digitally signed and would be untrusted, and disables debug interfaces that could be used to download untrusted FW onto the device. In addition, an embodiment of a secure boot could also support digital signature verification when the host 220),
a booting process of the main board is completed after the first and second verification processes are successful(Strong, [0029], The memory sub-system 210 can be configured as a memory sub-system. The host 220 can communicate with the memory sub-system 210 through an interface 221, such as but not limited to a PCIe host interface, [0033], The boot process for the memory sub-system 210, the memory controller 215 and the microcontroller 216 can operate together to provide a secure boot mode. In some embodiments, a secure boot includes a process where FW is cryptographically verified from memory sub-system 210 power on until the main FW is executing. Supporting secure boot assumes that the boot process starts with a root of trust.).
Regarding Claim 7:
Opferman discloses:
A method for performing information processing by using a processor having a first CPU core (Opferman, FIG. 1, Abstract, a processor core supporting a heterogenous system, [0023], a computer or other information processing system. For example, core 100 in FIG. 1 may correspond to or be included in any of core 49 ),
and a second CPU core(Opferman, [0048], Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: 1) a general purpose in-order core intended for general-purpose computing; 2) a high-performance general purpose out-of-order core intended for general-purpose computing);
the second CPU core having an operating frequency higher than that of the first CPU core(Opferman, [0021], In some such systems, different cores may have different ISAs. Therefore, a system may include a first core with hardware, hardwiring, microcode, control logic, and/or other micro-architecture designed to execute particular instructions according to a particular ISA (or extensions to or other subset of an ISA), and the system may also include a second core without such micro-architecture);
Opferman does not disclose:
a second verification process of verifying the compressed file
Gunti discloses:
a second verification process of verifying the compressed file (Gunti, [0021], digitally signing the state data files after initial installation for subsequent secure reboots, embodiments employ a sandbox maintained by the kernel (“kernel sandbox”) in which state data files are mounted at step 330. For verification during subsequent reboots, these state data files are collected into an archive file for state data and, upon rebooting,)
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Opferman’s Processor core supporting a heterogeneous system instruction set architecture by enhancing Opferman’s systems for a processor core supporting a heterogenous system to ensure that a computer system is securely booted by executing a boot firmware as taught by Gunti in order to enhance system security and prevent execution of tampered or unauthorized code.
The motivation is to ensure that integrity verification is extended beyond initial boot components to all subsequently loaded program elements, thereby maintaining a continuous chain of trust during the boot process.
Opferman in view of Gunti does not disclose:
a compressed file having a second capacity size larger than the first capacity size
Gu discloses:
a compressed file having a second capacity size larger than the first capacity size(Gu, [0028], The CRAMFS image 114C can include compressed and uncompressed files. [0031], The SFS differencing 200 determines 206 differences between content of the images by determining differences between the portions of each of the original image and the new image.);
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Opferman in view of Gunti’s Processor core supporting a heterogeneous system instruction set architecture by enhancing Opferman in view of Gunti’s systems for a processor core supporting a heterogenous system to ensure that a computer system is securely booted by executing a boot firmware as taught by Gu in order to enhance memory utilization and reduce storage and bandwidth requirements during boot
The motivation is to ensure that larger executable system images are stored and transferred in compressed form, thereby reducing memory footprint and improving system efficiency while maintain the ability to deploy such images through a smaller loader program.
Opferman in view of Gunti in further view of Strong disclose:
a memory, the processor and the memory being provided on a main board that is configured to communicate with a sub board on which another processor and another memory are provided
the memory storing an initial program loader program
deployment program having a first capacity size
a first electronic signature
and a second electronic signature
the method comprising: performing, by executing the initial program loader program
a first verification process of verifying the deployment program based on the first electronic signature
performing, by executing the deployment program
based on the second electronic signature
and completing a booting process of the main board after the first and second verification processes are successful
Strong discloses:
a memory, the processor and the memory being provided on a main board that is configured to communicate with a sub board on which another processor and another memory are provided(Strong, [0030], The memory controller 215 can include a processor configured to execute instructions stored in a local memory similar to the memory controller 115 of FIG. 1. The memory controller 215 can be coupled to other memory components such DRAM 242. [0028], The memory controller 215 may correspond to the controller 115 in FIG. 1, and the microcontroller 216 may correspond to the microcontroller 116. [0032], In a boot process for the memory sub-system 210, the memory controller 215 can read a PBL in a read-only memory (ROM) 223. Alternatively, the PBL may optionally reside in EEPROM 226 coupled to the 12C bus)
the memory storing an initial program loader program(Strong, [0012], When a memory sub-system, such as a SSD, is powered, a boot process is initiated in the SSD to enable loading of an operating system within the memory sub-system. In a boot process for a memory sub-system, a memory controller can read a set of instructions, which are typically code resident in a read-only memory (ROM). The resident code is small firmware (FW) program referred to as a primary boot loader (PBL));
deployment program having a first capacity size(Strong, [0031], the memory controller 215, a serial peripheral interface (SPI) NOR boot device 222 having a SPI connection 242 to the memory controller 215, and light emitting diodes (LEDs) 233 having a general purpose input/output (GPIO) connection 243 to the memory controller 215. The SPI NOR Boot Device 222 is a nonvolatile memory that can stores a SBL for memory sub-system 210.);
a first electronic signature(Strong,[0040], The cryptographic verification can include a RSA signature verification. RSA is a cryptosystem in which an encryption key public and is different from the decryption key, which is kept private. A public key is created and published based on two large prime numbers along with an auxiliary value, where the prime numbers are kept secret. Other cryptographic techniques can be used to implement a secure mechanism for a secure boot process.),
and a second electronic signature(Strong, [0033], cryptographic verification of FW during device boot, a secure boot prevents the host 220 from downloading FW using the PBL, because the FW may not be digitally signed and would be untrusted, and disables debug interfaces that could be used to download untrusted FW onto the device. In addition, an embodiment of a secure boot could also support digital signature verification when the host 220),
the method comprising: performing, by executing the initial program loader program(Strong, [0012], When a memory sub-system, such as a SSD, is powered, a boot process is initiated in the SSD to enable loading of an operating system within the memory sub-system. In a boot process for a memory sub-system, a memory controller can read a set of instructions, which are typically code resident in a read-only memory (ROM). The resident code is small firmware (FW) program referred to as a primary boot loader (PBL));
a first verification process of verifying the deployment program based on the first electronic signature(Strong, [0031], a SBL for memory sub-system 210. The LEDs 233 can provide an indication of the memory sub-system 210 status through various blink codes. The memory controller 215 can be coupled to a temperature sensor (TS) 234, which provides measurements of the temperature of the memory controller 215, [0033], an embodiment of a secure boot could also support digital signature verification);
performing, by executing the deployment program(Strong, [0031], a serial peripheral interface (SPI) NOR boot device 222 having a SPI connection 242 to the memory controller 215, and light emitting diodes (LEDs) 233 having a general purpose input/output (GPIO) connection 243 to the memory controller 215. The SPI NOR Boot Device 222 is a nonvolatile memory that can stores a SBL for memory sub-system 210.),
based on the second electronic signature(Strong, [0033], cryptographic verification of FW during device boot, a secure boot prevents the host 220 from downloading FW using the PBL, because the FW may not be digitally signed and would be untrusted, and disables debug interfaces that could be used to download untrusted FW onto the device. In addition, an embodiment of a secure boot could also support digital signature verification when the host 220);
and completing a booting process of the main board after the first and second verification processes are successful(Strong, [0029], The memory sub-system 210 can be configured as a memory sub-system. The host 220 can communicate with the memory sub-system 210 through an interface 221, such as but not limited to a PCIe host interface, [0033], The boot process for the memory sub-system 210, the memory controller 215 and the microcontroller 216 can operate together to provide a secure boot mode. In some embodiments, a secure boot includes a process where FW is cryptographically verified from memory sub-system 210 power on until the main FW is executing. Supporting secure boot assumes that the boot process starts with a root of trust.).
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Opferman in view of Gunti in further view of Gu’s Processor core supporting a heterogeneous system instruction set architecture by enhancing Opferman in view of Gunti in further view of Gu’s systems for a processor core supporting a heterogenous system to ensure that a computer system is securely booted by executing a boot firmware as taught by Strong to ensure secure and efficient booting of a multi-processor system
The motivation is to ensure secure boot operation in a multi-processor system while optimizing memory usage and performance through the use of compressed executable images and staged signature verification.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Opferman(US Publication No. 2019/0042258 A1) in view of Gunti(US Publication No. 2017/0372074 A1) in further view of Gu (US Publication No. 20060174300 A1) in further view of Strong(US Publication No. 20200082089 A1) in further view of Lee(US Publication No. 2021/0406379 A1).
Regarding Claim 3:
Opferman in view of Gunti in further view of Gu in further view of Strong disclose:
The information processing device according to claim 1…
Opferman in view of Gunti in further view of Gu in further view of Strong do not disclose:
wherein first memory is further configured to store a boot loader, and the first CPU core is configured to, by executing the boot loader before the second CPU executes the deployment program, perform the first verification process
Lee discloses:
wherein first memory is further configured to store a boot loader (Lee, [0026], During the secure boot process, the boot loader 1220 may verify whether the pair of an image of the firmware 1260 and the signature SIG match by using the public key PUK in the electronic device 1200.)
and the first CPU core is configured to, by executing the boot loader before the second CPU executes the deployment program, perform the first verification process (Lee, [0031], … the area 2240 of the electronic device 2200, but the public key PUK may not yet be written in the electronic device 2200 during or immediately after a manufacturing process. In such a case, the boot loader 2220 may verify the integrity of the test firmware 2260 using a public key PUK_T embedded in the boot loader 2220 itself and a signature SIG… [0034], The reason for embedding the signature SIG in the boot loader 3220 is to prevent a test firmware, other than the test firmware intended by the manufacturer, from being executed in the electronic device 3200. By embedding the signature SIG in the boot loader 3220, the signature SIG).
Before the effective filing date of the claimed invention, it would have been obvious to one with ordinary skill in the art to modify Opferman in view of Gunti in further view of Gu in further view of Strong’s Processor core supporting a heterogeneous system instruction set architecture by enhancing Opferman in view of Gunti’s in further view of Gu in further view of Strong’s systems for a processor core supporting a heterogenous system to ensure the firmware and executing the firmware of which integrity has been verified as taught by Lee in order to ensure that the system begins execution only from authenticated untampered code.
The motivation is to ensure that the firmware may be protected from the risk of forgery or alteration by verifying the integrity of the test firmware installed in an electronic device at the time of manufacture and production[Lee, 0014].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MAYASA SHAAWAT whose telephone number is (571)272-3939. The examiner can normally be reached on M-F, 8 AM TO 5 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, JEFFREY PWU can be reached on (571)272-6789. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MAYASA A. SHAAWAT/Examiner, Art Unit 2433
/JEFFREY C PWU/Supervisory Patent Examiner, Art Unit 2433
Prosecution Insights