DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 2-3, 9-10, and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claim 7, it is not clear what “a first memory subsystem that is configured to receive power from a first domain power system that is part of a first power domain, and a second memory subsystem that is configured to receive power from a first domain power system that is part of a first power domain” should be construed as. [0075], [0076] appears to suggest that each memory subsystem has a different domain and “ . . . the unavailability of the 1st networked memory power domain provided by the 1st networked memory power domain power system, which will affect power supplied to the networked memory subsystem 712a coupled to the 1st domain networked memory power system, does not affect power supplied to the networked memory subsystems 714a-716a”. This is further suggested by claim 8 (copy, following an unavailability of the first domain power system that results in a loss of the data on the first memory subsystem, the data from the second memory subsystem to the first memory subsystem). If both memory subsystems are on a single domain, the system would not function. For this rejection, it is assumed each memory subsystem has its own power domain.
As per claim 14, see rejection on claim 7.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Badri et al (Badri, Satyajaswanth, Mukesh Saini, and Neeraj Goel. "An efficient nvm-based architecture for intermittent computing under energy constraints." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31.6 (2023): 725-737) (hereinafter Badri) in view of Sloat et al (US 2022/0066899) (hereinafter Sloat) .
As per claim 1, Badri teaches:
A multi-power-domain emulated persistent memory resource system, comprising:
a first memory subsystem that is configured to receive power from a first domain power system that is part of a first power domain (Badri, Fig. 1. Architecture designs to integrate NVM. (a) Introduce NVM at main memory. (b) Introduce NVM at the LLC and main-memory levels. (c) Introduce NVM at both the cache levels and main-memory level. (d) Introduce NVM-based backup region (BR) at the LLC—under BRI, a first domain power system that is part of a first power domain can be power domain that supplies volatile L1 );
a second memory subsystem that is configured to receive power from a second domain power system that is part of a second power domain that is different than the first power domain (Badri, Fig. 1. Architecture designs to integrate NVM. (a) Introduce NVM at main memory. (b) Introduce NVM at the LLC and main-memory levels. (c) Introduce NVM at both the cache levels and main-memory level. (d) Introduce NVM-based backup region (BR) at the LLC—under BRI, a second power domain can be power domain that supplies STT-RAM at LLC, and PCM ;
a memory interface/data mover subsystem that is coupled to the first memory subsystem and the second memory subsystem (Badri, Fig. 1. Architecture designs to integrate NVM. (a) Introduce NVM at main memory. (b) Introduce NVM at the LLC and main-memory levels. (c) Introduce NVM at both the cache levels and main-memory level. (d) Introduce NVM-based backup region (BR) at the LLC—under BRI, a memory interface/data mover subsystem can be the system that moves data across Architecture-2); and
a System Control Processor (SCP) subsystem that is coupled to the memory interface/data mover subsystem, wherein the SCP subsystem is configured to:
present, to a storage subsystem, an emulated persistent memory resource that is based on the first memory subsystem and the second memory subsystem (Badri, Fig 2 Overview of proposed architecture);
receive, from the storage subsystem a write request that requests the writing of data to the emulated persistent memory resource (Badri, IV. PROPOSED ARCHITECTURE, A. Proposed Architecture—a write request exists in order to have a write hit) ; and
use, in response to receiving the write request, the memory interface/data mover subsystem to write the data to the first memory subsystem and the second memory subsystem (Badri, (Badri, IV. PROPOSED ARCHITECTURE, A. Proposed Architecture—under BRI, write the data to the first memory subsystem and the second memory subsystem can be writing to L1 and STT RAM & PCM ), and
wherein the memory interface/data mover subsystem is configured to:
copy, following an unavailability of the first domain power system that results in a loss of the data on the first memory subsystem, the data from the second memory subsystem to the first memory subsystem.
Badri does not expressly teach:
wherein the memory interface/data mover subsystem is configured to:
copy, following an unavailability of the first domain power system that results in a loss of the data on the first memory subsystem, the data from the second memory subsystem to the first memory subsystem.
However, Sloat discloses:
wherein the memory interface/data mover subsystem is configured to:
copy, following an unavailability of the first domain power system that results in a loss of the data on the first memory subsystem, the data from the second memory subsystem to the first memory subsystem (Sloat, [0001]).
Both Sloat and Badri pertain to the art of memory architecture.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Sloat’s method of restoring data after power failure because restoring memory after a power failure ensures data continuity, prevents data corruption, and drastically minimizes system downtime.
As per claim 5, Badri/Sloat teaches:
The system of claim 1 (see rejection on claim 1), wherein each of the first memory subsystem and the second memory subsystem include at least one Dynamic Random Access Memory (DRAM) device (Badri, pg 726, II. BACKGROUND AND RELATED WORKS).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Badri/Sloat as applied to claim 1 above, and further in view of Prasad et al (US 2020/0026443) (hereinafter Prasad) .
As per claim 4, Badri/Sloat teaches:
The system of claim 1 (see rejection on claim 1).
Badri/Sloat does not expressly teach:
wherein the emulated persistent memory resource is a virtual Non-Volatile Dual Inline Memory Module (vNVDIMM).
However, Prasad discloses:
wherein the emulated persistent memory resource is a virtual Non-Volatile Dual Inline Memory Module (vNVDIMM) (Prasad, Abstract).
Both Prasad and Badri/Sloat pertain to the art of memory architecture.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Prasad’s method of using vNVDIMM because using a vNVDIMM (Virtual Non-Volatile Dual In-line Memory Module) allows a virtual machine (VM) to access persistent memory (PMem) at near-DRAM speeds.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Badri/Sloat as applied to claim 1 above, and further in view of Khosrowpour et al (US 2025/0138997) (hereinafter Khosrowpour).
As per claim 6, Badri/Sloat teaches:
The system of claim 1 (see rejection on claim 1).
Badri/Sloat does not expressly teach:
wherein the memory interface/data mover subsystem includes a Smart Data Acceleration Interface (SDXI).
However, Khosrowpour discloses:
wherein the memory interface/data mover subsystem includes a Smart Data Acceleration Interface (SDXI) (Khosrowpour, [0013]).
Both Khosrowpour and Badri/Sloat pertain to the art of memory architecture.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Khosrowpour’s method of using SDXI because SDXI offers significant CPU offloading.
Claims 7, 12, 14, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Badri in view of Benz et al (Benz, Thomas, et al. "A high-performance, energy-efficient modular DMA engine architecture." IEEE Transactions on Computers 73.1 (2023): 263-277) (hereinafter Benz).
As per claim 7, Badri teaches:
An Information Handling System (IHS), comprising:
a System Control Processor (SCP) processing system; and an SCP memory system that is coupled to the SCP processing system and that includes instructions that, when executed by the SCP processing system, cause the SCP processing system to provide an SCP engine that is configured to:
present, to a storage subsystem that is coupled to the SCP processing system, an emulated persistent memory resource that is based on a first memory subsystem that is configured to receive power from a first domain power system that is part of a first power domain, and a second memory subsystem that is configured to receive power from a first domain power system that is part of a first power domain (see rejection on claim 1);
Badri does not expressly teach:
receive, from the storage subsystem, a write request that requests the writing of data to the emulated persistent memory resource;
generate, in response to receiving the write request, a write instruction that is configured to cause a memory interface/data mover engine to write the data to the first memory subsystem and to the second memory subsystem; and
transmit, to the memory interface/data mover engine, the write instruction.
However, Benz discloses:
receive, from the storage subsystem, a write request that requests the writing of data to the emulated persistent memory resource (Benz, pg 265, A. Front-End, under BRI, a write request can be instructions encoding iDMA transfers);
generate, in response to receiving the write request, a write instruction that is configured to cause a memory interface/data mover engine to write the data to the first memory subsystem and to the second memory subsystem (Benz, pg 264, II. ARCHITECTURE—under BRI, a write instruction can be transfer descriptors); and
transmit, to the memory interface/data mover engine, the write instruction (Benz, pg 264, II. ARCHITECTURE—under BRI, “transmit” can be the step before “the back-end accepts a ID transfer descriptor specifying a source address . . . protocol, and back-end options”).
Both Benz and Badri pertain to the art of memory architecture.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Benz’s method of generating write instructions because this design allows the hardware to handle complex, non-contiguous, or multi-block data transfers autonomously without CPU intervention
As per claim 12, Badri/Benz teaches:
The IHS of claim 7 (See rejection on claim 7), wherein each of the first memory subsystem and the second memory subsystem include at least one Dynamic Random Access Memory (DRAM) device (Badri, pg 726, II. BACKGROUND AND RELATED WORKS).
As per claim 14, see rejection on claim 7.
As per claim 19, see rejection on claim 12.
Claims 8 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Badri/Benz as applied above, and further in view of Sloat.
As per claim 8, Badri/Benz teaches:
The IHS of claim 7 (see rection on claim 7), further comprising:
a memory interface/data mover processing system (see rejection on claim 1);
Badri/Benz does not expressly teach:
a memory interface/data mover memory system that is coupled to the memory interface/data mover processing system and that includes instructions that, when executed by the memory interface/data mover processing system, cause the memory interface/data mover processing system to provide the memory interface/data mover engine that is configured to:
copy, following an unavailability of the first domain power system that results in a loss of the data on the first memory subsystem, the data from the second memory subsystem to the first memory subsystem.
However, Sloat discloses:
a memory interface/data mover memory system that is coupled to the memory interface/data mover processing system and that includes instructions that, when executed by the memory interface/data mover processing system, cause the memory interface/data mover processing system to provide the memory interface/data mover engine that is configured to:
copy, following an unavailability of the first domain power system that results in a loss of the data on the first memory subsystem, the data from the second memory subsystem to the first memory subsystem (Sloat, [0001]).
Both Sloat and Badri/Benz pertain to the art of memory architecture.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Sloat’s method of restoring data after power failure because restoring memory after a power failure ensures data continuity, prevents data corruption, and drastically minimizes system downtime.
As per claim 15, see rejection on claim 8.
Claims 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Badri/Benz as applied above, and further in view of Prasad.
As per claim 11, Badri/Benz teaches:
The IHS of claim 7 (see rejection on claim 7).
Badri/Benz does not expressly teach:
wherein the emulated persistent memory resource is a virtual Non-Volatile Dual Inline Memory Module (vNVDIMM).
However, Prasad discloses:
wherein the emulated persistent memory resource is a virtual Non-Volatile Dual Inline Memory Module (vNVDIMM) (Prasad, Abstract).
Both Prasad and Badri/Benz pertain to the art of memory architecture.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Prasad’s method of using vNVDIMM because using a vNVDIMM (Virtual Non-Volatile Dual In-line Memory Module) allows a virtual machine (VM) to access persistent memory (PMem) at near-DRAM speeds.
As per claim 18, see rejection on claim 11.
Claims 13 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Badri/Benz/Sloat as applied above, and further in view of Khosrowpour.
As per claim 13, Badri/Benz/Sloat teaches:
The IHS of claim 8 (see rejection on claim 8).
Badri/Benz/Sloat does not expressly teach:
wherein the memory interface/data mover engine provides a Smart Data Acceleration Interface (SDXI).
However, Khosrowpour discloses:
wherein the memory interface/data mover engine provides a Smart Data Acceleration Interface (SDXI) (Khosrowpour, [0013]).
Both Khosrowpour and Badri/Benz/Sloat pertain to the art of memory architecture.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use Khosrowpour’s method of using SDXI because SDXI offers significant CPU offloading.
As per claim 20, see rejection on claim 13.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 12664081 teaches a method of using NVMs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLIE SUN whose telephone number is (571)270-5100. The examiner can normally be reached 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Pierre Vital can be reached at (571) 272-4215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHARLIE SUN/Primary Examiner, Art Unit 2198
