Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s response to previous office action was filed 12/22/2025. No claims have been amended. Claims 1-24 are pending.
Response to Arguments
Applicant's arguments filed 12/22/2025 have been fully considered but they are not persuasive. Applicant argues that Pedersen does not teach a detection circuitry configured to detect “a respective error for each circuit element” and circuitry configured to selectively enable and disable one or more of the set of redundant circuit elements for functional use in a circuit based on the “respective errors”. While examiner generally agrees with applicant’s characterization of Pederson, examiner asserts that Pederson reads on the claim as presented. The claim requires detection of errors in each circuit element, not that the system detects errors for each circuit at the same time. Pederson does teach detecting an error in a circuit and switching the circuitry path based on the detection. One path is disabled while another is enabled. The system will monitor the circuit and detect errors and enable/disable elements as needed, and in this way, errors can be detected for each element (see examiner’s rejection of claim 1 below for further detail).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 9 – 14, 16 and 22-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Publication 20130002287-(Pedersen et al.) [herein “Pedersen”].
Regarding claim 1 –
Pedersen teaches (a) system comprising: a set of redundant circuit elements; ” In one exemplary embodiment, an apparatus includes two sets of circuit elements used in two configurations of the apparatus. The first set of circuit elements is used in a first configuration of the apparatus, whereas the second set of circuit elements is used in a second configuration of the apparatus” (Page 1, Paragraph [0004]).
Pedersen also teaches detection circuitry configured to detect a respective error for each circuit element of the set of redundant circuit elements; “Failures in the user's design may typically be detected by self-test circuitry implemented internally to FPGA 103” (Page 8, Paragraph [0077]).
In addition, Pedersen teaches control circuitry configured to selectively enable and disable one or more of the set of redundant circuit elements for functional use in a circuit based on the respective errors, (Fig 3) plus “FIG. 3 shows circuitry for switching of configurations according to another exemplary embodiment. In this embodiment, controller 30 uses signals 42A, 44A, 46A, and 48A to control, respectively, controlled switches 42, 44, 46, and 48. In response to their respective control signals, switches 42, 44, 46, and 48 may open or close, as desired” (Page 3, Paragraph [0041]) plus “circuit 10 includes circuitry and coupling mechanisms (e.g., MUXs, demultiplexers (DEMUXs ), pass transistors, switching matrices, etc.) that allow controller 30 to switch configurations of circuit 10. In other words, such circuitry and coupling mechanisms allow controller 30 to couple active circuit elements 20 in a given configuration in a manner that provides the overall desired functionality of circuit 10. Similarly, such circuitry and coupling mechanisms provide controller 30 with the capability to uncouple or inactivate other circuit elements 20 (e.g., those circuit elements used in other configurations of circuit 10), i.e., configure those circuit elements 20 so that they do not realize the functionality of circuit 10 during that particular configuration” (Page 3, Paragraph [0038]).
Regarding claim 3 –
Pedersen teaches all the limitations of claim 1 above.
Pedersen also teaches wherein each circuit element comprises a transistor, “Modern semiconductor fabrication technologies, such as those used to make complementary metal oxide semiconductor (CMOS) devices and ICs, have resulted in the introduction of new mechanisms or phenomena that change device ( e.g., transistors, such asp-type metal oxide semiconductor (PMOS) or n-type metal oxide semiconductor (NMOS) transistors) characteristics, sometimes in relatively significant ways. Examples of such adverse phenomena known to persons of ordinary skill in the art include negative bias temperature instability (NBTI) in PMOS devices, and positive bias temperature instability (PBTI) in NMOS devices” (Page 1, Paragraph [0019]) plus “As a result of the above phenomena or other phenomena, device or circuit characteristics change during the lifecycle of the circuit elements such as transistors” (Page 1, Paragraph [0021]).
Regarding claim 9 –
Pedersen teaches all the limitations of claim 1 above.
Pedersen also teaches wherein the detection circuitry is configured to perform detection of the respective error for each circuit element of the set of redundant circuit elements in response to a stimulus, (Fig 4) plus “Initialization circuit 139 may cause the performance of various functions at reset or power-up of FPGA 103. I/O circuitry 112 may constitute a wide variety of I/O devices or circuits. I/O circuitry 112 may couple to various parts of FPGA 103, for example, programmable logic 106 and programmable interconnect 109. I/O circuitry 112 provides a mechanism and circuitry for various blocks within FPGA 103 to communicate with external circuitry or devices. Test/debug circuitry 115 facilitates the testing and troubleshooting of various blocks and circuits within FPGA 103. Test/debug circuitry 115 may include a variety of blocks or circuits known to persons of ordinary skill in the art. For example, test/debug circuitry 115 may include circuits for performing tests after FPGA 103 powers up or resets, as desired” (Page 4, Paragraph [0049]).
Regarding claim 10 –
Pedersen teaches all the limitations of claim 9 above.
Pedersen also teaches wherein the stimulus comprises one of testing of the circuit, powering up of the circuit, a change of temperature associated with the circuit, a passage of a predetermined period of time, and a user command Examiner is presented with several choices to examine and selects: “Powering Up” - (Fig 4) plus “Initialization circuit 139 may cause the performance of various functions at reset or power-up of FPGA 103. I/O circuitry 112 may constitute a wide variety of I/O devices or circuits. I/O circuitry 112 may couple to various parts of FPGA 103, for example, programmable logic 106 and programmable interconnect 109. I/O circuitry 112 provides a mechanism and circuitry for various blocks within FPGA 103 to communicate with external circuitry or devices. Test/debug circuitry 115 facilitates the testing and troubleshooting of various blocks and circuits within FPGA 103. Test/debug circuitry 115 may include a variety of blocks or circuits known to persons of ordinary skill in the art. For example, test/debug circuitry 115 may include circuits for performing tests after FPGA 103 powers up or resets, as desired” (Page 4, Paragraph [0049]).
Regarding claim 11 –
Pedersen teaches all the limitations of claim 1 above.
Pedersen also teaches wherein the detection circuitry is on the same die as the set of redundant circuit elements, (Fig 4) plus “Failures in the user's design may typically be detected by self-test circuitry implemented internally to FPGA 103” (Page 8, Paragraph [0077]).
Regarding claim 12 –
Pedersen teaches all the limitations of claim 1 above.
Pedersen also teaches wherein the control circuitry is on the same die as the set of redundant circuit elements, (Fig 4, Item 30 “Controller”).
Regarding claim 13 –
Pedersen teaches all the limitations of claim 1 above.
Pedersen also teaches further comprising logic on the same die as the set of redundant circuit elements to define a trigger to cause the detection circuitry to re-execute detection of the respective error for each circuit element of the set of redundant circuit elements and to cause the control circuitry to re-execute selectively enabling and disabling of one or more of the set of redundant circuit elements for functional use in the circuit based on the respective errors, “Failures in the user's design may typically be detected by self-test circuitry implemented internally to FPGA 103” (Page 8, Paragraph [0077]) plus (Fig 3) plus “FIG. 3 shows circuitry for switching of configurations according to another exemplary embodiment. In this embodiment, controller 30 uses signals 42A, 44A, 46A, and 48A to control, respectively, controlled switches 42, 44, 46, and 48. In response to their respective control signals, switches 42, 44, 46, and 48 may open or close, as desired” (Page 3, Paragraph [0041]) plus “circuit 10 includes circuitry and coupling mechanisms (e.g., MUXs, demultiplexers (DEMUXs ), pass transistors, switching matrices, etc.) that allow controller 30 to switch configurations of circuit 10. In other words, such circuitry and coupling mechanisms allow controller 30 to couple active circuit elements 20 in a given configuration in a manner that provides the overall desired functionality of circuit 10. Similarly, such circuitry and coupling mechanisms provide controller 30 with the capability to uncouple or inactivate other circuit elements 20 (e.g., those circuit elements used in other configurations of circuit 10), i.e., configure those circuit elements 20 so that they do not realize the functionality of circuit 10 during that particular configuration” (Page 3, Paragraph [0038]).
Regarding claim 14 –
Pedersen teaches (a) method comprising: detecting a respective error for each circuit element of a set of redundant circuit elements; “Failures in the user's design may typically be detected by self-test circuitry implemented internally to FPGA 103” (Page 8, Paragraph [0077]).
Pedersen also teaches selectively enabling and disabling one or more of the set of redundant circuit elements for functional use in a circuit based on the respective errors, (Fig 3) plus “FIG. 3 shows circuitry for switching of configurations according to another exemplary embodiment. In this embodiment, controller 30 uses signals 42A, 44A, 46A, and 48A to control, respectively, controlled switches 42, 44, 46, and 48. In response to their respective control signals, switches 42, 44, 46, and 48 may open or close, as desired” (Page 3, Paragraph [0041]) plus “circuit 10 includes circuitry and coupling mechanisms (e.g., MUXs, demultiplexers (DEMUXs ), pass transistors, switching matrices, etc.) that allow controller 30 to switch configurations of circuit 10. In other words, such circuitry and coupling mechanisms allow controller 30 to couple active circuit elements 20 in a given configuration in a manner that provides the overall desired functionality of circuit 10. Similarly, such circuitry and coupling mechanisms provide controller 30 with the capability to uncouple or inactivate other circuit elements 20 (e.g., those circuit elements used in other configurations of circuit 10), i.e., configure those circuit elements 20 so that they do not realize the functionality of circuit 10 during that particular configuration” (Page 3, Paragraph [0038]).
Regarding claim 16 –
Pedersen teaches all the limitations of claim 14 above.
Pedersen also teaches wherein each circuit element comprises a transistor, “Modern semiconductor fabrication technologies, such as those used to make complementary metal oxide semiconductor (CMOS) devices and ICs, have resulted in the introduction of new mechanisms or phenomena that change device ( e.g., transistors, such asp-type metal oxide semiconductor (PMOS) or n-type metal oxide semiconductor (NMOS) transistors) characteristics, sometimes in relatively significant ways. Examples of such adverse phenomena known to persons of ordinary skill in the art include negative bias temperature instability (NBTI) in PMOS devices, and positive bias temperature instability (PBTI) in NMOS devices” (Page 1, Paragraph [0019]) plus “As a result of the above phenomena or other phenomena, device or circuit characteristics change during the lifecycle of the circuit elements such as transistors” (Page 1, Paragraph [0021]).
Regarding claim 22 –
Pedersen teaches all the limitations of claim 14 above.
Pedersen also teaches further comprising performing detection of the respective error for each circuit element of the set of redundant circuit elements in response to a stimulus, (Fig 4) plus “Initialization circuit 139 may cause the performance of various functions at reset or power-up of FPGA 103. I/O circuitry 112 may constitute a wide variety of I/O devices or circuits. I/O circuitry 112 may couple to various parts of FPGA 103, for example, programmable logic 106 and programmable interconnect 109. I/O circuitry 112 provides a mechanism and circuitry for various blocks within FPGA 103 to communicate with external circuitry or devices. Test/debug circuitry 115 facilitates the testing and troubleshooting of various blocks and circuits within FPGA 103. Test/debug circuitry 115 may include a variety of blocks or circuits known to persons of ordinary skill in the art. For example, test/debug circuitry 115 may include circuits for performing tests after FPGA 103 powers up or resets, as desired” (Page 4, Paragraph [0049]).
Regarding claim 23 –
Pedersen teaches all the limitations of claim 22 above.
Pedersen also teaches wherein the stimulus comprises one of testing of the circuit, powering up of the circuit, a change of temperature associated with the circuit, and a passage of a predetermined period of time. Examiner is presented with several choices to examine and selects: “Powering Up” - (Fig 4) plus “Initialization circuit 139 may cause the performance of various functions at reset or power-up of FPGA 103. I/O circuitry 112 may constitute a wide variety of I/O devices or circuits. I/O circuitry 112 may couple to various parts of FPGA 103, for example, programmable logic 106 and programmable interconnect 109. I/O circuitry 112 provides a mechanism and circuitry for various blocks within FPGA 103 to communicate with external circuitry or devices. Test/debug circuitry 115 facilitates the testing and troubleshooting of various blocks and circuits within FPGA 103. Test/debug circuitry 115 may include a variety of blocks or circuits known to persons of ordinary skill in the art. For example, test/debug circuitry 115 may include circuits for performing tests after FPGA 103 powers up or resets, as desired” (Page 4, Paragraph [0049]).
Regarding claim 24 –
Pedersen teaches all the limitations of claim 14 above.
Pedersen also teaches further comprising defining, with logic on the same die as the set of redundant circuit elements, a trigger to cause the detection circuitry to re-execute detection of the respective error for each circuit element of the set of redundant circuit elements and to cause the control circuitry to re-execute selectively enabling and disabling of one or more of the set of redundant circuit elements for functional use in the circuit based on the respective errors, “Failures in the user's design may typically be detected by self-test circuitry implemented internally to FPGA 103” (Page 8, Paragraph [0077]) plus (Fig 3) plus “FIG. 3 shows circuitry for switching of configurations according to another exemplary embodiment. In this embodiment, controller 30 uses signals 42A, 44A, 46A, and 48A to control, respectively, controlled switches 42, 44, 46, and 48. In response to their respective control signals, switches 42, 44, 46, and 48 may open or close, as desired” (Page 3, Paragraph [0041]) plus “circuit 10 includes circuitry and coupling mechanisms (e.g., MUXs, demultiplexers (DEMUXs ), pass transistors, switching matrices, etc.) that allow controller 30 to switch configurations of circuit 10. In other words, such circuitry and coupling mechanisms allow controller 30 to couple active circuit elements 20 in a given configuration in a manner that provides the overall desired functionality of circuit 10. Similarly, such circuitry and coupling mechanisms provide controller 30 with the capability to uncouple or inactivate other circuit elements 20 (e.g., those circuit elements used in other configurations of circuit 10), i.e., configure those circuit elements 20 so that they do not realize the functionality of circuit 10 during that particular configuration” (Page 3, Paragraph [0038]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 20130002287-(Pedersen et al.) [herein “Pedersen”], in view of U.S. Patent Publication 20200312406-(Sharma et al.) [herein “Sharma”].
Regarding claim 2 –
Pedersen teaches all the limitations of claim 1 above.
Pedersen does not teach wherein the respective error for each circuit element comprises one or more of a random telegraph noise, flicker noise, shot noise, and offset associated with such circuit element.
Sharma, however teaches wherein the respective error for each circuit element comprises one or more of a random telegraph noise, flicker noise, shot noise, and offset associated with such circuit element, Examiner is presented with several choices to examine and selects: “Random Telegraph Noise”; “Random Telegraph Noise (RTN), for example, results in the depletion of a portion of the conductive filament due to the presence of temporarily trapped charges. RTN can result in intermittent read errors with sufficient probability to cause an unacceptable operation of the system” (Page 2, Paragraph [0020]).
Pedersen and Sharma are analogous art because they are both directed to the design of advanced circuitry with analog components. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching on redundant analog circuit selection of Pedersen with the teachings regarding Random Telegraph Noise (RTN) in analog circuits of Sharma, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to switch, enable and disable analog circuits to prevent RTN.
Regarding claim 15 –
Pedersen teaches all the limitations of claim 14 above.
Pedersen does not teach wherein the respective error for each circuit element comprises one or more of a random telegraph noise, flicker noise, shot noise, and offset associated with such circuit element.
Sharma, however teaches wherein the respective error for each circuit element comprises one or more of a random telegraph noise, flicker noise, shot noise, and offset associated with such circuit element. Examiner is presented with several choices to examine and selects: “Random Telegraph Noise”; “Random Telegraph Noise (RTN), for example, results in the depletion of a portion of the conductive filament due to the presence of temporarily trapped charges. RTN can result in intermittent read errors with sufficient probability to cause an unacceptable operation of the system” (Page 2, Paragraph [0020]).
Pedersen and Sharma are analogous art because they are both directed to the design of advanced circuitry with analog components. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching on redundant analog circuit selection of Pedersen with the teachings regarding Random Telegraph Noise (RTN) in analog circuits of Sharma, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to switch, enable and disable analog circuits to prevent RTN.
Claims 4, 7, 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 20130002287-(Pedersen et al.) [herein “Pedersen”], in view of U.S. Patent 556352-(Hastings et al.) [herein “Hastings”].
Regarding claim 4 –
Pedersen teaches all the limitations of claim 1 above.
Pedersen does not teach wherein each circuit element comprises a differential pair.
Hastings, however teaches wherein each circuit element comprises a differential pair, (Fig 5) plus “The operational amplifier-comparator circuit input stages are differential pairs (see FIG. 5)” (Col 16, Lines 32-34).
Pedersen and Hastings are analogous art because they are both directed to the design of advanced circuitry with analog components. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching on redundant analog circuit selection of Pedersen with the teachings regarding differential pairs in analog circuits of Hastings, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to switch, enable and disable analog circuits consisting of differential pairs.
Regarding claim 7 –
Pedersen teaches all the limitations of claim 1 above.
Pedersen does not teach wherein each circuit element comprises an operational amplifier.
Hastings, however teaches wherein each circuit element comprises an operational amplifier, “At least one analog circuit may be an operational amplifier, a voltage comparator circuit, or preferably, a circuit that is selectively configurable either as an operational amplifier or a comparator in dependence upon the programmable digital logic states” (Col 6, Lines 12-16).
Pedersen and Hastings are analogous art because they are both directed to the design of advanced circuitry with analog components. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching on redundant analog circuit selection of Pedersen with the teachings regarding use of operational amplifiers in analog circuits of Hastings, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to switch, enable and disable analog circuits consisting of operational amplifiers.
Regarding claim 17 –
Pedersen teaches all the limitations of claim 14 above.
Pedersen does not teach wherein each circuit element comprises a differential pair.
Hastings, however teaches wherein each circuit element comprises a differential pair, (Fig 5) plus “The operational amplifier-comparator circuit input stages are differential pairs (see FIG. 5)” (Col 16, Lines 32-34).
Pedersen and Hastings are analogous art because they are both directed to the design of advanced circuitry with analog components. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching on redundant analog circuit selection of Pedersen with the teachings regarding differential pairs in analog circuits of Hastings, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to switch, enable and disable analog circuits consisting of differential pairs.
Regarding claim 20 –
Pedersen teaches all the limitations of claim 14 above.
Pedersen does not teach wherein each circuit element comprises an operational amplifier.
Hastings, however teaches wherein each circuit element comprises an operational amplifier, “At least one analog circuit may be an operational amplifier, a voltage comparator circuit, or preferably, a circuit that is selectively configurable either as an operational amplifier or a comparator in dependence upon the programmable digital logic states” (Col 6, Lines 12-16).
Pedersen and Hastings are analogous art because they are both directed to the design of advanced circuitry with analog components. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching on redundant analog circuit selection of Pedersen with the teachings regarding use of operational amplifiers in analog circuits of Hastings, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to switch, enable and disable analog circuits consisting of operational amplifiers.
Claims 5 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 20130002287-(Pedersen et al.) [herein “Pedersen”], in view of U.S. Patent Publication 20200228130-(Buelow et al.) [herein “Buelow”[.
Regarding claim 5 –
Pedersen teaches all the limitations of claim 1 above.
Pedersen does not teach wherein each circuit element comprises a current mirror.
Buelow, however teaches wherein each circuit element comprises a current mirror, (Figs 1, 3 and 6) plus “FIG. 6 shows another possible embodiment of analog input circuit 14 of switching circuit 12 illustrated in FIG. 1, which differs from the embodiment illustrated in FIG. 3 in that first signal S1 and second signal S2 are tapped at resistors in parallel current paths, the parallel current paths being connected to a current mirror, so that the currents flowing through the current paths are in a fixed ratio to each other (for example 1:1)” (Page 4, Paragraph [0053]).
Pedersen and Buelow are analogous art because they are both directed to the design of advanced circuitry with analog components. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching on redundant analog circuit selection of Pedersen with the teachings regarding use of current mirrors in analog circuits of Buelow, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to switch, enable and disable analog circuits consisting of current mirrors.
Regarding claim 18 –
Pedersen teaches all the limitations of claim 14 above.
Pedersen does not teach wherein each circuit element comprises a current mirror.
Buelow, however teaches wherein each circuit element comprises a current mirror, (Figs 1, 3 and 6) plus “FIG. 6 shows another possible embodiment of analog input circuit 14 of switching circuit 12 illustrated in FIG. 1, which differs from the embodiment illustrated in FIG. 3 in that first signal S1 and second signal S2 are tapped at resistors in parallel current paths, the parallel current paths being connected to a current mirror, so that the currents flowing through the current paths are in a fixed ratio to each other (for example 1:1)” (Page 4, Paragraph [0053]).
Pedersen and Buelow are analogous art because they are both directed to the design of advanced circuitry with analog components. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching on redundant analog circuit selection of Pedersen with the teachings regarding use of current mirrors in analog circuits of Buelow, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to switch, enable and disable analog circuits consisting of current mirrors.
Claims 6 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 20130002287-(Pedersen et al.) [herein “Pedersen”], in view of International Patent Publication WO2020131121-(Lucero et al.)-MODULAR SYSTEM FOR INTERNET OF THINGS [herein “Lucero”].
Regarding claim 6 –
Pedersen teaches all the limitations of claim 1 above.
Pedersen does not teach wherein each circuit element comprises a bipolar junction transistor pair.
Lucero, however teaches wherein each circuit element comprises a bipolar junction transistor pair, “This may be accomplished using analog circuits (for example, using bipolar junction transistor pairs or BJT pairs)” (Page 61, Paragraph [0197]).
Pedersen and Lucero are analogous art because they are both directed to the design of advanced circuitry with analog components. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching on redundant analog circuit selection of Pedersen with the teachings regarding use of bipolar junction transistor pairs in analog circuits of Lucero, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to switch, enable and disable analog circuits consisting of bipolar junction transistor pairs.
Regarding claim 19 –
Pedersen teaches all the limitations of claim 14 above.
Pedersen does not teach wherein each circuit element comprises a bipolar junction transistor pair.
Lucero, however teaches wherein each circuit element comprises a bipolar junction transistor pair, “This may be accomplished using analog circuits (for example, using bipolar junction transistor pairs or BJT pairs)” (Page 61, Paragraph [0197]).
Pedersen and Lucero are analogous art because they are both directed to the design of advanced circuitry with analog components. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching on redundant analog circuit selection of Pedersen with the teachings regarding use of bipolar junction transistor pairs in analog circuits of Lucero, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to switch, enable and disable analog circuits consisting of bipolar junction transistor pairs.
Claims 8 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Publication 20130002287-(Pedersen et al.) [herein “Pedersen”], in view of Chinese Patent Publication CN104065385A-(ZHUANG)-“Signal decoding circuit applied to wireless charging or radio frequency identification system(24-Sep-2014 )-(IPCOM Translation).
Regarding claim 8 –
Pedersen teaches all the limitations of claim 1 above.
Pedersen does not teach further comprising biasing circuitry to provide a range of direct current biases under which to test the set of redundant circuit elements for their respective errors at a variety of operating points.
Zhuang, however teaches further comprising biasing circuitry to provide a range of direct current biases under which to test the set of redundant circuit elements for their respective errors at a variety of operating points, (Fig 4) plus “Fig. 4 illustrates the circuit diagram for the voltage decoding circuit that is applied to wireless charging or radio-frequency recognition system according to the embodiment of the present invention. Please refer to Fig. 4, this voltage decoding circuit comprises that one by diode D6, the peak detection circuit that resistance R 31 and capacitor C 39 form, one isolation capacitance C33, a direct-flow biasing circuit being formed by resistance R 43 and R42 dividing potential drop” (Page 12, 5th Paragraph).
Pedersen and Zhuang are analogous art because they are both directed to the design of advanced circuitry with analog components. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching on redundant analog circuit selection of Pedersen with the teachings regarding use of biasing circuitry of Zhuang, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to test analog circuits through the use of biasing circuitry.
Regarding claim 21 –
Pedersen teaches all the limitations of claim 14 above.
Pedersen does not teach further comprising providing a range of direct current biases under which to test the set of redundant circuit elements for their respective errors at a variety of operating points.
Zhuang, however teaches further comprising providing a range of direct current biases under which to test the set of redundant circuit elements for their respective errors at a variety of operating points, (Fig 4) plus “Fig. 4 illustrates the circuit diagram for the voltage decoding circuit that is applied to wireless charging or radio-frequency recognition system according to the embodiment of the present invention. Please refer to Fig. 4, this voltage decoding circuit comprises that one by diode D6, the peak detection circuit that resistance R 31 and capacitor C 39 form, one isolation capacitance C33, a direct-flow biasing circuit being formed by resistance R 43 and R42 dividing potential drop” (Page 12, 5th Paragraph).
Pedersen and Zhuang are analogous art because they are both directed to the design of advanced circuitry with analog components. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching on redundant analog circuit selection of Pedersen with the teachings regarding use of biasing circuitry of Zhuang, since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of the ordinary skill in the art would have recognized that the results of this combination would provide a predictable result of a system able to test analog circuits through the use of biasing circuitry.
Further Prior Art
Fujiwara – US 9,666,3074 – teaches redundant error detection on multiple circuit elements prior to receiving the data using error detect latches which can be disabled.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARK D FEATHERSTONE whose telephone number is (571)270-3750. The examiner can normally be reached Monday-Friday 9:00AM - 5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Cottingham can be reached at 571-272-1400. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
MARK D. FEATHERSTONE
Supervisory Patent Examiner
Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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