DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election Restriction
Claims 1-20 were initially presented for examination. In response to a restriction requirement, Applicants elected claims of Group I, which consists of claims 1-10 and 14-20. Applicants are requested to cancel non-elected claims 11-13 in subsequent communication. Claims 1-10 and 14-20 are considered on the merits.
Information Disclosure Statement
The references listed in the information disclosure statement (IDS) submitted have been considered. The submission complies with the provisions of 37 CFR 1.9 /. Form PTO-1449 is signed and attached hereto.
Specification
The specification is accepted.
Drawings
The formal drawings are accepted.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 1 02, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Magnavacca et al. “herein Magnavacca” (U.S. PN: 12,141,466) in view of Avraham et al. “herein Avraham” (U.S. PN: 10,372,539).
As per claim 1:
Magnavacca substantially teaches or discloses a memory device comprising: a memory cell array including a first memory region storing first data (see col. 4, lines 17-36, col. 14, lines 32-39), a page buffer connected to the memory cell array and including a first latch configured to store data read from the memory cell array (see col. 4, lines 49-56, col. 14, lines 39-45, col. 15, lines 7-25, and a control logic circuit configured to receive parity adjustment information from an external device and control an operation of the memory cell array (see col. 6, lines 6-14, col. 9, lines 29-67 to col. 10, lines 1-20, col. 11, lines 22-33) wherein the first data includes first user data and first parity data including parity bits generated based on the first user data (see col. 7, lines 11-24), and wherein the control logic circuit is configured to adjust a size of the first parity data, based on the parity adjustment information, and dump the adjusted first parity data to the first latch.
Magnavacca substantially teaches the claimed invention described in claim 1 (as rejected above).
However, Magnavacca does not explicitly teach that a control logic circuit is configured to adjust a size of the first parity data, based on the parity adjustment information
Avraham, in an analogous art, teaches a control logic circuit is configured to adjust a size of the first parity data, based on the parity adjustment information “the controller 130 is configured to determine parity sizes associated with the first data and the second data. In a particular example, the ECC engine is configured to determine a first size associated with the first data and a second parity size associated with the second data. The first parity size is different than (i.e., greater than or less than) the second parity size” (View Avraham, col. 3, lines 47-62).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Magnavacca with the teachings of Avraham by adjusting the size of the first parity data based on the parity adjustment information.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention because one of ordinary skill in the art would have recognized that by adjusting the size of the parity data based on the parity adjustment information would increase efficiency of storage usage (e.g., by increasing an amount of parity allocated to higher priority data) (View Avraham, col. 4, lines 9-14).
As per claim 2:
The combination of Magnavacca and Avraham substantially teach the claimed invention described in claim 1 (as rejected above) including wherein the memory cell array further includes a second memory region including second data, the second data includes second user data and second parity data including parity bits generated based on the second user data, and a size of the first parity data is different from a size of the second parity data. (View Avraham col. 3, lines 47-62).
As per claim 9:
The combination of Magnavacca and Avraham substantially teach the claimed invention described in claim 1 (as rejected above) including wherein the parity adjustment information includes information indicating a format and size of parity data related to the first memory region and is generated based on reliability information of the first memory region (View Avraham col. 3, lines 63-67 to col. 4, lines 1-14).
Allowable subject matter
Claims 3-8 and 10 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten independent from including all of the limitation of the base claim and any intervening claims.
Independent claim 14 of the present application teaches, for example, “A storage device comprising: a memory device configured to adjust a size of first parity data, based on parity adjustment information, and output the first parity data having the adjusted size; and a memory controller configured to control an operation of the memory device, wherein the memory device includes: a memory cell array including a plurality of memory regions; a page buffer connected to the memory cell array and including a first latch configured to store data read from the memory cell array; and a control logic circuit configured to receive the parity adjustment information from the memory controller and control an operation of the memory cell array, and wherein the memory controller includes: a parity controller including reliability information which includes information indicating reliability of the plurality of memory regions included in the memory device, and the parity controller configured to: determine a format and size of the first parity data, based on the reliability information of a memory region in which user data corresponding to the first parity data is to be stored, and provide the parity adjustment information indicating the determined format and size of the first parity data to the memory device”.
The prior arts of record including the IDS filed by the applicant taken singly or incombination fail to teach, anticipate, suggest, or render obvious the foregoing limitations, “a memory device configured to adjust a size of first parity data, based on parity adjustment information, and output the first parity data having the adjusted size; and a memory controller configured to control an operation of the memory device, wherein the memory device includes: a memory cell array including a plurality of memory regions; a page buffer connected to the memory cell array and including a first latch configured to store data read from the memory cell array; and a control logic circuit configured to receive the parity adjustment information from the memory controller and control an operation of the memory cell array, and wherein the memory controller includes: a parity controller including reliability information which includes information indicating reliability of the plurality of memory regions included in the memory device, and the parity controller configured to: determine a format and size of the first parity data, based on the reliability information of a memory region in which user data corresponding to the first parity data is to be stored, and provide the parity adjustment information indicating the determined format and size of the first parity data to the memory device”. Consequently, claim 14 is allowed over the prior arts.
Dependent claims 15-20 depend from allowable independent claims and inherently include limitations therein and therefore are allowed as well.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim (U.S. PN: 11,126,545) teaches a memory device 150 may include a read/write circuit 320 which is controlled by the control circuit. During a verification/normal read operation, the read/write circuit 320 may operate as a sense amplifier for reading (i.e., sensing and amplifying) data from the memory cell array. During a program operation, the read/write circuit 320 may operate as a write driver for supplying a voltage or a current to bit lines according to data to be stored in the memory cell array. During a program operation, the read/write circuit 320 may receive, from a buffer (not illustrated), data to be stored into the memory cell array, and drive bit lines according to the received data. The read/write circuit 320 may include a plurality of page buffers 322 to 326 respectively corresponding to columns (or bit lines) or column pairs (or bit line pairs). Each of the page buffers 322 to 326 may include a plurality of latches (not illustrated).
Avraham et al. (U.S. PN: 11,853,160) describes a size of the plurality of first KV pair data is different than a size of the plurality of second KV pair data. A size of the first portion of the redistributed amount of free space is equal to a size of the second portion of the redistributed amount of free space. A size of the first parity data is different than a size of the second parity data. A size of a plurality of first KV pair data stored in the first CW is equal to a size of a plurality of second KV pair data stored in the second CW. A size of first parity data encoded using the determined ECC code rate and a size of second parity data encoded using the determined ECC code rate is less than a size of the first parity data encoded using a generic ECC code rate and a size of the second parity data encoded using the generic ECC code rate (see col. 11, lines 24-50).
The examiner also requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. 37 C.F.R. § 1.75(d) (1) requires such support in the Specification for any new language added to the claims and 37 C.F.R. § 1.83(a) requires support be found in the Drawings for all claimed features.
When responding to this office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections See 37 CFR 1.111(c).
Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant, in preparing the responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Esaw T. Abraham whose telephone number is (571) 272-3812. The examiner can normally be reached on M-F 8am-4PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner'ssupervisor, Albert DeCady can be reached on (571) 272-3819. The fax phone number for the organization where this application or proceeding is assigned is (703) 872-9306.
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/ESAW T ABRAHAM/Primary Examiner,
Art Unit 2112