DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 6, 8-12, 14, 15, 18, 19, 24-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tietjen et al. – US 2009/0115650 (hereinafter Tietjen) in view of Kiesel et al. – US 2023/0239023 (hereinafter Kiesel).
Re claim 1, Tietjen discloses:
“A radio frequency (RF) device comprising:
an RF antenna” (para. 0004, 0092);
an application-specific integrated circuit (ASIC) downstream from the RF antenna and comprising
“a plurality of analog-to-digital converters (ADCs) configured to generate a plurality of replica digitized input signals” (Fig. 6A, 7A; para. 0059; wherein Tietjen provides “replica” signals because ADCs have the same input),
“a plurality of digital signal processing (DSP) cores downstream from the plurality of ADCs, each DSP core comprising a plurality of complex coefficient multipliers and associated delay circuits” (para. 0045, 0058, 0059, 0061, 0063, 0071; Fig. 6A; wherein combination of elements downstream of the ADCs and prior to the summer 310, 312 are equivalent to the “DSP cores”; the register 202 teaches the claimed “delay circuit”), and
“a respective summer downstream from each DSP core” (Fig. 6A, 7A; para. 0059, 0063, elements 310, 312); and
a processor configured to control the plurality of complex coefficient multipliers and associated delay circuits.
Tietjen differs from the claimed invention in that it does not explicitly discloses the above underlined claimed subject matter.
Kiesel, in similar filed of endeavor, discloses various modules may be implemented with ASIC, etc. (para. 0041, 0132) and suggests a control mechanism for managing operation of tee receiver in para. 0095, Fig. 7; or the receiver (i.e. access node, user terminal, etc.) as a whole in para. 0020, 0021, 0031, 0047).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the filing to have incorporated such teaching from Kiesel into Tietjen to provide, for example, ASIC implementation as such to provide dedicate circuit for specific task, thus lower the overall power consumption.
Re claim 10, see claim 1 for similar claimed subject matter; and Tietjen further implies the teaching of “a finite impulse response (FIR) as part of the CADC in para. 0045, 0058.
Re claim 18, see corresponding apparatus claim 1 above.
Re claim 2, the combination of Tietjen and Kiesel further discloses “wherein each DSP core comprises a plurality of band pass filters respectively coupled to the plurality of complex coefficient multipliers” in Tietjen, para. 0086.
Re claim 11, see claim 2 for similar claimed subject matter.
Re claim 3, the further claimed subject matter “wherein the processor is configured to generate coefficients for the plurality of complex coefficient multipliers, delay values for the associated delay circuits, and passband parameters for the plurality of band pass filters” would have been within the knowledge of one skilled in the art based on the combination of Tietjen and Kiesel above since the processor from Kiesel manages operation of the receiver (Kiesel, para. 0095, Fig. 7).
Re claim 12, see claim 3 for similar claimed subject matter.
Re claim 19, see both claim 2 and 3 for similar claimed subject matter.
Re claim 5, the combination of Tietjen and Kiesel discloses “at least of other ASIC” in Kiesel, para. 0043. Taking the above combination as a whole, one of ordinary skill in the art would have realized that the “at least of other ASIC” would have been coupled to “the processor” since the processor manages operation of the receiver (Kiesel, para. 0095).
Re claim 14, see claim 5 for similar claimed subject matter.
Re claim 6, the combination of Tietjen and Kiesel further suggests the claimed subject mater “wherein the processor is external from the ASIC” as evidence in Kiesel, Fig. 7, element 770, para. 0095.
Re claim 15, see claim 6 for similar claimed subject matter.
Re claim 8, Tietjen further discloses “wherein the plurality of DSP cores is coupled in parallel to the plurality of ADCs” in Fig. 6A, where 202, 30MI & 30MQ are arranged in parallel and are coupled to a corresponding ADC (200).
Re claim 9, the combination of Tietjen and Kiesel further suggests the claimed subject matter “wherein the ASIC defines a finite impulse response (FIR) filter circuit” in that Tietjen utilizes FIR filter for weight multiplied and sum (para. 0059, 0063, 0086, 0099); and with the combination of Kiesel as stated above, Kiesel suggests “the ASIC defines a finite impulse response (FIR) filter circuit” in para. 0041.
Re claim 24, see similar claimed subject matter in claim 10; and further in Fig. 6A, where 202, 30MI & 30MQ are arranged in parallel and are coupled to a corresponding ADC (200) for claimed subject matter “the plurality of DSP cores” “coupled in parallel to the plurality of ADCs”.
Re claim 25, see claim 2 for similar claimed subject matter.
Re claim 26, see claim 3 for similar claimed subject matter.
Allowable Subject Matter
Claims 4, 7, 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 21-23 are allowed.
Response to Arguments
Applicant's arguments filed 01/15/26 have been fully considered but they are not persuasive.
In the REMARKS, pages 12-14, applicant has argued that Tietjen does not discloses the claimed “DSP cores”. The Office respectfully disagrees. Even though Tietjen does not discloses the exact term “DSP cores”, as stated in the rejection above, the combination of elements downstream to the ADC’s and prior to the summer 310, 312 in Tietjen discloses the equivalency of the claimed “DSP core”. Particularly, each of multiplier 30MI and 30MQ and the associated delay 202 construes one “DSP core”, and there are N of such “DSP core” arranged in parallel coupled to the ADC 200 (Fig. 6A, para. 0059). Applicant also noted paragraph [0062], where it discussed a DSP. However, this DSP is for further processing in Tietjen and is not part of the teaching of the claimed “DSP cores”.
Further, on page 15-16, applicant has argued the “Examiner is using impermissible hindsight reconstruction …” The Office also respectfully disagrees. Kiesel, in similar filed of endeavor, discloses suggests a control mechanism for managing operation of the receiver in para. 0095, Fig. 7; or the receiver (i.e. access node, user terminal, etc.) as a whole in para. 0020, 0021, 0031, 0047) and various modules may be implemented with ASIC, etc. (para. 0041, 0132). At least the fact that ASIC implementation provides dedicate circuit for specific task, thus lower the overall power consumption, would have motivated one of ordinary skill in the art at the time of the filing to have looked to Kiesel’s ulization of ASIC for such benefit. Thus, it is believed that Tietjen and Kiesel are combinable and the such combination meets all claimed subject matter in the rejected claims, as stated above.
Conclusion
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/DAC V HA/ Primary Examiner, Art Unit 2633