Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status
This instant application No. 18/785385 has claims 1-20 pending. The effective filing date of this application is 03/08/2016.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3, 4, 8, 9, 13, 14, 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Ou (2012/0246394) hereinafter Ou in view of Kawamura et al (2016/0335195) hereinafter Kawamura.
Regarding claim 1, Ou discloses A memory system (Ou: Fig. 4), comprising:
a nonvolatile memory including a plurality of blocks, each of the plurality of blocks being a unit of an erase operation (Ou: Fig. 4: block 411 – block 41x; [0023]: “The flash memory 404 comprises a plurality of blocks for data storage. Each block has a corresponding erase count which is the frequency at which the corresponding block is erased”); and
a controller electrically connected to the nonvolatile memory (Ou: Fig. 4: Controller 402) and configured to:
manage a plurality of block groups, each of the plurality of block groups including at least two of the plurality of blocks (Ou: Fig. 4: First block group 410 to Third block group 430);
Ou does not explicitly disclose in response to receiving a first management command from a host, the first management command specifying a first number of block groups to be allocated to a first namespace, allocate the first number of block groups from among the plurality of block groups to the first namespace for writing data, and in response to receiving a first write command from the host, the first write command specifying at least a group identifier of one of the first number of block groups allocated to the first namespace, select, based on the group identifier, the one of the first number of block groups allocated to the first namespace, and perform a write operation on each block included in the one of the first number of block groups
However, Kawamura discloses in response to receiving a first management command from a host, the first management command specifying a first number of block groups to be allocated to a first namespace (Kawamura: [0100]: “The virtual address configuration information 1007 retains, for each virtual address group (group 1201), a subsequent write position 1202 which is a pointer retaining the subsequent write position (in the present embodiment, the unit is in sectors, but other units can also be used), and a physical block number (physical block #) 1204 of multiple physical blocks constituting a virtual address space of the corresponding group. According to the FMPKG 112 of the present embodiment, a unique identification number within the FMPKG is assigned to each physical block within the FMPKG for management, and this identification number is called a physical block number”), allocate the first number of block groups from among the plurality of block groups to the first namespace for writing data ([0097]: “When a request to write data to the logical page is received from the higher level device, the FMPKG 112 determines a non-written area address (group number and offset address within group) in the virtual address space to be associated with the relevant logical page, and stores the value in the group #1102 and the offset address 1103”); and
in response to receiving a first write command from the host, the first write command specifying at least a group identifier of one of the first number of block groups allocated to the first namespace, select, based on the group identifier, the one of the first number of block groups allocated to the first namespace, and perform a write operation on each block included in the one of the first number of block groups (Kawamura: [0108]: “When the FMPKG 112 receives a write request and write data to a logical page, the FMPKG determines an address (group number and offset address within group) of a non-written area (area in a virtual address space to which no logical page is mapped yet) using the virtual address configuration information 1007, and registers the address information of the determined area to the field of the group 1102 and the offset address 1103 in the page mapping table. Then, one or more physical pages corresponding to the address of the determined non-written area are specified, and write data is stored in the specified physical page(s)”).
Disclosures by Ou and Kawamura are analogous because they are in the same field of endeavor.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate classifying a flash memory into a plurality of block groups and allocating block groups according to the erase counts of the blocks taught by Ou to include determining a virtual block number of the data write target for write processing disclosed by Kawamura. The motivation for determining a virtual block number of the data write target for write processing by paragraph [0018] of Kawamura is for improving the storage efficiency.
Regarding claim 11, these claims limitations are significantly similar to those of claim 1, and, therefore, are rejected on the same grounds.
Regarding claim 3, Kawamura combined discloses The memory system of Claim 1, wherein the controller is further configured to: in response to receiving a second management command from the host, the second management command specifying a second number of blocks to be allocated to the first namespace (Kawamura: Fig .12: Physical Block # 1024 corresponds to Group 1201), allocate the second number of blocks from among the plurality of blocks to the first namespace for writing data ([0097]: “When a request to write data to the logical page is received from the higher level device, the FMPKG 112 determines a non-written area address (group number and offset address within group) in the virtual address space to be associated with the relevant logical page, and stores the value in the group #1102 and the offset address 1103”); and
in response to receiving a second write command from the host, the second write command specifying at least a block identifier of one of the second number of blocks allocated to the first namespace, select, based on the block identifier, the one of the second number of blocks allocated to the first namespace, and perform a write operation on the one of the second number of blocks (Kawamura: [0108]: “When the FMPKG 112 receives a write request and write data to a logical page, the FMPKG determines an address (group number and offset address within group) of a non-written area (area in a virtual address space to which no logical page is mapped yet) using the virtual address configuration information 1007, and registers the address information of the determined area to the field of the group 1102 and the offset address 1103 in the page mapping table. Then, one or more physical pages corresponding to the address of the determined non-written area are specified, and write data is stored in the specified physical page(s)”).
Disclosures by Ou and Kawamura are analogous because they are in the same field of endeavor.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate classifying a flash memory into a plurality of block groups and allocating block groups according to the erase counts of the blocks taught by Ou to include determining a virtual block number of the data write target for write processing disclosed by Kawamura. The motivation for determining a virtual block number of the data write target for write processing by paragraph [0018] of Kawamura is for improving the storage efficiency.
Regarding claim 13, these claims limitations are significantly similar to those of claim 3, and, therefore, are rejected on the same grounds.
Regarding claim 4, Kawamura combined discloses The memory system of Claim 1, wherein the at least two of the plurality of blocks included in each of the plurality of block groups are accessible in parallel with each other (Kawamura: [0116]: “write data in parallel to multiple physical blocks to enhance the access performance further. In that case, it is preferable to select multiple physical blocks to be registered in the group 1201 from different FM chips 209 in the virtual address configuration information 1007. For example, in the group construction processing (described later), the virtual address configuration information 1007 is set so that the physical blocks mapped to virtual blocks whose virtual block #1203 are address 0, address 1, address 2 and address 3 are set to physical blocks within FM chips 209a, 209b, 209e and 209f of FIG. 2, and when data for four physical blocks is collectively stored to the FM chip, it is preferable to issue a write request in parallel to FM chips 209a, 209b, 209e and 209f, according to which the performance can be improved compared to a case where the write request is issued to a single FM chip 209”).
Disclosures by Ou and Kawamura are analogous because they are in the same field of endeavor.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate classifying a flash memory into a plurality of block groups and allocating block groups according to the erase counts of the blocks taught by Ou to include writing data in parallel to multiple physical blocks disclosed by Kawamura. The motivation for writing data in parallel to multiple physical blocks by paragraph [0116] of Kawamura is for further enhancing the access performance.
Regarding claim 14, these claims limitations are significantly similar to those of claim 4, and, therefore, are rejected on the same grounds.
Regarding claim 8, Kawamura combined discloses The memory system of Claim 1, wherein the controller is further configured to copy data stored in a block included in the one of the first number of block groups to a block included in another one of the first number of block groups (Kawamura: [0127]: “Though the objects of RC and RF differ, both of them are the processes for copying valid data within a block to another block and for erasing the copy source block”).
Disclosures by Ou and Kawamura are analogous because they are in the same field of endeavor.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate classifying a flash memory into a plurality of block groups and allocating block groups according to the erase counts of the blocks taught by Ou to include copying valid data from a block to another block within a group unit disclosed by Kawamura. The motivation for copying valid data from a block to another block within a group unit by paragraph [0128] of Kawamura is for reducing the amount of copying performed as much as possible.
Regarding claim 18, these claims limitations are significantly similar to those of claim 8, and, therefore, are rejected on the same grounds.
Regarding claim 9, Kawamura combined discloses The memory system of Claim 1, wherein the controller is further configured to:
manage a plurality of namespaces including at least the first namespace (Kawamura: Fig. 12: Virtual Address Configuration Information includes first namespace of group 0 and second namespace of group 1); and
allocate, for writing data, different number of block groups from among the plurality of block groups, based on a command received from the host, to different namespaces among the plurality of namespaces (Fig. 12: Physical Block # are allocated for each group 0 and group 1).
Disclosures by Ou and Kawamura are analogous because they are in the same field of endeavor.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate classifying a flash memory into a plurality of block groups and allocating block groups according to the erase counts of the blocks taught by Ou to include determining a virtual block number of the data write target for write processing disclosed by Kawamura. The motivation for determining a virtual block number of the data write target for write processing by paragraph [0018] of Kawamura is for improving the storage efficiency.
Regarding claim 19, these claims limitations are significantly similar to those of claim 9, and, therefore, are rejected on the same grounds.
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Ou (2012/0246394) hereinafter Ou in view of Kawamura et al (2016/0335195) hereinafter Kawamura as applied to claims 1 and 11 respectively above, and further in view of Ishii (2015/0363284) hereinafter Ishii.
Regarding claim 2, Kawamura and Ou do not disclose the current limitations of claim 2.
However, Ishii discloses The memory system of Claim 1, wherein the controller is further configured to notify the host of the group identifier of the one of the first number of block groups allocated to the first namespace (Ishii: [0072]: “the host server 12a requests the management server 13 to change (update) the AM table 134_LU0 (step S31), as indicated by arrow A1 in FIG. 9. This request includes a virtual block address (leading write address) in a logical unit LU0, at which data is to be written, and the size of data blocks to be written (i.e., the number of the data blocks)”).
Disclosures by Ou, Kawamura and Ishii are analogous because they are in the same field of endeavor.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate classifying a flash memory into a plurality of block groups and allocating block groups according to the erase counts of the blocks taught by Ou/Kawamura to include notifying a virtual block address in a logical unit for write processing disclosed by Ishii. The motivation for notifying a virtual block address in a logical unit for write processing by paragraph [0007] of Ishii is for overcoming the concentration of access on the management server.
Regarding claim 12, these claims limitations are significantly similar to those of claim 2, and, therefore, are rejected on the same grounds.
Claims 5-7 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Ou (2012/0246394) hereinafter Ou in view of Kawamura et al (2016/0335195) hereinafter Kawamura as applied to claims 1 and 11 respectively above, and further in view of Syu et al (8769190) hereinafter Syu.
Regarding claim 5, Kawamura and Ou do not disclose the current limitations of claim 5.
However, Syu discloses The memory system of Claim 1, wherein the controller is further configured to perform the erase operation collectively on the at least two of the plurality of blocks included in each of the plurality of block groups (Syu: Fig. 3A; column 3, lines 49-54: “each of the first set of superblocks 350 encompasses the bottom eight dies while each of the second set of superblocks 351 encompasses the top eight dies. The superblock 340 is shown as a group of shaded blocks within the dies in the superblock set 350 while the superblock 341 is shown as a group of shaded blocks within the dies in the superblock set 351. When the memory management subsystem issues an erase command (e.g., for a garbage collection operation) for dies in the superblock set 350”).
Disclosures by Ou, Kawamura and Syu are analogous because they are in the same field of endeavor.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate classifying a flash memory into a plurality of block groups and allocating block groups according to the erase counts of the blocks taught by Ou/Kawamura to include an erase operation performed on a group of blocks distributed across all dies of memory disclosed by Syu. The motivation for an erase operation performed on a group of blocks distributed across all dies of memory by column 2, lines 27-33 of Syu is for freeing memory for future write commands.
Regarding claim 15, these claims limitations are significantly similar to those of claim 5, and, therefore, are rejected on the same grounds.
Regarding claim 6, Ou combined further disclose The memory system of Claim 5, wherein the controller is further configured to: in response to receiving a first count command from the host, the first count command requesting acquisition of a total number of erase operations performed on each of the first number of block groups allocated to the first namespace, notify the host of the total number of erase operations performed on each of the first number of block groups allocated to the first namespace (Ou: [0029]: “The controller 402 then divides logical addresses used by the host 450 into a plurality of logical address sections respectively corresponding to the block groups 410, 420, and 430 (step 604). In one embodiment, the logical address section with high data importance corresponds to the block group with a low erase count, and the logical address section with low data importance corresponds to the block group with a high erase count. The controller 402 then receives write data from a host 450 (step 606). The controller 402 then determines a target block group corresponding to the logical address section corresponding to the write data from the block groups 410, 420, and 430 (step 608). The controller 402 then selects a target block from the target block group (step 610), and then writes the write data to the target block”).
Regarding claim 16, these claims limitations are significantly similar to those of claim 6, and, therefore, are rejected on the same grounds.
Regarding claim 7, Ou combined further disclose The memory system of Claim 5, wherein the controller is further configured to: manage an erase count of each of the plurality of block groups; and in response to receiving the first management command, select, from the plurality of block groups, a block group having a minimum erase count to be included in the first number of block groups (Ou: [0024]: “The controller 402 then selects a target block from the target block group, and then writes the write data to the target block. In one embodiment, the blocks of the flash memory 404 are divided into a first block group with high erase counts and second block group with a low erase counts. When the controller 402 determines the write data to be system data with high importance, because system data has a low tolerance for data errors, the controller 402 selects the second block group with a low erase count as the target block group for storing the write data”).
Regarding claim 17, these claims limitations are significantly similar to those of claim 7, and, therefore, are rejected on the same grounds.
Claims 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ou (2012/0246394) hereinafter Ou in view of Kawamura et al (2016/0335195) hereinafter Kawamura as applied to claims 1 and 11 respectively above, and further in view of Patil et al (2013/0254508) hereinafter Patil.
Regarding claim 10, Kawamura and Ou do not disclose the current limitations of claim 10.
However, Patil discloses The memory system of Claim 1, wherein the controller is further configured to, in response to receiving a third management command from the host, de- allocate one or more of the first number of block groups from the first namespace (Patil: [0066]: “If file system 114 determines that the deleted block's write count is within the write count thresholds of the write group in which the deleted block currently resides, then, in step 708, file system 114 removes the deleted block from the allocated block list of the current write group and adds it to the free block list of the same write group”).
Disclosures by Ou, Kawamura and Patil are analogous because they are in the same field of endeavor.
It would have been obvious to an ordinary person skilled in the art before the earliest effective filing date of the claimed invention to incorporate classifying a flash memory into a plurality of block groups and allocating block groups according to the erase counts of the blocks taught by Ou/Kawamura to include removing blocks from allocated block list of the write group disclosed by Patil. The motivation for removing blocks from allocated block list of the write group by paragraph [0066] of Patil is for adding the removed block to the free block list.
Regarding claim 20, these claims limitations are significantly similar to those of claim 10, and, therefore, are rejected on the same grounds.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAN V DOAN whose telephone number is (571)270-7250. The examiner can normally be reached Monday, Wednesday and Thursday from 10:45 AM to 4:45PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kenneth Lo can be reached at 571-272-9774. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAN V DOAN/Examiner, Art Unit 2136
/KENNETH M LO/Supervisory Patent Examiner, Art Unit 2136