DETAILED ACTION
1. This Office Action is taken in response to Applicants’ Amendments and Remarks filed on 3/3/2026 regarding application 18/785,444 filed on 7/26/2024.
Claims 1-20 are pending for consideration.
2. Response to Amendments and Remarks
Applicants’ amendments and remarks have been fully and carefully considered, with the Examiner’s response set forth below.
(1) In response to the amendments and remarks, an updated claim analysis has been made with newly identified reference(s). Refer to the corresponding sections of the following Office Action for details.
3. Examiner’s Note
(1) In the case of amending the Claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. This will assist in expediting compact prosecution. MPEP 714.02 recites: “Applicant should also specifically point out the support for any amendments made to the disclosure. See MPEP § 2163.06. An amendment which does not comply with the provisions of 37 CFR 1.121(b), (c), (d), and (h) may be held not fully responsive. See MPEP § 714.” Amendments not pointing to specific support in the disclosure may be deemed as not complying with provisions of 37 C.F.R. 1.131(b), (c), (d), and (h) and therefore held not fully responsive. Generic statements such as “Applicants believe no new matter has been introduced” may be deemed insufficient.
(2) Examiner has cited particular columns/paragraph and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Miyamoto et al. (US Patent Application Publication 2016/0170642, hereinafter Miyamoto), in view of Rajagopal et al. (US Patent Application Publication 2022/0413876, hereinafter Rajagopal), and further in view of Nagai (US Patent Application Publication 2019/0265897).
As to claim 1, Miyamoto teaches An operating method for a solid state device (SSD), wherein the SSD comprises an SSD controller and a memory device [as shown in figures 1-3; Hereinafter, memory systems according to embodiments will be described in detail with reference to the accompanying drawings. The invention is not limited by the embodiments. In each of the following embodiments, a case in which a memory system is a solid state drive (SSD) will be described. The memory system may be a drive, such as a hard disk drive (HDD), other than the SSD (¶ 0017); Nagai also teaches this limitation -- SSD as shown in figure 1, 3], the operating method comprising:
receiving a first operation request from a host [host, figure 1, 60A; A memory system according to an embodiment includes a non-volatile memory and a controller configured to control the non-volatile memory. The controller includes an interface and a control unit. The interface receives, from a host, a first instruction to change a performance of the memory system as a performance control instruction. The control unit controls the memory system on the basis of the performance control instruction such that the number of parallel operations of parallel operating units which are operated in parallel in the memory system is changed (abstract); Nagai also teaches this limitation -- host, figure 6, 2];
performing a first memory operation in response to the first operation request [A memory system according to an embodiment includes a non-volatile memory and a controller configured to control the non-volatile memory. The controller includes an interface and a control unit. The interface receives, from a host, a first instruction to change a performance of the memory system as a performance control instruction. The control unit controls the memory system on the basis of the performance control instruction such that the number of parallel operations of parallel operating units which are operated in parallel in the memory system is changed (abstract); Nagai also teaches this limitation -- The host 2 is an information processing apparatus (referred to also as a computing device) such as a personal computer or a server computer and is configured to make a data write request, data read request, etc., to a solid state drive (SSD) 3 which is a storage device connected to the host 2 (¶ 0029)];
receiving, from the host, information on maximum consumption power based on a command defined in an NVMe interface, wherein the maximum consumption power is to be consumed by the SSD [The power consumption setting interface 25e receives power consumption information from the host 60A and transmits the power consumption information to the CPU 51. The power consumption information is information about the maximum power consumption of the memory system 10A allowed by the host 60A … (¶ 0056-0057); Nagai also teaches maximum power consumption information -- The host interface 11 receives various commands (for example, a write command, a read command, commands (inquiry commands) which request to report the state or various settings of the SSD 3, etc.) from the host 2 (¶ 0086); FIG. 7 shows a case where the SSD 3 supports four power states which require different amounts of power consumption … The maximum power consumption of the power state 0 is 14 W, for example. The maximum power consumption of the power state 1 is 11 W, for example. The maximum power consumption of the power state 2 is 8 W, for example. The maximum power consumption of a power state 3 is 5 W, for example (¶ 0104-0105);
Rajagopal teaches NVMe interface command – In some embodiments, computing system 100 comprises Nonvolatile Memory Express (NVMe) controller 116, Serial Peripheral Interface (SPI) interface 118, Embedded Multimedia Card (eMMC) interface 120, and Universal Flash Storage (UFS) interface 122. In some embodiments, computing system 100 includes an internal bus 126. The internal bus 126 may couple controller 110 with the NVMe controller 116, SPI interface 118, eMMC interface 120, and UFS interface 122 (¶ 0015); … The actions depicted in FIG. 2 involve user interface 114, BIOS 104, controller 110, OS 106, endpoint device 112, and PMC 154. At 214, BIOS 104 receives a password for endpoint device 112 from a user via user interface 114. At 216, BIOS 104 sends the password to endpoint device 112, e.g., an NVMe controller, to unlock endpoint device 112 … (¶ 0032)];
storing the information on maximum consumption power in an internal memory of the SSD controller [power consumption table, figure 2, 45E; The power consumption setting interface 25e receives power consumption information from the host 60A and transmits the power consumption information to the CPU 51. The power consumption information is information about the maximum power consumption of the memory system 10A allowed by the host 60A. As the power consumption, for example, 9 W (watt) or 10 W is designated. In the power consumption table 45E, the power consumption information and the resource limit information of the resource of which parallel operation is limited are associated with each other … (¶ 0056-0057); Nagai also teaches this information -- FIG. 7 shows a case where the SSD 3 supports four power states which require different amounts of power consumption … The maximum power consumption of the power state 0 is 14 W, for example. The maximum power consumption of the power state 1 is 11 W, for example. The maximum power consumption of the power state 2 is 8 W, for example. The maximum power consumption of a power state 3 is 5 W, for example (¶ 0104-0105)];
calculating a respective plurality of maximum component power values for a plurality of components in the SSD based on the information on maximum consumption power [Miyamoto teaches calculating predicted component power values for a SSD, which includes a plurality of NAND chips and CPUs (see figures 3-5) – as shown in figure 11, steps S10-S50; Next, a third embodiment will be described with reference to FIGS. 9 to 11. In a storage server system according to the third embodiment, a memory system calculates its power consumption (predicted power consumption which will be described below) on the basis of the required performance (for example, bandwidth or throughput) from the host … When receiving predicted power consumption (watt) corresponding to the required performance from the memory system 10C, the host 60C transmits a performance control instruction (maximum allowable power consumption) corresponding to the received predicted power consumption to the memory system 10C (¶ 0119-0122);
Rajagopal teaches measuring/calculating power consumption of one or more components of the device -- In some embodiments, device 5500 comprises power measurement circuitries 5542, e.g., for measuring power consumed by one or more components of the device 5500 … For example, power measurement circuitries 5542 may measure power, current and/or voltage supplied by one or more voltage regulators 5514, power supplied to SoC 5501, power supplied to device 5500, power consumed by processor 5504 (or any other component) of device 5500, etc (¶ 0072);
Nagai teaches determining maximum power consumption for a plurality of NAND chips in an SSD -- SSD as shown in figure 1, 3; The SSD 3 includes the controller 4 and a nonvolatile semiconductor memory (NAND flash memory) 5. The NAND flash memory 5 may include a plurality of NAND flash memory chips. The controller 4 operates as a memory controller which is electrically connected to the NAND flash memory 5, controls the NAND flash memory 5, and performs a data write operation and a data read operation on the NAND flash memory 5. The controller 4 may be realized as a circuit such as a system-on-a-chip (SoC) (¶ 0081); FIG. 7 shows a case where the SSD 3 supports four power states which require different amounts of power consumption. These power states are identified by different numbers (power state numbers) assigned to these power states. The maximum power consumption corresponding to the each power state indicates a maximum power that may be consumed in this state … For example, the speed of a read operation and a write operation on the NAND flash memory 5 increases as the power consumption of the power state increases … The maximum power consumption of the power state 0 is 14 W, for example. The maximum power consumption of the power state 1 is 11 W, for example. The maximum power consumption of the power state 2 is 8 W, for example. The maximum power consumption of a power state 3 is 5 W, for example (¶ 0104-0105); The SSD 3 only supports the power state 0. Therefore, the SSD 3 always uses the power state 0 and performs a data write operation and a data read operation on the NAND flash memory 5 using the power state 0. The maximum power consumption of the power state 0 is 14 W, for example (¶ 0162)], wherein calculating the respective plurality of maximum component power values includes calculating a maximum component power value for a NAND flash memory chip in the SSD [this limitation is taught by Nagai – SSD as shown in figure 1, 3; The SSD 3 includes the controller 4 and a nonvolatile semiconductor memory (NAND flash memory) 5. The NAND flash memory 5 may include a plurality of NAND flash memory chips. The controller 4 operates as a memory controller which is electrically connected to the NAND flash memory 5, controls the NAND flash memory 5, and performs a data write operation and a data read operation on the NAND flash memory 5. The controller 4 may be realized as a circuit such as a system-on-a-chip (SoC) (¶ 0081); FIG. 7 shows a case where the SSD 3 supports four power states which require different amounts of power consumption. These power states are identified by different numbers (power state numbers) assigned to these power states. The maximum power consumption corresponding to the each power state indicates a maximum power that may be consumed in this state … For example, the speed of a read operation and a write operation on the NAND flash memory 5 increases as the power consumption of the power state increases … The maximum power consumption of the power state 0 is 14 W, for example. The maximum power consumption of the power state 1 is 11 W, for example. The maximum power consumption of the power state 2 is 8 W, for example. The maximum power consumption of a power state 3 is 5 W, for example (¶ 0104-0105); The SSD 3 only supports the power state 0. Therefore, the SSD 3 always uses the power state 0 and performs a data write operation and a data read operation on the NAND flash memory 5 using the power state 0. The maximum power consumption of the power state 0 is 14 W, for example (¶ 0162)];
based on the plurality of maximum component power values, setting a maximum power value to be consumed by at least one component in the SSD [The power consumption setting interface 27 transmits the required performance transmitted from the host 60C to the power consumption calculation unit 31. In addition, the power consumption setting interface 27 transmits a performance control instruction for the maximum allowable power consumption transmitted from the host 60C to the CPU 51 … (¶ 0131-0141)];
receiving a second operation request from the host [The memory system according to claim 1, wherein the performance control instruction is a maximum value of the performance of the memory system requested by the host (claim 7); The memory system according to claim 1, wherein the performance control instruction is the minimum endurance of the memory system requested by the host (claim 8); The memory system according to claim 1, wherein the performance control instruction is the maximum power consumption of the memory system requested by the host (claim 9); The memory system according to claim 1, wherein the performance control instruction is the upper limit of the temperature of the memory system requested by the host (claim 10)]; and
performing a second memory operation in response to the second operation request [A memory system according to an embodiment includes a non-volatile memory and a controller configured to control the non-volatile memory. The controller includes an interface and a control unit. The interface receives, from a host, a first instruction to change a performance of the memory system as a performance control instruction. The control unit controls the memory system on the basis of the performance control instruction such that the number of parallel operations of parallel operating units which are operated in parallel in the memory system is changed (abstract)];
wherein the first memory operation is operated within a default power [The preset value setting interface 25b receives the preset value transmitted from the host 60A and transmits the preset value to the CPU 51. The preset value indicates a combination of the use resource (available resource ID) and the number of parallel operations under typical conditions … (¶ 0041-0042); … The power consumption table 47 may be preset, for example, upon shipment of the memory system 10C or it may be changed by an instruction from the host 60C (¶ 0130)], and the second memory operation is operated within the maximum consumption power [The power consumption setting interface 27 transmits the required performance transmitted from the host 60C to the power consumption calculation unit 31. In addition, the power consumption setting interface 27 transmits a performance control instruction for the maximum allowable power consumption transmitted from the host 60C to the CPU 51 … (¶ 0131-0141); The memory system according to claim 1, wherein the performance control instruction is the maximum power consumption of the memory system requested by the host (claim 9)], wherein the SSD controller comprises a volatile memory [as shown in figure 6, where the controller (12B) comprises a volatile memory (52); The memory 52 is, for example, a volatile memory … (¶ 0034)], and the memory device comprises a plurality of NAND flash memory chips [as shown in figure 3; The memory system 10A includes a NAND memory 11 and a controller 12A. The NAND memory 11 is a storage medium that can store information in a non-volatile manner. The NAND memory 11 is a NAND flash memory which is an example of a recordable non-volatile memory (¶ 0019)], and the plurality of components the SSD comprise the SSD controller, the volatile memory, and the NAND flash memory chips [as shown in figures 1 and 3], and wherein setting the maximum power value includes controlling a frequency of a clock signal provided to at least one of the SSD controller, the volatile memory, and the NAND flash memory chips [this limitation is taught by Rajagopal -- The clock generator 5516 can comprise a phase locked loop (PLL), frequency locked loop (FLL), or any suitable clock source. In some embodiments, each core of processor 5504 has its own clock source. As such, each core can operate at a frequency independent of the frequency of operation of the other core. In some embodiments, PCU 5510 and/or PMIC 5512 performs adaptive or dynamic frequency scaling or adjustment. For example, clock frequency of a processor core can be increased if the core is not operating at its maximum power consumption threshold or limit … (¶ 0093)].
Regarding claim 1, Miyamoto does not expressively teach NVMe interface, and setting of the maximum power value includes controlling a frequency of a clock signal provided to at least one component.
However, both NVMe interface and setting of the maximum power value includes controlling a frequency of a clock signal provided to at least one component are well known and commonly used in the art.
For example, Rajagopal specifically teaches both NVMe interface and setting of the maximum power value includes controlling a frequency of a clock signal provided to at least one component [In some embodiments, computing system 100 comprises Nonvolatile Memory Express (NVMe) controller 116, Serial Peripheral Interface (SPI) interface 118, Embedded Multimedia Card (eMMC) interface 120, and Universal Flash Storage (UFS) interface 122. In some embodiments, computing system 100 includes an internal bus 126. The internal bus 126 may couple controller 110 with the NVMe controller 116, SPI interface 118, eMMC interface 120, and UFS interface 122 (¶ 0015); … The actions depicted in FIG. 2 involve user interface 114, BIOS 104, controller 110, OS 106, endpoint device 112, and PMC 154. At 214, BIOS 104 receives a password for endpoint device 112 from a user via user interface 114. At 216, BIOS 104 sends the password to endpoint device 112, e.g., an NVMe controller, to unlock endpoint device 112 … (¶ 0032); The clock generator 5516 can comprise a phase locked loop (PLL), frequency locked loop (FLL), or any suitable clock source. In some embodiments, each core of processor 5504 has its own clock source. As such, each core can operate at a frequency independent of the frequency of operation of the other core. In some embodiments, PCU 5510 and/or PMIC 5512 performs adaptive or dynamic frequency scaling or adjustment. For example, clock frequency of a processor core can be increased if the core is not operating at its maximum power consumption threshold or limit … (¶ 0093)]
Therefore, it would have been obvious for one of ordinary skills in the art before the effective filing date of claimed invention to adopt both NVMe interface and setting of the maximum power value includes controlling a frequency of a clock signal provided to at least one component, as specifically demonstrated by Rajagopal, and to incorporate it into the existing scheme disclosed by Miyamoto, in order to also support NVMe interface, and to dynamically adjust the maximum allowable power consumption by varing clock frequency, which is straightforward and relatively to achieve.
Further regarding claim 1, Miyamoto in view of Rajagopal teaches calculating/measuring power consumption of a plurality of components of a memory device including NAND chips and CPUs [Miyamoto teaches calculating predicted component power values for a SSD, which includes a plurality of NAND chips and CPUs (see figures 3-5) – as shown in figure 11, steps S10-S50; Next, a third embodiment will be described with reference to FIGS. 9 to 11. In a storage server system according to the third embodiment, a memory system calculates its power consumption (predicted power consumption which will be described below) on the basis of the required performance (for example, bandwidth or throughput) from the host … When receiving predicted power consumption (watt) corresponding to the required performance from the memory system 10C, the host 60C transmits a performance control instruction (maximum allowable power consumption) corresponding to the received predicted power consumption to the memory system 10C (¶ 0119-0122);
Rajagopal teaches measuring/calculating power consumption of one or more components of the device -- In some embodiments, device 5500 comprises power measurement circuitries 5542, e.g., for measuring power consumed by one or more components of the device 5500 … For example, power measurement circuitries 5542 may measure power, current and/or voltage supplied by one or more voltage regulators 5514, power supplied to SoC 5501, power supplied to device 5500, power consumed by processor 5504 (or any other component) of device 5500, etc (¶ 0072)], does not expressively teach calculating a maximum component power value for a NAND flash memory chip in the SSD.
However, Nagai specifically teaches calculating a maximum component power value for a NAND flash memory chip in the SSD [SSD as shown in figure 1, 3; The SSD 3 includes the controller 4 and a nonvolatile semiconductor memory (NAND flash memory) 5. The NAND flash memory 5 may include a plurality of NAND flash memory chips. The controller 4 operates as a memory controller which is electrically connected to the NAND flash memory 5, controls the NAND flash memory 5, and performs a data write operation and a data read operation on the NAND flash memory 5. The controller 4 may be realized as a circuit such as a system-on-a-chip (SoC) (¶ 0081); FIG. 7 shows a case where the SSD 3 supports four power states which require different amounts of power consumption. These power states are identified by different numbers (power state numbers) assigned to these power states. The maximum power consumption corresponding to the each power state indicates a maximum power that may be consumed in this state … For example, the speed of a read operation and a write operation on the NAND flash memory 5 increases as the power consumption of the power state increases … The maximum power consumption of the power state 0 is 14 W, for example. The maximum power consumption of the power state 1 is 11 W, for example. The maximum power consumption of the power state 2 is 8 W, for example. The maximum power consumption of a power state 3 is 5 W, for example (¶ 0104-0105); The SSD 3 only supports the power state 0. Therefore, the SSD 3 always uses the power state 0 and performs a data write operation and a data read operation on the NAND flash memory 5 using the power state 0. The maximum power consumption of the power state 0 is 14 W, for example (¶ 0162)].
Therefore, it would have been obvious for one of ordinary skills in the art before the effective filing date of claimed invention to calculate a maximum component power value for a NAND flash memory chip in the SSD, as specifically demonstrated by Nagai, and to incorporate it into the existing scheme disclosed by Miyamoto in view of Rajagopal, in order to know the specific power consumed by a NAND chip.
As to claim 2, Miyamoto in view of Rajagopal & Nagai teaches The operating method of claim 1, wherein the SSD controller further comprises a CPU core [Miyamoto – CPU, figure 1, 51], and wherein setting the maximum power value includes controlling the maximum power value consumed by at least one of the CPU core [Miyamoto – as shown in figure 5, where table 45B includes multiple preset configurations with various number of CPUs; In the memory system 10A, for example, power consumption varies depending on workload (for example, the amount of information processed) or an environment (for example, temperature). In this embodiment, the host 60A designates the maximum allowable power consumption of the memory system 10A. The power consumption information may be the amount of power consumption. When receiving the resource limit information, the CPU 51 registers the resource limit information in the resource usage information 45X. In addition, when receiving the preset value, the CPU 51 selects the resource limit information corresponding to the preset value from the preset value table 45B and registers the selected resource limit information in the resource usage information 45X (¶ 0057-0058)], a clock generator generating the clock signal [Rajagopal – clock generator, figure 4, 5516] or the NAND flash memory chips [Miyamoto – as shown in figure 3].
As to claim 3, Miyamoto in view of Rajagopal & Nagai teaches The operating method of claim 2, wherein setting the maximum power value includes calculating information on a maximum power value for the CPU core and the NAND flash memory chips [Miyamoto – as shown in figure 5, where table 45B includes multiple preset configurations with various number of CPUs; In the memory system 10A, for example, power consumption varies depending on workload (for example, the amount of information processed) or an environment (for example, temperature). In this embodiment, the host 60A designates the maximum allowable power consumption of the memory system 10A. The power consumption information may be the amount of power consumption. When receiving the resource limit information, the CPU 51 registers the resource limit information in the resource usage information 45X. In addition, when receiving the preset value, the CPU 51 selects the resource limit information corresponding to the preset value from the preset value table 45B and registers the selected resource limit information in the resource usage information 45X (¶ 0057-0058)].
As to claim 4, Miyamoto in view of Rajagopal & Nagai teaches The operating method of claim 1, wherein the SSD further comprises a power management integrated circuit (PMIC) to control power consumed by the SSD [Rajagopal – PMIC, figure 4, 5512].
As to claim 5, Miyamoto in view of Rajagopal & Nagai teaches The operating method of claim 4, wherein the PMIC controls a provision of the power to each of the at least one component [Rajagopal – PMIC, figure 4, 5512; In some embodiments, device 5500 comprises Power Management Integrated Circuit (PMIC) 5512, e.g., to implement various power management operations for device 5500. In some embodiments, PMIC 5512 is a Reconfigurable Power Management ICs (RPMICs) and/or an IMVP (Intel® Mobile Voltage Positioning). In an example, the PMIC is within an IC die separate from processor 5504. The may implement various power management operations for device 5500. PMIC 5512 may include hardware interfaces, hardware circuitries, connectors, registers, etc., as well as software components (e.g., drivers, protocol stacks), to implement various power management operations for device 5500 … (¶ 0090-0095)].
As to claim 6, Miyamoto in view of Rajagopal & Nagai teaches The operating method of claim 4, wherein the SSD further comprises a power checker to monitor a level of the power provided by the PMIC to the at least one component [Rajagopal – … In some embodiments, PCU 5510 and/or PMIC 5512 determines the operating condition of each core of a processor, and opportunistically adjusts frequency and/or power supply voltage of that core without the core clocking source (e.g., PLL of that core) losing lock when PCU 5510 and/or PMIC 5512 determines that the core is operating below a target performance level. For example, if a core is drawing current from a power supply rail less than a total current allocated for that core or processor 5504, then PCU 5510 and/or PMIC 5512 can temporality increase the power draw for that core or processor 5504 (e.g., by increasing clock frequency and/or power supply voltage level) so that the core or processor 5504 can perform at higher performance level. As such, voltage and/or frequency can be increased temporality for processor 5504 without violating product reliability (¶ 0093)].
As to claim 7, Miyamoto in view of Rajagopal & Nagai teaches The operating method of claim 1, further comprising: transmitting the information on maximum consumption power to the host in response to a request from the host [Miyamoto – as shown in figure 11, step S30; Then, the power consumption calculation unit 31 of the controller 12C calculates predicted power consumption corresponding to the required performance (Step S20). Then, the controller 12C notifies the calculated predicted power consumption to the host 60C through the power consumption setting interface 27 (Step S30) (¶ 0135)].
As to claim 8, Miyamoto in view of Rajagopal & Nagai teaches The operating method of claim 1, wherein the SSD receives power table information including the information on maximum consumption power, and wherein the power table information includes one or more pieces of battery step information and information on maximum consumption power corresponding to each pieces of battery step information [Miyamoto – as shown in figure 5, where table 45B includes multiple preset configurations with various number of CPUs; In the memory system 10A, for example, power consumption varies depending on workload (for example, the amount of information processed) or an environment (for example, temperature). In this embodiment, the host 60A designates the maximum allowable power consumption of the memory system 10A. The power consumption information may be the amount of power consumption. When receiving the resource limit information, the CPU 51 registers the resource limit information in the resource usage information 45X. In addition, when receiving the preset value, the CPU 51 selects the resource limit information corresponding to the preset value from the preset value table 45B and registers the selected resource limit information in the resource usage information 45X (¶ 0057-0058); Rajagopal -- … In an example, PCU 5510 and/or PMIC 5512 may control battery power usage, charging of battery 5518, and features related to power saving operation. The clock generator 5516 can comprise a phase locked loop (PLL), frequency locked loop (FLL), or any suitable clock source. In some embodiments, each core of processor 5504 has its own clock source. As such, each core can operate at a frequency independent of the frequency of operation of the other core. In some embodiments, PCU 5510 and/or PMIC 5512 performs adaptive or dynamic frequency scaling or adjustment. For example, clock frequency of a processor core can be increased if the core is not operating at its maximum power consumption threshold or limit sage, charging of battery 5518, and features related to power saving operation … (¶ 0092-0093)].
As to claim 9, Miyamoto in view of Rajagopal & Nagai teaches The operating method of claim 1, wherein the SSD sets the maximum power value such that power consumed by the at least one component does not exceed the maximum consumption power [Miyamoto – In the power consumption table 47, the maximum allowable power consumption required for the memory system 10C is associated with the resource limit information of the resources of which parallel operation is limited. Therefore, the memory system 10C controls the parallel operation of the resources corresponding to the resource limit information stored in the power consumption table 47 and operates with the maximum allowable power consumption corresponding to the resource limit information (¶ 0133)].
As to claim 10, Miyamoto in view of Rajagopal & Nagai teaches The operating method of claim 1, wherein setting the maximum power value includes generating table information comprising information on the maximum power value consumed by the at least one component [Miyamoto – as shown in figure 5, where table 45B includes multiple preset configurations with various number of CPUs; In the memory system 10A, for example, power consumption varies depending on workload (for example, the amount of information processed) or an environment (for example, temperature). In this embodiment, the host 60A designates the maximum allowable power consumption of the memory system 10A. The power consumption information may be the amount of power consumption. When receiving the resource limit information, the CPU 51 registers the resource limit information in the resource usage information 45X. In addition, when receiving the preset value, the CPU 51 selects the resource limit information corresponding to the preset value from the preset value table 45B and registers the selected resource limit information in the resource usage information 45X (¶ 0057-0058)].
As to claim 11, Miyamoto in view of Rajagopal & Nagai teaches The operating method of claim 10, further comprising: storing the table information in the internal memory of the SSD controller [Miyamoto – as shown in figure 2, 42A, which contains a plurality of tables, 45X-45E].
As to claim 12, Miyamoto in view of Rajagopal & Nagai teaches The operating method of claim 1, further comprising: detecting power consumed by the SSD; and reducing power consumed by the SSD when the detected power exceeds the maximum consumption power [Miyamoto – In the power consumption table 47, the maximum allowable power consumption required for the memory system 10C is associated with the resource limit information of the resources of which parallel operation is limited. Therefore, the memory system 10C controls the parallel operation of the resources corresponding to the resource limit information stored in the power consumption table 47 and operates with the maximum allowable power consumption corresponding to the resource limit information (¶ 0133)].
As to claim 13, Miyamoto in view of Rajagopal & Nagai teaches The operating method of claim 12, further comprising: determining that an operation pattern of the SSD corresponds to a random write pattern or a sequential write pattern; and differently adjusting power consumed by the at least one component, based on the operation pattern of the SSD [Miyamoto – In this embodiment, the performances of the resources are, for example, a data read/write speed, the amount of data which is read or written, and an access patterns such as sequential and random. Specifically, the performances of the resources are, for example, the number of parallel operations, data storage capacity, an information processing speed, and the amount of information processed. In addition, examples of the information processing include arithmetic processing, a data writing process, a data reading process, and a communication process (¶ 0027)].
As to claim 14, it recites substantially the same limitations as in claim 1, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
As to claim 15, it recites substantially the same limitations as in claim 11, and is rejected for the same reasons set forth in the analysis of claim 11. Refer to “As to claim 11” presented earlier in this Office Action for details.
As to claim 16, it recites substantially the same limitations as in claim 11, and is rejected for the same reasons set forth in the analysis of claim 11. Refer to “As to claim 11” presented earlier in this Office Action for details.
As to claim 17, it recites substantially the same limitations as in claim 1, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
It is noted that the low performance mode recited in claim 17 corresponds to the default power level recited in claim 1, and the high performance mode recited in claim 17 corresponds to the maximum power level recited in claim 1.
As to claim 18, Miyamoto in view of Rajagopal & Nagai teaches The operating method of claim 17, wherein the low performance mode or the high performance mode is selected based on a type of an application executed by the host [Miyamoto -- The memory system according to claim 1, wherein the performance control instruction is a maximum value of the performance of the memory system requested by the host (claim 7); The memory system according to claim 1, wherein the performance control instruction is the minimum endurance of the memory system requested by the host (claim 8); The memory system according to claim 1, wherein the performance control instruction is the maximum power consumption of the memory system requested by the host (claim 9); The memory system according to claim 1, wherein the performance control instruction is the upper limit of the temperature of the memory system requested by the host (claim 10)].
As to claim 19, it recites substantially the same limitations as in claim 1, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
As to claim 20, it recites substantially the same limitations as in claim 1, and is rejected for the same reasons set forth in the analysis of claim 1. Refer to “As to claim 1” presented earlier in this Office Action for details.
Conclusion
5. Claims 1-20 are rejected as explained above.
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG JEN TSAI whose telephone number is 571-272-4244. The examiner can normally be reached on Monday-Friday, 9-6.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached on 571-272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG JEN TSAI/Primary Examiner, Art Unit 2136