Prosecution Insights
Last updated: October 25, 2026
Application No. 18/785,462

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

Non-Final OA §103
Filed
Jul 26, 2024
Priority
Dec 07, 2021 — continuation of 12/057,378
Examiner
SOWARD, IDA M
Art Unit
Tech Center
Assignee
Amkor Technology Singapore Holding Pte. Ltd.
OA Round
1 (Non-Final)
93%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allowance Rate
1285 granted / 1376 resolved
+33.4% vs TC avg
Moderate +5% lift
Without
With
+5.4%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
36 currently pending
Career history
1414
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
37.6%
-2.4% vs TC avg
§102
36.6%
-3.4% vs TC avg
§112
24.9%
-15.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1376 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action is in response to the election filed September 7, 2026. Election/Restrictions Applicant’s election without traverse of claims 21-36 in the reply filed on September 7, 2026 is acknowledged. Drawings The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 1115b. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: PACKAGED ELECTRONIC DEVICE INCLUDING LEAD INWARD AND OUTWARD SIDES. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 21-23 and 26-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kyung et al. (KR 101647587 B1) in view of Choi et al. (WO 2007005263 A2). In regard to claim 21, Kyung et al. teach a packaged electronic device 100, comprising: a molded substrate 110/131 comprising: a conductive structure 110/131 comprising: a first lead 111 comprising a first lead outward side and a first lead inward side opposite to the first lead outward side; and a second lead 112 comprising a second lead outward side and a second lead inward side opposite to the second lead outward side; and a first encapsulant 131 covering a lower portion of the first lead inward side and a lower portion of the second lead inward side; an electronic component 120 coupled to the first lead 111 and the second lead 112; and a second encapsulant 132 (Figures 1a-2b and 3b, pages 4-11). However, Kyung et al. fail to teach an upper portion of the first lead outward side and an upper portion of the second lead outward side exposed from the first encapsulant; and a second encapsulant covering an upper portion of the first lead inward side, the upper portion of the second lead outward side, and an upper portion of the second lead inward side, wherein the second encapsulant comprises a second encapsulant top side and second encapsulant sides. In regard to claim 21, Choi et al. teach an upper portion of the first lead outward side (of 702(a)) and an upper portion of the second lead outward side (of 702(b)) exposed from the first encapsulant 721; and a second encapsulant 703 covering an upper portion of the first lead inward side (of 702(a)), the upper portion of the second lead outward side (of 702(b)), and an upper portion of the second lead inward side, (of 702(b)) wherein the second encapsulant 703 comprises a second encapsulant top side and second encapsulant sides (Figure 2B, pages 13-21, paragraphs [0112]-[0147]). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the packaged electronic device structure as taught by Kyung et al. with the packaged electronic device structure having an upper portion of the first lead outward side and an upper portion of the second lead outward side exposed from the first encapsulant; and a second encapsulant covering an upper portion of the first lead inward side, the upper portion of the second lead outward side, and an upper portion of the second lead inward side, wherein the second encapsulant comprises a second encapsulant top side and second encapsulant sides as taught by Choi et al. to improve functionality of semiconductor die packages (paragraph [0004]). In regard to claim 22, Kyung et al. teach the first encapsulant 131 covering a lower portion of the second lead outward side (at 112) (Figures 1a-2b and 3b, pages 4-11). In regard to claim 23, Choi et al. teach the first encapsulant 721 covering a lower portion of the first lead outward side (of 702(a)) (Figure 2B, pages 13-21, paragraphs [0112]-[0147]). In regard to claim 26, Kyung et al. teach a lower portion of the first lead outward side (of 111) is inset with respect to the upper portion of the first lead outward side (of 111) (Figures 1a-2b and 3b, pages 4-11). In regard to claim 27, Kyung et al. teach the lower portion of the first lead outward side (of 111) covered by the first encapsulant 131 (Figures 1a-2b and 3b, pages 4-11). Allowable Subject Matter Claims 24-25 and 28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 29-36 are allowed. The following is a statement of reasons for the indication of allowable subject matter: In regard to claim 29, The prior art of record (Kyung et al. (KR 101647587 B1) in view of Choi et al. (WO 2007005263 A2)) does not disclose, make obvious, or otherwise suggest the structure of the applicant's claimed invention together with the other limitations of the dependent claims, such as the configuration of the pre-molded substrate, conductive structure, edge lead, edge lead outward side, edge lead inward side, edge lead top side, edge lead bottom side, inner lead, inner lead outward side, inner lead inward side, inner lead top side, inner lead bottom side, first & second encapsulants, upper portion of the edge lead outward side, upper portion of the inner lead outward side, lower portion of the edge lead inward side, lower portion of the inner lead inward side, electronic component, second encapsulant top, second encapsulant sides and conductive cover. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following patents are cited to further show the state of the art with respect to packaged electronic devices: Han et al. (US 2018/0294235 A1) Kim et al. (US 2016/0225687 A1). Any inquiry concerning this communication or earlier communications from the examiner should be directed to IDA M SOWARD whose telephone number is (571)272-1845. The examiner can normally be reached Monday through Thursday, 7am to 5:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. IMS October 5, 2026 /IDA M SOWARD/Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Jul 26, 2024
Application Filed
Aug 12, 2024
Response after Non-Final Action
Oct 07, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12765223
DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME
3y 3m to grant Granted Oct 13, 2026
Patent 12765247
OPTICAL CONTROL PANEL, DISPLAY APPARATUS INCLUDING SAME, AND METHOD OF MANUFACTURING THE DISPLAY APPARATUS
3y 4m to grant Granted Oct 13, 2026
Patent 12757577
DISPLAY DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME INCLUDING SIGNAL TRANSMISSION REGION
3y 10m to grant Granted Oct 06, 2026
Patent 12757611
DISPLAY DEVICE, METHOD FOR MANUFACTURING DISPLAY DEVICE, AND FINGERPRINT SENSOR
3y 2m to grant Granted Oct 06, 2026
Patent 12757385
SEMICONDUCTOR DEVICE
3y 0m to grant Granted Oct 06, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
93%
Grant Probability
99%
With Interview (+5.4%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1376 resolved cases by this examiner. Grant probability derived from career allowance rate.

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