DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the RCE and amendment filed on 1/30/2026.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/30/2026 has been entered.
Claims 1 and 11 have been amended.
The objections and rejections from the prior correspondence that are not restated herein are withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 5-7, 9-13, and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilkinson (US 2023/0044342) and Tamilarasan et al. (US 2023/0325324).
With respect to claim 1, Wilkinson teaches of a system for hiding memory access latency in a heterogeneous compute environment, the system comprising: a memory hierarchy having low-tier memory and high-tier memory (fig. 1-2; paragraph 16, 23; memory device 220 includes at least two levels of memory, where tier 1 is a higher bandwidth or lower latency memory than the memory for tier 2);
an input/output (I/O) port configured to map into the low-tier memory (fig. 2-3; paragraph 23, 26-29; where the memory interface receives and forwards read/write requests to the memory, including the tier 2 memory, and forwards responses from the memory to the server. This includes the MMIO mapped registers of the memory interface);
a central processing unit (CPU) associated with the high-tier memory and configured to make one or more page requests for accessing a page stored in the low-tier memory via the I/O port (fig. 3; paragraphs 24-29; where the processors that send read/write requests for pages in the memory via the memory interface); and
an accelerated compute fabric (ACF) comprising a management processor and communicatively coupled with the CPU (fig. 3; paragraph 24, 26-28; where the MAT (claimed ACF comprising a management processor) is coupled with the processors on the server),
the ACF configured to: determine a count of the one or more page requests (fig. 3; paragraph 25-29; where the MAT in the memory interface performs access tracking of the pages using a count of the read/write accesses); and
move content of the page from the low-tier memory to the high-tier memory when the count of the one or more-page requests exceeds a threshold (fig. 3-4; paragraph 24-25, 30-32; 45; where the memory manager determines a hot page threshold number of accesses and when blocks/pages that exceed the threshold are hot and are migrated from far (tier 1) to near (tier 2) memory).
wherein the threshold is determined based on an aggregate bandwidth load to the I/O port (paragraph 16, 20, 24-28; the memory manager performs the determination of a hot page threshold number in terms of number of accesses over an epoch based on the histogram bin data from memory interface 310 (claimed I/O port). The histogram bin data is a distribution of pages with respect to the distribution of counts of accesses over a time duration. Thus the overall histogram is an aggregate of the counts of the page distribution, with the counts of the pages specifying the bandwidth for that page over the memory interface).
Wilkinson fails to explicitly teach of wherein the threshold is dynamically adjusted in real time based on a current aggregate bandwidth load to the I/O port.
However, Tamilarasan teaches of wherein the threshold is dynamically adjusted in real time based on a current aggregate bandwidth load to the I/O port (paragraph 194; where the threshold is tuned based on the current data storage system I/O workload dynamically as the conditions of the current state of the data storage system change over time).
Wilkinson and Tamilarasan are analogous art because they are from the same field of endeavor, as they are directed to managing memory tiering.
It would have been obvious to one of ordinary skill in the art having the teachings Wilkinson and Tamilarasan before the time of the effective filing of the claimed invention to incorporate the dynamically adjustable threshold of Tamilarasan in Wilkinson. Their motivation would have been to enable adaptation of the system to current conditions (Tamilarasan, paragraph 194).
With respect to claim 11, the combination of Wilkinson and Tamilarasan teaches of the limitations cited and described above with respect to claim 1 for the same reasoning as recited with respect to claim 1.
Wilkinson also teaches of enabling access to the transferred content in the high-tier memory (paragraph 16; where the frequently accessed pages are mapped in tier 1 memory. As they are frequently accessed and were moved to tier 1 memory in order to reduce access times, the migrated data must be accessible in the tier 1 memory).
With respect to claims 5 and 16, Wilkinson teaches of wherein the ACF is further configured to move content of a page stored in the high-tier memory to the low-tier memory based on a count of page requests (paragraph 25, 45; where a tier 1 page is migrated to tier 2 page based on the count of accesses for the page).
With respect to claims 6 and 17, Wilkinson teaches of wherein the low-tier memory is a Compute Express Link (CXL) memory, and the high-tier memory is the CPU’s main memory comprising a Double Data Rate (DDR) memory (fig. 1-2; paragraph 15-16; where tier 1 memory is DDR attached memory and tier 2 memory is CXL attached memory).
With respect to claims 7 and 18, Wilkinson teaches of wherein a load on the I/O port is indicative of a number of page requests made by the CPU via the I/O port for a respective page (fig. 3; paragraph 25-26; where the hot block threshold is set to identify hot blocks based on their number of accesses over a time. These accesses occur via the memory interface).
With respect to claims 9 and 12, Wilkinson teaches of wherein, in response to the count of the one or more page requests exceeding the predetermined threshold, the CPU is further configured to mark the page as missing to trigger a page fault (paragraphs 2-3; where page faults are induced by un-mapping pages to determine in a page is accessed).
With respect to claims 10 and 13, Wilkinson teaches of wherein the ACF is further configured to: update a remapping table to point to a physical location in the high-tier memory where the content of the page has been transferred to (paragraph 16, 20, 27, 53; where the memory addresses are mapped to counters, they must be updated when the data is moved so the count remains accurate); and
enable access to the transferred content of the page in the high-tier memory (paragraph 16; where the frequently accessed pages are mapped in tier 1 memory. As they are frequently accessed and were moved to tier 1 memory in order to reduce access times, the migrated data must be accessible in the tier 1 memory).
Claim(s) 4 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilkinson, Tamilarasan, and Coburn et al. (US 2018/0046411).
With respect to claims 4 and 20, the combination of Wilkinson and Tamilarasan fails to explicitly teach of wherein a counting bloom filter is used to determine the count of the one or more page requests.
However, Coburn teaches of wherein a counting bloom filter is used to determine the count of the one or more page requests (fig. 4; paragraph 34, 38-39; where a counting bloom filter is used to maintain the access statistics for the pages).
Wilkinson, Tamilarasan, and Coburn are analogous art because they are from the same field of endeavor, as they are directed to memory tiering.
It would have been obvious to one of ordinary skill in the art having the teachings Wilkinson, Tamilarasan, and Coburn before the time of the effective filing of the claimed invention to utilize the counting bloom filters of Coburn to track the access counts in the combination of Wilkinson and Tamilarasan. Their motivation would have been to save space over using counters (Coburn, paragraph 34).
Claim(s) 2-3 and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wilkinson, Tamilarasan, and Patel et al. (US 2023/0051781).
With respect to claim 2, the combination of Wilkinson and Tamilarasan fails to explicitly teach of a page queue interface comprising (i) a first queue for queuing the content of the page from the low-tier memory and (ii) a second queue for queuing destination page locations in the high-tier memory for receiving the content of the page, and wherein, to move the content of the page from the low-tier memory to the high-tier memory, the ACF is further configured to use the page queue interface to transfer the content of the page from the first queue in the low-tier memory to the second queue in the high-tier memory.
However, Patel teaches of a page queue interface comprising (i) a first queue for queuing the content of the page from the low-tier memory and (ii) a second queue for queuing destination page locations in the high-tier memory for receiving the content of the page (fig. 3-4; paragraph 41-42, 46-47; where I/O queues are created in the storage target and the host and are used to transfer requests and data between them. In the combination with Wilkinson, the queues are between the host and each of the tiers, see Wilkinson fig. 1), and
The combination of Wilkinson, Tamilarasan, and Patel teaches of wherein, to move the content of the page from the low-tier memory to the high-tier memory, the ACF is further configured to use the page queue interface to transfer the content of the page from the first queue in the low-tier memory to the second queue in the high-tier memory (Wilkinson, fig. 3-4; paragraph 24-25, 30-32; 45; Patel, fig. 3-4; paragraph 41-42, 46-47; In the combination the data is migrated from the tier 2 to tier 1 using the I/O queues in each tier from Patel).
Wilkinson, Tamilarasan, and Patel are analogous art because they are from the same field of endeavor, as they are directed to memory tiering.
It would have been obvious to one of ordinary skill in the art having the teachings Wilkinson, Tamilarasan, and Patel before the time of the effective filing of the claimed invention to incorporate the I/O queues in each of the storage tiers and hosts in the combination of Wilkinson and Tamilarasan as taught in Patel. Their motivation would have been to more efficiently communicate between locations.
With respect to claim 3, Patel teaches of wherein the first queue is a device-side queue and the second queue is a CPU-side queue (Patel, fig. 3-4; paragraph 41-42, 46-47; where the queues are in each storage device and the host).
The reasoning for obviousness is the same as indicated above with respect to claim 2.
With respect to claims 14-15, the combination of Wilkinson, Tamilarasan, and Patel teaches of the limitations cited and described above with respect to claims 2-3 for the same reasoning indicated with respect to claims 2-3.
Response to Arguments
Applicant's arguments with respect to independent claims 1 and 11 have been considered but are moot because of the new reference(s) being applied, in light of the amendment, to the particular limitations the arguments are referencing. Thereby the arguments no longer apply to the rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL C KROFCHECK whose telephone number is (571)272-8193. The examiner can normally be reached on Monday - Friday 8am -5pm, first Friday off.
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/Michael Krofcheck/Primary Examiner, Art Unit 2138