DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is responsive to amendment filed on 06/16/2026. Claims 1-20 have been examined and are pending in this application.
Response to Arguments
Applicant's arguments filed 06/16/2026 have been fully considered but they are not persuasive.
Applicant argues, page 1 of the remarks, “Thus, a person of ordinary skill in relevant field would recognize that the memory system 3 of Nagai does not use SQHTP configured in the host 2.”
The Examiner respectfully disagrees. In sharp contrast, the value of SQHTP stored in the host memory (RAM 22) is critically needed by the memory subsystem 3 of Nagai. For example, Nagai states “The value of the SQTP 4111-n is updated to the value of the updated SQHTP 224-n. Such an update of the SQTP 4111-n via the doorbell register triggers the controller 4 to start processing each of the commands stored in the submission queue 221-n.” Para 0088 and FIG. 1. The value is critical because the controller 4 cannot start processing the commands until and unless “The value of the SQTP 4111-n is updated to the value of the updated SQHTP 224-n.”
In view of the foregoing remarks, independent claims 1, 9, and 18 are not in a condition for allowance. Claims depending therefrom, either directly or indirectly, are also not in a condition for allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Nagai US 2024/0419359 (“Nagai”) in view of Manula et al. US 2014/0181323 (“Manula”).
As per independent claim 1, Nagai teaches A method (“… methods described herein …” para 0316), comprising:
setting up a plurality of submission queues to send storage access commands from a host system to a memory sub-system (“… RAM 22 is used to store submission queues (SQs) 221-0, …, 221-v, …” para 0040 and FIG. 1. “Each of the submissions queues 221-0, …, 221-v is a queue for storing commands issued by the host 2 to the memory subsystem 3.” Para 0041 and FIG. 1);
configuring, in a random access memory (RAM 22, para 0040 and FIG. 1) accessible to both the memory sub-system (“The command fetch processing identifies a slot in which a command to be fetched is stored … in the plurality of submission queues … and fetches the command stored in the identified slot.” Para 0061 and FIG. 1) and the host system (“Each of the submission queues … is a queue for storing commands issued by the host 2 to the memory system 3.” Para 0041 and FIG. 1), a plurality of slots each configured to store data indicative of a queue status of one submission queue among the plurality of submission queues (“The other part of the storage area of the RAM 22 is used to store … submission queue host tail pointers (SQHTPs) 224-0, . . . , 224-v,” para 0040. “The host 2 uses … SQHTPs 224-0, . . . , 224-v, to manage submission queues 221-0, . . . , 221-v. … SQHTP 224-n indicates a free slot in which a new command will be stored next among the plurality of slots in submission queue 221-n.” Para 0041);
entering, by the host system, the storage access commands into the submission queues (“FIG. 2(b) shows the submission queue 221-n in which two commands are stored.” Para 0078 and FIG. 2);
providing, by the host system, contents in the slots to indicate the entering of the storage access commands into the submission queues (“Step 2: The host 2 updates the value of the SQHTP 224-n. The host 2 increments the value of the SQHTP 224-n by the number of commands stored in step 1.” Para 0087 and FIG. 3), wherein the providing of the contents does not trigger the memory sub-system to process the submission queue (“The SQHTP is an SQTP managed by the host 2 and indicates the slot in which the next command to be issued is to be stored.” Para 0198);
retrieving, by the memory sub-system, the contents from the slots (“The value of the SQTP 4111-n is updated to the value of the updated SQHTP 224-n.” Para 0088. Further, Nagai teaches “the memory system 3 can read and write a RAM 22 of the host 2.” Para 0035. SQHTP is located in RAM 22. Hence, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Nagai with the memory system 3 retrieving the SQHTP value. The motivation would be that when the value of SQHTP is written to SQTP, the memory system 3 starts processing host commands);
Nagai discloses all of the claimed limitations from above, and additionally teaches a host generated submission queue identifier, paras 0068, 0099. However, in Nagai, the submission queue identifier is transmitted to the host by the memory controller in response to the completion of a command, para 0068. Therefore, Nagai does not explicitly teach “identifying, by the memory sub-system and based on the contents retrieved from the slots, one or more submission queues to retrieve a subset of the storage access commands”.
However, in an analogous art in the same field of endeavor, Manula teaches identifying, by the memory sub-system and based on the contents retrieved from the slots, one or more submission queues to retrieve a subset of the storage access commands (“A doorbell is an indication to the send queue scheduler that a command is in a send queue … a doorbell includes a queue pair identifier and a sequence number. Using the queue pair identifier and the sequence number, the send queue scheduler obtains and processes the corresponding commands.” Para 0012).
Given the teaching of Manula, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to further modify the scope of the invention of Nagai with “identifying, by the memory sub-system and based on the contents retrieved from the slots, one or more submission queues to retrieve a subset of the storage access commands”. The motivation would be that the invention avoids deadlock of a scheduler, para 0012 of Manula, thus improving efficiency.
As per dependent claim 2, Nagai in combination with Manula discloses the method of claim 1. Nagai teaches wherein the plurality of slots correspond to the plurality of submission queues respectively (“The host 2 uses … SQHTPs 224-0, . . . , 224-v, to manage submission queues 221-0, . . . , 221-v.” Para 0041 and FIG. 1);
each of the plurality of slots is configured to store data indicative of a queue status of a predetermined one of the plurality of submission queues (“SQHTP 224-n indicates a free slot in which a new command will be stored next among the plurality of slots in submission queue 221-n.” Para 0041 and FIG. 1).
As per dependent claim 3, Nagai in combination with Manula discloses the method of claim 2. Nagai teaches wherein each of the plurality of slots is configured to store an integer configured to identify a sequence number of a command entered at an end of a respective submission queue (“The information on the fetched command includes at least the contents and the CID [Command Identifier] of the fetched command.” Para 0061).
As per dependent claim 4, Nagai in combination with Manula discloses the method of claim 3. Nagai teaches wherein the random access memory is configured in the host system (“RAM 22 of the host 2.” Para 0035 and FIG. 1).
As per dependent claim 5, Nagai in combination with Manula discloses the method of claim 3. Nagai teaches wherein the random access memory is configured in the memory sub-system (“RAM 411 of the memory system 3,” para 0035 and FIG. 1).
As per dependent claim 6, Nagai in combination with Manula discloses the method of claim 3. Nagai teaches wherein the plurality of slots are configured as an array in the random access memory in accordance with a count of the plurality of submission queues set up at a time of booting up the host system (“The host 2 uses … SQHTPs 224-0, . . . , 224-v, to manage submission queues 221-0, . . . , 221-v.” Para 0041 and FIG. 1).
As per dependent claim 7, Nagai in combination with Manula discloses the method of claim 1. Nagai teaches wherein the plurality of slots are configured in a cyclic buffer allocated from the random access memory (“The cycle counter indicates the number of times the pointer has cycled the cyclic queue.” Para 0112).
As per dependent claim 8, Nagai in combination with Manula discloses the method of claim 7. Nagai teaches wherein a count of the slots is smaller than a count of the submission queues (“in a case where the value of the cycle counter before the update is the upper limit value, the cycle counter control circuit 45 sets the cycle counter to its initial value instead of incrementing it by one.” Para 0112).
As per independent claim 9, many of the claim limitations of this claim are rejected based on arguments provided above for similar rejected independent claim 1. As per other claim limitations, Nagai teaches A memory sub-system (”FIG. 1 is a block diagram illustrating an example of a configuration of an information processing system 1 that includes a memory system” para 0032 and FIG. 1), comprising:
non-volatile memory cells configured to provide a storage capacity of the memory sub-system (“The memory system 3 includes a nonvolatile memory.” Para 0034 and FIG. 1);
at least one processor (“CPU 21” para 0038 FIG. 1 and “CPU 42” para 0050 and FIG. 1) configured to:
execute the subset of the storage access commands (“The controller 4 executes read processing to read data from the nonvolatile memory 5 and write processing to write data into the nonvolatile memory 5 by processing each I/O command received from the host 2.” Para 0047 and FIG. 1).
As per dependent claims 10-14, these claims are respectively rejected based on arguments provided above for similar rejected dependent claims 2-3 and 6-8.
As per dependent claim 15, Nagai in combination with Manula discloses the system of claim 14. Nagai may not explicitly disclose, but Manula teaches wherein each of the plurality of slots is configured to store an identification of a submission queue and a queue status of the submission queue identified by the identification (“A doorbell is an indication to the send queue scheduler that a command is in a send queue waiting to be processed by the send queue scheduler. … a doorbell includes a queue pair identifier and a sequence number.” Para 0012).
The same motivation that was utilized for combining Nagai and Manula as set forth in claim 14 is equally applicable to claim 15.
As per dependent claim 16, Nagai in combination with Manula discloses the system of claim 15. Nagai teaches further comprising: a doorbell register configured to have a size same as a slot size of the plurality of slots (“SQTPs [Submission Queue Tail Pointers] … are values stored in submission queue (SQ) tail doorbell registers in the storage area of RAM 411.” Para 0053 and FIG. 1).
As per dependent claim 17, Nagai in combination with Manula discloses the system of claim 16. Nagai teaches wherein the at least one processor is further configured to store a content of the doorbell register into a slot in the cyclic buffer in response to the host system writing to the doorbell register (“The cycle counter indicates the number of times the pointer has cycled the cyclic queue.” Para 0112).
As per independent claim 18, this claim is rejected based on arguments provided above for similar rejected independent claim 9. See FIG. 1 of Nagai for host 2.
As per dependent claim 19, Nagai in combination with Manula discloses the system of claim 18. Nagai teaches wherein each of the plurality of submission queues is assigned to only one of the processor cores to submit commands for execution in the memory sub-system (“Each of the doorbell registers is a storage area in the RAM 411 that, has a function of when written to from the outside through an I/F, notifying the CPU 42 to generate an interrupt or activate hardware such as the cycle counter control circuit 45, and rapidly starting operation in response to the write.” Para 0053 and FIG. 1).
As per dependent claim 20, this claim is rejected based on arguments provided above for similar rejected dependent claim 2.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZUBAIR AHMED whose telephone number is (571)272-1655. The examiner can normally be reached 7:30AM - 5:00PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, HOSAIN T. ALAM can be reached at (571) 272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZUBAIR AHMED/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
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