DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is sent in response to Applicant’s Communication received 7/26/2024 for application number 18/785,694. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, and claims.
Claims 1 – 20 are presented for examination.
Drawings
Examiner contends that the drawings filed 7/26/2024 are acceptable for examination proceedings.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,086,412. Although the claims at issue are not identical, they are not patentably distinct from each other because they are simple changes of a statutory category. Claim 1 of patent 12,086,412 include all the limitations of the instant claim 1 and therefore anticipates the instant claim. All features of instant dependent claims 2-7 are covered by claims 1-7 of patent 12,086,412 and are therefore rejected accordingly. The other independent claims 8 and 15 of the instant application and their corresponding dependent claims are rejected under the same rationale and are covered by claims 8-14 and 15-20 of patent 12,086,412 respectively. Comparisons of selected claims are shown in the following table.
Instant Application (18/785,694)
USPAT 12,086,412
1. A system comprising: a memory device; a first interface port and a second interface port operatively coupled with the memory device; and a processing device, operatively coupled with the memory device, to perform operations comprising: receiving, from a firmware component of the memory device, a configuration setting based on an interrupt message associated with the first interface port; identifying an arbitration method for allocating one or more resources to the first interface port in a threshold period of time based on the configuration setting; and allocating, by the processing device, the one or more resources to the first interface port according to the identified arbitration method for the threshold period of time, wherein the one or more resources includes memory access commands.
1. A system comprising: a memory device; a first interface port and a second interface port operatively coupled with the memory device; and a processing device, operatively coupled with the memory device, to perform operations comprising: detecting a triggering event associated with the first interface port; responsive to detecting the triggering event, sending an interrupt message to a firmware component of the memory device; receiving, from the firmware component, a configuration setting based on the interrupt message, wherein the configuration setting comprises one or more instructions referencing (i) an arbitration method for allocating one or more resources to the first interface port and (ii) a threshold period of time for using the arbitration method; identifying the arbitration method and the threshold period of time referenced in the one or more instructions of the configuration setting; and allocating, by the processing device, the one or more resources to the first interface port according to the identified arbitration method for the threshold period of time; wherein the one or more resources include memory access commands.
2. The system of claim 1, wherein the operations further comprise: detecting a triggering event associated with the first interface port by receiving a message from a host system connected to the first interface port, wherein the message indicates a reduced power mode at the first interface port; and sending the interrupt message to the firmware component of the memory device.
1. …sending an interrupt message to a firmware component of the memory device;…
2. The system of claim 1, wherein to detect the triggering event associated with the first interface port, the processing device is to perform operations further comprising: receiving a message from a host system connected to the first interface port, wherein the message indicates a reduced power mode at the first interface port.
3. The system of claim 1, wherein the operations further comprises: detecting a triggering event associated with the first interface port by determining that a counter associated with the first interface port satisfies a threshold criterion, wherein the counter references a number of memory access commands received at the first interface port; and sending the interrupt message to the firmware component of the memory device.
1. …sending an interrupt message to a firmware component of the memory device;…
3. The system of claim 1, wherein to detect the triggering event associated with the first interface port, the processing device is to perform operations further comprising: determining that a counter associated with the first interface port satisfies a threshold criterion, wherein the counter references a number of memory access commands received at the first interface port.
4. The system of claim 1, wherein the operations further comprises: detecting a triggering event associated with the first interface port by identifying a decrease in a speed associated with the first interface port; determining that the decrease in the speed associated with the first interface port satisfies a threshold criterion; and sending the interrupt message to the firmware component of the memory device.
1. …sending an interrupt message to a firmware component of the memory device;…
4. The system of claim 1, wherein to detect the triggering event associated with the first interface port, the processing device is to perform operations further comprising: identifying a decrease in a speed associated with the first interface port; and determining that the decrease in the speed associated with the first interface port satisfies a threshold criterion.
5. The system of claim 1, wherein to receive the configuration setting, the processing device is to perform operations further comprising: accessing the configuration setting stored in one or more registers associated with the memory device, wherein the configuration setting is stored, by the firmware component, in the one or more registers via an internal bus.
5. The system of claim 1, wherein to receive the configuration setting, the processing device is to perform operations further comprising: accessing the configuration setting stored in one or more registers associated with the memory device, wherein the configuration setting is stored, by the firmware component, in the one or more registers via an internal bus.
6. The system of claim 1, wherein the configuration setting comprises an instruction to allocate the one or more resources to the first interface port using a weighted round robin arbitration.
6. The system of claim 1, wherein the configuration setting comprises an instruction to allocate the one or more resources to the first interface port using a weighted round robin arbitration.
7. The system of claim 1, wherein the configuration setting comprises an instruction to allocate the one or more resources to the first interface port using a priority arbitration.
7. The system of claim 1, wherein the configuration setting comprises an instruction to allocate the one or more resources to the first interface port using a priority arbitration.
8. A method comprising: determining, by a firmware component of a memory device, a configuration setting based on an interrupt message associated with a first interface port, wherein the memory device is operatively coupled with the first interface port and a second interface port, and wherein the configuration setting comprises one or more instructions referencing an arbitration method for allocating one or more resources to the first interface port in a threshold period of time; and sending the configuration setting to a hardware component of the memory device, wherein the one or more resources is to be allocated to the first interface port according to the arbitration method for the threshold period of time identified based on the configuration setting, and wherein the one or more resources includes memory access commands.
8. A method comprising: receiving, by a firmware component of a memory device, an interrupt message, wherein the interrupt message is received in response to a triggering event detected at a first interface port, wherein the memory device is operatively coupled with the first interface port and a second interface port; determining a configuration setting based on the interrupt message, wherein the configuration setting comprises one or more instructions referencing (i) an arbitration method for allocating one or more resources to the first interface port and (ii) a threshold period of time for using the arbitration method; identifying the arbitration method and the threshold period of time referenced in the one or more instructions of the configuration setting; and sending the configuration setting to a hardware component of the memory device, wherein the one or more resources is to be allocated to the first interface port according to the identified arbitration method for the threshold period of time; wherein the one or more resources include memory access commands.
9. The method of claim 8, wherein sending the configuration setting to the hardware component of the memory device comprises storing the configuration setting in one or more registers associated with the memory device via an internal bus.
9. The method of claim 8, wherein sending the configuration setting to the hardware component of the memory device comprises storing the configuration setting in one or more registers associated with the memory device via an internal bus.
10. The method of claim 8, further comprising: receiving, by a firmware component of a memory device, an interrupt message, wherein the interrupt message is received in response to a triggering event detected at the first interface port, and wherein the triggering event detected at the first interface port of the memory device comprises a reduced power mode at the first interface port.
8. …receiving, by a firmware component of a memory device, an interrupt message, wherein the interrupt message is received in response to a triggering event detected at a first interface port…
10. The method of claim 8, wherein the triggering event detected at the first interface port of the memory device comprises a reduced power mode at the interface port.
11. The method of claim 8, further comprising: receiving, by a firmware component of a memory device, an interrupt message, wherein the interrupt message is received in response to a triggering event detected at the first interface port, and wherein the triggering event detected at the first interface port of the memory device comprises a threshold decrease in speed associated with the first interface port.
8. …receiving, by a firmware component of a memory device, an interrupt message, wherein the interrupt message is received in response to a triggering event detected at a first interface port…
11. The method of claim 8, wherein the triggering event detected at the first interface port of the memory device comprises a threshold decrease in speed associated with the interface port.
12. The method of claim 8, wherein determining the configuration setting based on the interrupt message further comprises: identifying a current first speed of the first interface port; identifying a current second speed of the second interface port; determining a speed ratio between the first interface port and the second interface port based on the current first speed of the first interface port and the current second speed of the second interface port; and determining an allocation of the one or more resources to the first interface port based on the speed ratio.
12. The method of claim 8, wherein determining the configuration setting based on the interrupt message further comprises: identifying a current first speed of the first interface port; identifying a current second speed of the second interface port; determining a speed ratio between the first interface port and the second interface port based on the current first speed of the first interface port and the current second speed of the second interface port; and determining an allocation of the one or more resources to the first interface port based on the speed ratio.
13. The method of claim 12, wherein the determined allocation of the one or more resources to the first interface port is a weighted round robin arbitration.
13. The method of claim 12, wherein the determined allocation of the one or more resources to the first interface port is a weighted round robin arbitration.
14. The method of claim 12, wherein the determined allocation of the one or more resources to the first interface port is a priority arbitration.
14. The method of claim 12, wherein the determined allocation of the one or more resources to the first interface port is a priority arbitration.
15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: receiving, from a firmware component of a memory device, a configuration setting based on an interrupt message associated with a first interface port, wherein the memory device is operatively coupled with the first interface port and a second interface port; identifying an arbitration method for allocating one or more resources to the first interface port in a threshold period of time based on the configuration setting; and allocating, by the processing device, the one or more resources to the first interface port according to the identified arbitration method for the threshold period of time, wherein the one or more resources includes memory access commands.
15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: detecting a triggering event associated with a first interface port, wherein a memory device is operatively coupled to the first interface port and a second interface port; responsive to detecting the triggering event, sending an interrupt message to a firmware component of the memory device; receiving, from the firmware component, a configuration setting based on the interrupt message, wherein the configuration setting comprises one or more instructions referencing (i) an arbitration method for allocating one or more resources to the first interface port and (ii) a threshold period of time for using the arbitration method; identifying the arbitration method and the threshold period of time referenced in the one or more instructions of the configuration setting; and allocating, by the processing device, the one or more resources to the first interface port according to the identified arbitration method for the threshold period of time; wherein the one or more resources include memory access commands.
16. The non-transitory computer-readable storage medium of claim 15, wherein the operations further comprise: detecting a triggering event associated with the first interface port by receiving a message from a host system connected to the first interface port, wherein the message indicates a reduced power mode at the first interface port; and sending the interrupt message to the firmware component of the memory device.
16. The non-transitory computer-readable storage medium of claim 15, wherein to detect the triggering event associated with the first interface port, the processing device is to perform operations further comprising: receiving a message from a host system connected to the first interface port, wherein the message indicates a reduced power mode at the first interface port.
15. … sending an interrupt message to a firmware component of the memory device…
17. The non-transitory computer-readable storage medium of claim 15, wherein the operations further comprises: detecting a triggering event associated with the first interface port by determining that a counter associated with the first interface port satisfies a threshold criterion, wherein the counter references a number of memory access commands received at the first interface port; and sending the interrupt message to the firmware component of the memory device.
17. The non-transitory computer-readable storage medium of claim 15, wherein to detect the triggering event associated with the first interface port, the processing device is to perform operations further comprising: determining that a counter associated with the first interface port satisfies a threshold criterion, wherein the counter references a number of memory access commands received at the first interface port.
15. … sending an interrupt message to a firmware component of the memory device…
18. The non-transitory computer-readable storage medium of claim 15, wherein the operations further comprises: detecting a triggering event associated with the first interface port by identifying a decrease in a speed associated with the first interface port; determining that the decrease in the speed associated with the first interface port satisfies a threshold criterion; and sending the interrupt message to the firmware component of the memory device.
18. The non-transitory computer-readable storage medium of claim 15, wherein to detect the triggering event associated with the first interface port, the processing device is to perform operations further comprising: identifying a decrease in a speed associated with the first interface port; and determining that the decrease in the speed associated with the first interface port satisfies a threshold criterion.
15. … sending an interrupt message to a firmware component of the memory device…
19. The non-transitory computer-readable storage medium of claim 15, wherein to receive the configuration setting, the processing device is to perform operations further comprising: accessing the configuration setting stored in one or more registers associated with the memory device, wherein the configuration setting is stored, by the firmware component, in the one or more registers via an internal bus.
19. The non-transitory computer-readable storage medium of claim 15, wherein to receive the configuration setting, the processing device is to perform operations further comprising: accessing the configuration setting stored in one or more registers associated with the memory device, wherein the configuration setting is stored, by the firmware component, in the one or more registers via an internal bus.
20. The non-transitory computer-readable storage medium of claim 15, wherein the configuration setting comprises an instruction to allocate the one or more resources to the first interface port using a priority arbitration.
20. The non-transitory computer-readable storage medium of claim 15, wherein the configuration setting comprises an instruction to allocate the one or more resources to the first interface port using a priority arbitration.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, Huang et al. (PGPUB 2017/0228330) teaches a system comprising:
a device;
a first interface port and a second interface port operatively coupled with the device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
receiving, from a firmware component of the device, a configuration setting based on an interrupt message associated with the first interface port; and
allocating, by the processing device, the one or more resources to the first interface port.
Spencer (PGPUB 2004/0243739) teaches receiving, from a firmware component of the memory device, a configuration setting based on an interrupt message; identifying an arbitration method for allocating one or more resources; allocating, by the processing device, the one or more resources according to the identified arbitration method, wherein the one or more resources includes memory access commands.
Neither Huang et al. nor Spencer teach the full limitations of identifying an arbitration method for allocating one or more resources to the first interface port in a threshold period of time based on the configuration setting; allocating, by the processing device, the one or more resources to the first interface port according to the identified arbitration method for the threshold period of time. The prior art of record do not teach individually or in combination all the limitations required by the independent claims as a whole.
Claims 8 and 15 are similar in scope to claim 1, and thus also includes allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicant is reminded that in amending in response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR §1.111(c).
Chiu et al. (PGPUB 2018/0341430) teaches scheduling and executing commands in flash memory in a round robin algorithm, and is performed by loading firmware [0021].
Niu et al. (USPAT 9,830,086) teaches arbitration policy may be defined and updated by BIOS, and that arbitration policy may follow round-robin algorithm.
Chang et al. (PGPUB 2017/0249191) teaches arbitrator and event distributor being implemented in firmware, and receiving a message that includes a task or event type [0033].
Lockerbie et al. (PGPUB 2012/0250745) teaches firmware to control bus arbitration and message decoding [0024].
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/DANNY CHAN/Primary Examiner, Art Unit 2175
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