DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO ARGUMENTS
Applicant’s arguments with respect to claim 13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
I. ALLOWABLE SUBJECT MATTER
Claims 1-2, 4-6, 8-9, and 12 are allowed.
II. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13 are rejected under 35 U.S.C. 103 as being unpatentable over Smith et al. (US Patent 10,015,087) in view of Sindhu et al. (US Patent 5,905,725) and LEE et al. (US Pub.: 2009/0161659).
As per claim 13, Smith teaches/suggests an integrated circuit (IC), comprising: a first bus interface configured to be coupled to a communication bus, wherein the communication bus is configure to transfer packets from a second bus interface to the first bus interface (e.g. associated with communication bus for transferring data packet between MOCB crossbar’s interface to local SoC device and MOCB crossbar’s interface to nonlocal Soc Device: Fig. 2A-2B; col. 6, l. 41 to col. 8, l. 42); and a crossbar (e.g. associated with MOCB Crossbar (108)) coupled to the first bus interface and configured to: receive data; route to a first memory (e.g. associated with first write command which writes to a first given address of corresponding storage/memory: col. 8, ll. 33-66); receive data; and route to a second memory (e.g. associated with second write command which writes to a second given address of corresponding storage/memory: col. 8, ll. 33-66); being coupled to the first bus interface and the second bus interface (e.g. associated with MOCB crossbar’s interface to nonlocal Soc Device and MOCB crossbar’s interface to local SoC device) (Fig. 2A-2B; Fig. 4A-4B; col. 6, l. 41 to col. 9, l. 49; and col. 10, ll. 1-59).
Smith does not teach the IC comprising:
being coupled to a plurality of lanes in a bus, wherein each of the plurality of lanes in the bus operating accordingly;
having a first packet from a first lane in a first plurality of consecutive clock cycles;
read a channel identifier in the first packet;
route the first packet based on the channel identifier,
having a second packet from a second lane in a second plurality of consecutive clock cycles;
read a second channel identifier in the second packet; and
route the second packet based on the second channel identifier,
wherein: each lane of the plurality of lanes consists of a physical electrical conductor electrically coupled; and
the second plurality of consecutive clock cycles overlaps in time with the first plurality of clock cycles.
Sindhu teaches/suggests a system comprising: being coupled to a plurality of lanes in a bus, wherein each of the plurality of lanes in the bus operating accordingly (e.g. associated with communication paths of output ports (108) in Fig. 2B); having a first packet from a first lane in a first plurality of consecutive clock cycles (e.g. associated with receiving first packet at first input port (107): col. 4, l. 30 to col. 5, l. 18); read a channel identifier in the first packet (e.g. associated with reading key from first packet: col. 4, ll. 30-51); route the first packet based on the channel identifier (e.g. associated with forwarding the first packet to output port (180) based on key: col. 4, ll. 30-51); having a second packet from a second lane in a second plurality of consecutive clock cycles (e.g. associated with receiving second packet at second input port (107): col. 4, l. 30 to col. 5, l. 18); read a second channel identifier in the second packet (e.g. associated with reading key from second packet: col. 4, ll. 30-51); and route the second packet based on the second channel identifier (e.g. associated with forwarding second packet to output port (180) based on key: col. 4, ll. 30-51), wherein: each lane of the plurality of lanes consists of a physical electrical conductor electrically coupled (e.g. associated with port(s) being physical that would have conducted electrical signal when communicating packet(s): Fig. 2B; and col. 4, ll. 14-51); and the second plurality of consecutive clock cycles operates in association with the first plurality of clock cycles (col. 4, l. 30 to col. 5, l. 18) (Fig. 2B-4B; and col. 4, l. 14 to col. 6, l. 13).
LEE teaches/suggests a system comprising: being overlaps in time with another (e.g. associated with simultaneously receiving data packets: [0143]-[0146]) (Fig. 4; Fig. 6; [0069]-[0080]; and [0143]-[0146]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Sindhu’s data transferring architecture and LEE’s simultaneous receiving into Smith’s IC for the benefit of implementing an architecture that efficiently manage and route packets (Sindhu, col. 2, ll. 66-67) and improving data transmitting/receiving performance (LEE, [0015]) to obtain the invention as specified in claim 13.
III. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 October 04, 2026
