DETAILED ACTION
This action is responsive to the following communications: the Application filed July 26,2024, and Information Disclosure Statement filed on June 06, 2025.
Claims 1-24 are pending. Claims 1, 10, 17 and 21 are independent.
Information Disclosure Statement
Acknowledged is made of Application’s Information Disclosure Statement (IDS) Form PTO-1449 filed on June 06, 2025. This IDS has been considered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, 9, 10-11, 17, 18, 20, 21-24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gong et al. (2021/0375360).
Regarding independent claim 1, Gong et al. disclose a memory device comprising: first (114, figure 2) and second electrodes (102, figure 2) apart from each other; a self-selecting (OTS SELECTOR, figure 2) memory layer between the first and second electrodes (figure 2), having an ovonic threshold switching characteristic (see para.[0028] discloses: Turning now to an overview of the aspects of the invention, one or more embodiments of the invention address the above-described shortcomings of the prior art by stacking a PCM cell together with a chalcogenide-based ovonic threshold switch (OTS) to form a multi-level cell (MLC) 1S1R structure. The OTS can switch between a minimum (base) voltage level and a maximum (peak) voltage level. Unlike transistor switches) , comprising a chalcogenide-based material (see para.[0028] above), and configured to have a threshold voltage varying depending on a polarity of and strength of a voltage applied thereto (see para.[0034] and figure 4 below); and a resistive memory layer between the second electrode and the self-selecting memory layer and having a resistance characteristic varying depending on a voltage applied thereto, wherein the memory device is configured to implement multi-level resistance states by changing at least one of a pulse polarity, a number of pulses, a pulse height, and a pulse width of a voltage applied between the first and second electrodes (see paragraphs [0029]-[0043] and figures 2-4).
[0033] Adhesion is effected between the OTS selector 106 and the PCM cell 110 via the second interfacial layer 108. The PCM cell 110 includes a phase change material having a thickness ranging, for example, from about 10 nm to about 50 nm. The phase change material of the PCM can include a combination of two elements, such as GaSb, InSb, InSe, Sb2Te3 or GeTe, a combination of three elements, such as GeSbTe, GaSeTe, InSbTe, SnSb2Te4 or InSbGe, or a combination of four elements such as AgInSbTe, (GeSn)SbTe, GeSb(SeTe), or TeGeSbS. GeSbTe, which is a combination of germanium (Ge), antimony (Sb) and tellurium (Te), may be used as the PCM 110 in certain embodiments. Accordingly, the phase change material is capable of being transitioned or “switched” between amorphous phase having a relatively high resistance and a crystalline phase having a relatively low resistance (i.e., lower than the amorphous phase) in response to an application of energy such as heat or electrical current.
[0034] In one or more non-limiting embodiments of invention, the phase change material can be formed to establish multiple different resistance levels. The threshold voltage of PCM is correlated to the amount of amorphous region within the PCM cell 110. The threshold voltage of OTS-PCM is the combination of the threshold voltage of the selector 106 and the threshold voltage of PCM cell 110. As such, multi threshold voltage level of the OTS-PCM is capable of being tuned by changing the amount of amorphous with respect to crystalline in a region of the PCM cell 110. Voltage pulses having different voltage levels selected by the OTS selector 106 can therefore be used to change the phase (e.g., the amorp Voltage pulses having different voltage levels selected by the OTS selector 106 can therefore be used to change the phase (e.g., the amorphous phase and the crystalline phase) of a given level of the PCM cell 110. That is, the phase at a first portion of the PCM cell 110 can be changed with respect to a different second portion of the PCM cell 110 thereby making it possible to apply partial voltage pulses that can set or reset a first data value stored at a first portion of the PCM cell 110 while maintaining a second data value stored at a second portion of the PCM cell. In this manner, the PCM cell 110 can be utilized to provide a MLC 1S1R structure 100 capable of storing data of at least 2 or more bits as described in greater detail below. hous phase and the crystalline phase) of a given level of the PCM cell 110.
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Regarding claim 2, Gong et al. disclose the limitation of claim 1.
Gong et al. further disclose wherein the self-selecting memory layer and the resistive memory layer are electrically connected to each other in series (see figures 2-3).
Regarding claim 3, Gong et al. disclose the limitation of claim 1.
Gong et al. further disclose wherein the self-selecting memory layer comprises a chalcogen element including at least one of Se, Te, and S, and at least one of Ge, As, and Sb (see para.[0032] discloses: the OTS selector 106 includes a chalcogenide combination including one or more elements from the group comprising tellurium (Te), selenium (Se), germanium (Ge), silicon (Si), arsenic (As), titanium (Ti), sulfur (S) and antimony (Sb). For example, the OTS selector can include a chalcogenide, including, but not limited to, GeTe, GeSe, GeAsSe, and SiGeAsTe)
Regarding claim 4, Gong et al. disclose the limitation of claim 3.
GONG et al. further disclose wherein the self-selecting memory layer further comprises at least one of In, Al, C, B, Sr, Ga, O, N, Si, Ca, and P (see para.[0032] above).
Regarding claim 6, Gong et al. disclose the limitation of claim 1.
Gong et al. further disclose he memory wherein the memory device is configured to have a pulse voltage of certain polarity applied between the first and second electrodes, and to have multi-level resistance states implemented by adjusting at least one of a number of pulses, a pulse height, and a pulse width of the pulse voltage (see paragraphs [0040]-[0043], also see rejection of claim 1).
Regarding claim 9, Gong et al. disclose the limitation of claim 1.
Gong et al. disclose further comprising: an insert layer in at least one of between the first electrode and the self-selecting memory layer, and between the second electrode and the resistive memory layer (see figure 2, 104 and 112).
Regarding independent claim 10, Gong et al. disclose a method of implementing a multi-level memory by using a memory device, the memory device comprising: first and second electrodes apart from each other; a self-selecting memory layer between the first and second electrodes, having an ovonic threshold switching characteristic, comprising a chalcogenide-based material, and configured to have a threshold voltage varying depending on a polarity of and a strength of a voltage applied thereto; and a resistive memory layer between the second electrode and the self-selecting memory layer and having a resistance characteristic varying depending on a voltage applied thereto, wherein the method comprises: implementing multi-level resistance states by changing at least one of a pulse polarity, a number of pulses, a pulse height, and a pulse width of a voltage applied between the first and second electrodes (see rejection of claim 1).
11. The method of claim 10, wherein the self-selecting memory layer and the resistive memory layer are electrically connected to each other in series (see rejection of claim 2).
12. The method of claim 10, further comprising: applying a pulse voltage of certain polarity between the first and second electrodes; and implementing multi-level resistance states by adjusting at least one of a number of pulses, a pulse height, and a pulse width of the pulse voltage (see rejection of claim 6).
Regarding independent claim 17, Gong et al. disclose a memory device comprising: a plurality of bit lines; a plurality of word lines intersecting the plurality of bit lines; and a plurality of memory cells where the plurality of bit lines and the plurality of word lines intersect each other (figure 3 below), wherein each of the plurality of memory cells comprises: first and second electrodes apart from each other; a self-selecting memory layer between the first and second electrodes, having an ovonic threshold switching characteristic, comprising a chalcogenide-based material, and configured to have a threshold voltage varying depending on a polarity of and a strength of a voltage applied thereto; and a resistive memory layer between the second electrode and the self-selecting memory layer and having a resistance characteristic varying depending on a voltage applied thereto, wherein the memory device is configured to implement multi-level resistance states by changing at least one of a pulse polarity, a number of pulses, a pulse height, and a pulse width of a voltage applied between the first and second electrodes (see rejection of claim 1).
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18. The memory device of claim 17, wherein the self-selecting memory layer and the resistive memory layer are electrically connected to each other in series (see rejection of claim 2).
Regarding claim 20, Gong et al. discloses the limitation of claim 17.
Gong et al. further disclose wherein the plurality of bit lines and the plurality of word lines are in a multi-layer structure alternating vertically with each other, and the memory cells over and under each of the plurality of bit lines are symmetrical with respect to the bit line (figure 3 above).
Regarding independent claim 21. A multi-level memory device comprising: a self-selecting memory device having an ovonic threshold switching characteristic and having a threshold voltage varying depending on a polarity and strength of a voltage applied thereto; a resistive memory device connected in series to the self-selecting memory device and having a resistance characteristic varying depending on a voltage applied thereto; and a memory controller configured to change a height of a pulse voltage of negative (-) polarity applied to the self-selecting memory device (see rejection of claim 1).
Regarding claim 22, Gong et al. disclose the limitation of claim 17.
Gong et al. further discloses wherein the memory controller is configured (see para. [0006] discloses: A controller is in electrical communication with the bit line and the word line. The controller is configured to select at least one voltage pulse from a group of different voltage pulses comprising a read pulse, a partial set pulse, a set pulse, a partial reset pulse, and a reset pulse, and configured to deliver the selected at least one voltage pulse to the at least one MLC 1S1R structure) to change a height of a pulse voltage applied to the resistive memory device (see figure 4 below).
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Regarding claim 23, Gong et al. disclose the limitation of claim 21.
Gong et al. further disclose wherein the memory controller is configured (see para.[0006] discloses: According to a non-limiting embodiment of the invention, a multi-level cell (MLC) one-selector-one-resistor (1S1R) three-dimensional (3D) cross-point memory system includes at least one MLC 1S1R structure including a stacked arrangement of a phase change memory (PCM) cell and a threshold switch selector. An electrically conductive bit line is in electrical communication with the OTS selector, and an electrically conductive word line is in signal communication with the PCM cell. A controller is in electrical communication with the bit line and the word line. The controller is configured to select at least one voltage pulse from a group of different voltage pulses comprising a read pulse, a partial set pulse, a set pulse, a partial reset pulse, and a reset pulse, and configured to deliver the selected at least one voltage pulse to the at least one MLC 1S1R structure) to change a number of pulse voltages applied to the resistive memory device (see figure 4 above).
Regarding claim 24, Gong et al. disclose the limitation of claim 21.
Gong et al. further disclose wherein the memory controller is configured (see para.[0006] above) to change a width of a pulse voltage applied to the resistive memory device (see figure 4 above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gong et al. (US 2021/0375360) in view of MOSENDZ et al. (US 2023/0247843).
Regarding claim 5, Gong et al. disclose the limitation of claim 1.
However, Gong et al. are silent with respect to wherein the resistive memory layer comprises at least one of Al2O3, In2O3, MgO, MoO3, Ta2O5, TiO2, HfO2, PrCaMnO3, V2O5, or ZnO.
MOSENDZ et al. disclose wherein the resistive memory layer comprises at least one of Al2O3, In2O3, MgO, MoO3, Ta2O5, TiO2, HfO2, PrCaMnO3, V2O5, or ZnO (see para.[0039]).
Since Gong et al. and MOSENDZ et al. are both from the same field of endeavor, the purpose disclosed by MOSENDZ et al. would have been recognized in the pertinent art of Gong et al.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Gong et al. to teaching of MOSENDZ et al. for purpose of using Mg0 is capable of supporting two different configurations of the free layer magnetization direction relative to the reference layer magnetization.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gong et al. (US 2021/0375360) in view of KUSAI et al. (US 2012/0091420).
Regarding claim 8, Gong et al. disclose the limitation of claim 1.
However, Gong et al. are silent with respect to further comprising: a third electrode between the self-selecting memory layer and the resistive memory layer.
KUSAI et al. disclose further comprising: a third electrode between the self-selecting memory layer and the resistive memory layer (see figure 1 below AND PARA.[0044]).
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Since Gong et al. and KUSAI et al. are both from the same field of endeavor, the purpose disclosed by KUSAI et al. would have been recognized in the pertinent art of Gong et al.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Gong et al. to teaching of KUSAI et al. for purpose of using the (n+1)-th electrode layer is included and a resistance is changed in a stepwise maner.
Allowable Subject Matter
Claims 7, 13-16 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 7, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein the memory device is configured to have each of the multi-level resistance states determined by a sum of a first resistance of the self-selecting memory layer and a second resistance of the resistive memory layer in combination with the other limitations thereof as is recited in the claim.
Regarding claim 13, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of determining each of the multi-level resistance states by summing a first resistance of the self-selecting memory layer and a second resistance of the resistive memory layer in combination with the other limitations thereof as is recited in the claim. Claims 14-16 depend on claim 13.
Regarding claim 19, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein each of the multi-level resistance states is based on a sum of a first resistance of the self-selecting memory layer and a second resistance of the resistive memory layer in combination with the other limitations thereof as is recited in the claim.
Conclusion
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/MINH D DINH/
Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827