DETAILED ACTION
Response to Amendment
The Amendment filed January 7, 2026has been entered. Claims 1-20 remain pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 6-8, 10, and 16-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Watanabe (US 2024/0248644).
Regarding claim 1, Watanabe discloses:
A method, comprising:
entering, by a host system, storage access commands (FIG. 2 Step 1. Host stores command in slot of submission queue) in a plurality of submission queues configured in a random access memory (FIG. 1 Submission Queues in RAM 22 of Host 2) accessible to both the host system and a memory sub-system ([0039] In the NVMe interface, communication between the host 2 and the SSD 3 is executed using a pair of queues including at least one submission queue SQ and a completion queue CQ correlated with the at least one submission queue SQ);
providing, by the host system and in association with a submission queue, an identification number of a command entered in the submission queue among the plurality of submission queues (Step 2: Host gets write access to SQ tail doorbell register and updates SQ tail pointer (SQTP));
retrieving, by the memory sub-system, the identification number provided by the host system in association with the submission queue ([0072] The update of the submission queue tail pointer (SQTP) is a trigger for the controller 4 to start the process of each of the commands stored in the submission queue SQ);
determining, by the memory sub-system and based on the identification number, a count of commands in the submission queue ([0072] The value of the submission queue tail pointer (SQTP) is incremented by the number of new commands stored in the submission queue SQ);
identifying, by the memory sub-system and based at least in part on the count, one or more submission queues among the plurality of submission queues ([0073] Step 3: The controller 4 can recognize the number of new commands stored in the submission queue SQ based on a difference between the new value of the submission queue tail pointer (SQTP) and the value of a submission queue head pointer (SQHP)); and
retrieving, by the memory sub-system, a subset of the storage access commands from the one or more submission queues for execution in the memory sub-system (Step 3. Controller fetches command; [0073] The controller 4 fetches any number of one or more commands from the submission queue SQ).
Regarding claim 2, Watanabe further discloses:
The method of claim 1, further comprising:
tracking, by the host system, a respective identification number of each respective command entered into the submission queue by increasing by one an identification number of a command entered into the submission queue before the respective command ([0072] The value of the submission queue tail pointer (SQTP) is incremented by the number of new commands stored in the submission queue SQ).
Regarding claim 6, Watanabe further discloses:
The method of claim 1, wherein the providing of the identification number in association with the submission queue includes the host system writing the identification number in a slot in a status array (Step 2: Host gets write access to SQ tail doorbell register and updates SQ tail pointer (SQTP)); and
wherein the slot is pre-associated with the submission queue among the plurality of submission queues ([0072] host 2 gets write access to a submission queue tail doorbell register in the SSD 3 corresponding to the submission queue SQ, and updates a value of the submission queue tail pointer (SQTP) corresponding to the submission queue SQ).
Regarding claim 7, Watanabe further discloses:
The method of claim 1, wherein the providing of the identification number in association with the submission queue includes the host system writing the identification number and an identification of the submission queue in a register in the memory sub-system (Step 2: Host gets write access to SQ tail doorbell register and updates SQ tail pointer (SQTP)); and
wherein the register has a predetermined address that is independent of the submission queue (FIG. 2 the submissions queues are located in the host and the submission queue tail doorbell register is located in the SSD).
Regarding claim 8, Watanabe further discloses:
The method of claim 1, wherein the providing of the identification number in association with the submission queue includes the host system adding, in a status queue, an entry including the identification number and an identification of the submission queue ([0072] host 2 gets write access to a submission queue tail doorbell register in the SSD 3 corresponding to the submission queue SQ, and updates a value of the submission queue tail pointer (SQTP) corresponding to the submission queue SQ; FIGs. 3B/4 SQ Identification Information; It would be obvious to one skilled in the art before the effective filing date of the claimed invention that the identification of the submission queue is included with the entry identification because the SSD would need to know which queue contained the commands and because the SSD uses this information for arbitration).
Regarding claim 10, Watanabe further discloses:
The method of claim 1, wherein the command is a second command (FIG. 2 the SQTP corresponds to a second command and the SQHP corresponds to a first command);
the identification number of the command is an identification number of the second command (FIG. 2 the SQTP corresponds to a second command and the SQHP corresponds to a first command); and
the method further comprises:
tracking, by the memory sub-system and for the submission queue, an identification number of a first command entered in the submission queue prior to addition of the second command into the submission queue (FIG. 2 SQHP);
wherein the count of commands is based on a difference between the identification number of the first command and the identification number of the second command ([0073] Step 3: The controller 4 can recognize the number of new commands stored in the submission queue SQ based on a difference between the new value of the submission queue tail pointer (SQTP) and the value of a submission queue head pointer (SQHP)).
Regarding claim 16, Watanabe discloses:
A memory sub-system, comprising:
non-volatile memory cells configured to provide a storage capacity of the memory sub-system (FIG. 1 Memory Cell Array 51); and
at least one processor (FIG. 1 CPU 43) configured to:
retrieve, for a submission queue among a plurality of submission queues (FIG. 1 Submission Queues in RAM 22 of Host 2) configured to provide commands from a host system (FIG. 2 Step 1. Host stores command in slot of submission queue) to the memory sub-system ([0039] In the NVMe interface, communication between the host 2 and the SSD 3 is executed using a pair of queues including at least one submission queue SQ and a completion queue CQ correlated with the at least one submission queue SQ), an identification number of a command in the submission queue ([0072] The update of the submission queue tail pointer (SQTP) is a trigger for the controller 4 to start the process of each of the commands stored in the submission queue SQ);
determine, based on the identification number, a count of commands in the submission queue ([0072] The value of the submission queue tail pointer (SQTP) is incremented by the number of new commands stored in the submission queue SQ);
identify, based on the count, one or more submission queues among the plurality of submission queues ([0073] Step 3: The controller 4 can recognize the number of new commands stored in the submission queue SQ based on a difference between the new value of the submission queue tail pointer (SQTP) and the value of a submission queue head pointer (SQHP));
retrieve, from the one or more submission queues, a subset of storage access commands in the plurality of submission queues (Step 3. Controller fetches command; [0073] The controller 4 fetches any number of one or more commands from the submission queue SQ); and
execute commands in the subset (Step 5. Controller executes command).
Regarding claim 17, Watanabe further discloses:
The memory sub-system of claim 16, wherein the command is a second command (FIG. 2 the SQTP corresponds to a second command and the SQHP corresponds to a first command);
the identification number of the command is an identification number of the second command (FIG. 2 the SQTP corresponds to a second command and the SQHP corresponds to a first command); and
the at least one processor is further configured to:
track, by the memory sub-system and for the submission queue, an identification number of a first command entered in the submission queue prior to addition of the second command into the submission queue (FIG. 2 SQHP);
wherein the count of commands is based on a difference between the identification number of the first command and the identification number of the second command ([0073] Step 3: The controller 4 can recognize the number of new commands stored in the submission queue SQ based on a difference between the new value of the submission queue tail pointer (SQTP) and the value of a submission queue head pointer (SQHP)).
Regarding claim 18, Watanabe further discloses:
The memory sub-system of claim 17, wherein the identification number of the second command is retrieved from a slot in a status array (Step 2: Host gets write access to SQ tail doorbell register and updates SQ tail pointer (SQTP)); and
wherein the slot is pre-associated with the submission queue among the plurality of submission queues ([0072] host 2 gets write access to a submission queue tail doorbell register in the SSD 3 corresponding to the submission queue SQ, and updates a value of the submission queue tail pointer (SQTP) corresponding to the submission queue SQ).
Regarding claim 19, Watanabe further discloses:
The memory sub-system of claim 17, further comprising:
a register (FIG. 2 SQ tail doorbell register) having a predetermined address that is independent of the submission queue (FIG. 2 the submissions queues are located in the host and the submission queue tail doorbell register is located in the SSD);
wherein the identification number of the second command is retrieved from the register in response to the host system writing to the predetermined address ([0072] Step 2: To notify the storage of the one or more new commands in the submission queue SQ to the controller 4 of the SSD 3, The host 2 gets write access to a submission queue tail doorbell register in the SSD 3 corresponding to the submission queue SQ, and updates a value of the submission queue tail pointer (SQTP) corresponding to the submission queue SQ. The value of the submission queue tail pointer (SQTP) is incremented by the number of new commands stored in the submission queue SQ. The update of the submission queue tail pointer (SQTP) is a trigger for the controller 4 to start the process of each of the commands stored in the submission queue SQ); and
wherein a content of the register further includes an identification of the submission queue ([0051] When the CPU 43 to be described below fetches a command, the arbitration mechanism selects a submission queue SQ from which a next command is to be fetched from the plurality of submission queues SQ0, SQ1, and . . . of the host 2. Hereinafter, the submission queue SQ from which a next command is to be fetched that is selected by the host I/F 41 is also called a target submission queue SQ; [0072] updates a value of the submission queue tail pointer (SQTP) corresponding to the submission queue SQ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe and Dutta (US 2022/0311716).
Regarding claim 11, Dutta discloses:
A host system, comprising:
a plurality of processor cores (FIG. 1 Cores 111); and
a connection to a memory sub-system (FIG. 1 TCP Connection 130);
wherein each respective processor core among the plurality of processor cores is dedicated a submission queue among a plurality of submission queues (FIG. 1 Send Queues on Host 110) configured to provide commands for execution in the memory sub-system ([0057] the send queue on the host 110 and the receive queue on the controller 121 of the storage element 120 support communications from the host 110 to the storage element 120 (e.g., communicating WRITE commands for writing data 122 to the storage element 120, communicating data being written to the storage element 120, communicating READ commands for requesting data 122 from the storage element 120, and so forth));
wherein the respective processor core is configured to enter storage access commands into the submission queue ([0067] 1. The driver enqueues each new command to the controller into the SQ…Each SQE describes one operation to be performed by the device such as a Read, Write, or Flush), and to provide, in association with the submission queue, an identification number of a command entered at an end in the submission queue ([0068] 2. When new entries are placed on an SQ, the driver informs the controller about the new entries by writing the new tail pointer to the SQ specific hardware doorbell register in the controller. This register is specific to the SQ being updated); and
Dutta does not appear to explicitly teach “wherein the identification number provided in association with the submission queue causes the memory sub-system to determine a count of commands in the submission queue.” However, Watanabe discloses:
wherein the identification number provided in association with the submission queue causes the memory sub-system to determine a count of commands in the submission queue ([0072] The value of the submission queue tail pointer (SQTP) is incremented by the number of new commands stored in the submission queue SQ).
Dutta and Watanabe are analogous art because Dutta and Watanabe teach fetching commands from queues.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Watanabe and Dutta before him/her, to modify the teachings of Dutta with Watanabe's teachings of submission queues because incrementing the submission queue tail pointer by the number of commands place in the corresponding submission queue enables the memory controller to calculate the number of commands that have been added to the corresponding submission queue.
Regarding claim 13, Watanabe further discloses:
The host system of claim 11, wherein the respective processor core is further configured to provide the identification number in association with the submission queue via writing the identification number in a slot in an array of slots (Step 2: Host gets write access to SQ tail doorbell register and updates SQ tail pointer (SQTP)); and
wherein the slot is pre-associated with the submission queue among the plurality of submission queues ([0072] host 2 gets write access to a submission queue tail doorbell register in the SSD 3 corresponding to the submission queue SQ, and updates a value of the submission queue tail pointer (SQTP) corresponding to the submission queue SQ).
Regarding claim 14, Watanabe further discloses:
The host system of claim 11, wherein the respective processor core is further configured to provide the identification number in association with the submission queue via writing the identification number and an identification of the submission queue in a register in the memory sub-system (Step 2: Host gets write access to SQ tail doorbell register and updates SQ tail pointer (SQTP)); and
wherein the register has a predetermined address that is independent of the submission queue (FIG. 2 the submissions queues are located in the host and the submission queue tail doorbell register is located in the SSD).
Allowable Subject Matter
Claims 3-5, 9, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims as discussed in the Non-Final Office Action mailed October 7, 2025.
Response to Arguments
Applicant's arguments filed January 7, 2026 have been fully considered but they are not persuasive. The rejection of claim 1 under 35 U.S.C. 102(a)(1) as unpatentable over Watanabe is determined to be proper and is, therefore, maintained.
Regarding the substance of the examiner’s anticipation rejection as argued on pages 1-4 of the remarks, the requirements for anticipation are discussed in MPEP § 2131, the requirements for giving claims their broadest reasonable interpretation in lights of the specification are discussed in MPEP § 2111, and the requirements for determining the plain meaning of a terms are discussed in MPEP § 2111.01.
Applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references. Applicant argues that Watanabe does not disclose the limitations “identifying, by the memory sub-system and based at least in part on the count, one or more submission queues among the plurality of submission queues; and retrieving, by the memory sub-system, a subset of the storage access commands from the one or more submission queues for execution in the memory sub-system” without pointing to how the cites portions of the reference fail to teach the specific limitations.
The rejection of claim 1 as anticipated over Watanabe is therefore maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRACY A WARREN whose telephone number is (571)270-7288. The examiner can normally be reached M-Th 7:30am-5pm, Alternate F.
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/TRACY A WARREN/Primary Examiner, Art Unit 2137