Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on Nov. 20, 2023. It is noted, however, that applicant has not filed a certified copy of the KR-10-2023-0161506 application as required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 26, 2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. A suggested title would be “Semiconductor Packages with Interconnected Under-Bump Patterns”.
The specification has not been checked to the extent necessary to determine the presence of all
possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant
may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20210398890 A1), hereinafter referred to as “Kim”, in view of Lee et al. (US 20200035589 A1), hereinafter referred to as “Lee”.
Regarding Claim 1, Kim teaches a semiconductor package ([0019] “a semiconductor package 1”; FIG. 1-7, 1), comprising:
a lower redistribution layer ([0020] “a lower redistribution substrate 1000”; FIG. 1, 3-4, 7: 1000);
a first semiconductor chip on the lower redistribution layer ([0049] “the first semiconductor chip 700 may be provided on the lower redistribution substrate 1000”; FIG 1, 3H-J, 4, 7: 700);
a second semiconductor chip on the first semiconductor chip ([0068] “a second semiconductor chip 800”; FIG 1, 4, 7: 800);
bonding pads between the first semiconductor chip and the second semiconductor chip ([0064] “A second bonding pad 620”; FIG 1, 3I-J, 4, 7: 620, 621, 622); and
connection terminals between the bonding pads and the second semiconductor chip ([0069] “The package coupling terminal 808 may be disposed between the first semiconductor package PK1 and the second semiconductor package PK2”; FIG 1, 4, 7: 808),
wherein the bonding pads are connected to one of the connection terminals ([0067] “The fourth metal pattern 622 may be in contact with a package coupling terminal 808”; FIG 1, 4, 7: 620, 622, 808).
Kim does not teach under-bump patterns between the first and second semiconductor chips, and does not teach a first under-bump pattern connected to two of the connection terminals.
Lee teaches a semiconductor chip ([0023] “a semiconductor chip 100”; FIG. 5-7: 100, 100a, 100b) comprising of under-bump patterns connected to two of the connection terminals ([0061] “a first UBM layer 160 may include a plurality of pad connection portions 161 to which a plurality of first connection bumps 171 are attached”; FIG. 5-7: 160, 161, 163).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add UBMs to the bonding pads of Kim. As is known in the art, adding a UBM to any bump-connecting structure improves connection and reliability. One of ordinary skill in the art can easily implement a UBM on top of a bonding pad, resulting in the obvious improvement to the semiconductor package.
Further, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the above modified Kim with the interconnection structure of Lee. The UBMs of the claimed invention and the interconnect structure of Lee serve the same purpose of assisting in making semiconductor packages smaller but still reliable (Lee [0003] “Nowadays, as semiconductor chips and semiconductor packages are gradually miniaturized and thinned according to the recent trend of light and thinner electronic devices, the effect of stress acting on the semiconductor chips or semiconductor packages may be gradually increasing and the reliability of the semiconductor chips or semiconductor packages may be gradually decreasing.”). Both components share the purpose of transferring signals, voltages, or ground between elements of the packages/chips (Lee [0051] “the plurality of first connection bumps 171, the first UBM layer 160 … may be electrically connected to one another… may be electrically grounded”), and replacing the UBMs of modified Kim with the structure of Lee to better suit a smaller embodiment would be obvious and result in the expected results of higher efficiency and reliability.
Regarding Claim 2, Kim in view of Lee teaches the semiconductor package of Claim 1.
Kim does not teach the first under-bump pattern comprising pad portions and an interconnection portion connecting the pad portions.
Lee teaches the first under-bump pattern comprising pad portions and an interconnection portion connecting the pad portions ([0061] “The bridge portion 163 may extend between the plurality of pad connection portions 161 to be connected to each of the plurality of pad connection portions 161”; FIG. 5-7: 161, 163).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package described in Kim in view of Lee because of the reasoning described in Claim 1.
Regarding Claim 3, Kim in view of Lee teaches the semiconductor package of claim 2.
Kim does not teach the pad portions respectively overlapped with the two of the connection terminals connected to the first under-bump pattern.
Lee teaches the pad portions respectively overlapped with the two of the connection terminals connected to the first under-bump pattern ([0061] “a first UBM layer 160 may include a plurality of pad connection portions 161 to which a plurality of first connection bumps 171 are attached”; FIG 5-7: 161, 171).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package described in Kim in view of Lee because of the reasoning described in Claim 1.
Regarding Claim 4, Kim in view of Lee teaches the semiconductor package of claim 1. Kim further teaches:
a conductive pillar on the lower redistribution layer and horizontally spaced apart from the first semiconductor chip ([0052] “The conductive pillar 930 may be laterally spaced apart from the first semiconductor chip 700”; FIG 1, 3H-J, 4: 930),
wherein the under-bump patterns and the lower redistribution layer are electrically connected to each other through the conductive pillar ([0052] “The conductive pillar 930 may be in contact with the top surface of the third interconnection portion L3 of at least one of the third redistribution patterns 310”, [0070] “The package coupling terminal 808 may be electrically connected to the second bonding pad 620 and the metal pad 817. Thus, the second semiconductor package PK2 may be electrically connected to the first semiconductor chip 700 and the outer coupling terminal 908 through the upper redistribution substrate 2000, the package coupling terminal 808, and the conductive pillar 930.”; FIG 1, H-J, 4: 930, L3, 808, 817).
Regarding Claim 5, Kim in view of Lee teaches the semiconductor package of claim 1.
Kim does not explicitly teach the connection terminals being two-dimensionally arranged such as to be spaced apart from each other in a first direction and a second direction that cross each other, and
the connection terminals, which are connected to the first under-bump pattern, being adjacent to each other in the first direction or the second direction.
Lee teaches the connection terminals being two-dimensionally spaced apart in two directions and the connection terminals connected under the first under-bump pattern being adjacent in a direction ([0024] “The plurality of connection bumps may be arranged in the form of a two-dimensional array on the bottom surface of the semiconductor chip 100.”; FIG 1, 3, 5, 8: 171, 173).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package described in Kim in view of Lee because of the reasoning described in Claim 1.
Regarding Claim 6, Kim in view of Lee teaches the semiconductor package of claim 1.
Kim does not explicitly teach the second under-bump pattern configured to receive an input/output signal of the second semiconductor chip.
Lee teaches the under-bump pattern configured to receive a data input/output signal ([0025] “The plurality of second connection bumps 173 may include terminals configured to receive a data input/output signal, a driving voltage, and/or a ground voltage from an external device.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package described in Kim in view of Lee because of the reasoning described in Claim 1.
Regarding Claim 7, Kim in view of Lee teaches the semiconductor package of claim 1. Kim further teaches the first semiconductor chip comprising a logic chip ([0049] “The first semiconductor chip 700 may be, for example, a logic chip.”), and
the second semiconductor chip comprising a memory chip ([0068] “the second semiconductor chip 800 may be a memory chip”).
Regarding Claim 8, Kim in view of Lee teaches the semiconductor package of claim 1. Kim further teaches upper redistribution patterns between the first semiconductor chip and the under bump patterns and connected to the under-bump patterns ([0020] “an upper redistribution substrate 2000”; FIG 1, 3I-J, 4, 7: 2000), and
an upper insulating pattern on the upper redistribution pattern on the upper redistribution patterns ([0060] “The fourth redistribution layer 400 may include fourth redistribution patterns 410 and a fourth insulating layer 420. The fifth redistribution layer 500 may include fifth redistribution patterns 510 and a fifth insulating layer 520.”; FIG 1, 3I-J, 4, 7: 520).
Regarding Claim 9, Kim in view of Lee teaches the semiconductor package of claim 8.
Kim does not teach the interconnection portion of the first under-bump pattern on the upper insulating pattern.
Lee teaches the bridge portion of the UBM on the insulating pattern (FIG 6-7: 163, 153).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package described in Kim in view of Lee because of the reasoning described in Claim 1.
Regarding Claim 10, Kim in view of Lee teaches the semiconductor package of claim 8. Kim further teaches the vertical thickness of the upper insulating pattern being 10 μm ([0058] “A thickness H2 of the upper redistribution substrate 2000 may range from about 10 to 60 μm.”)
Regarding Claim 11, Kim teaches a semiconductor package ([0019] “a semiconductor package 1”; FIG. 1-7, 1), comprising:
a lower redistribution layer ([0020] “a lower redistribution substrate 1000”; FIG. 1, 3-4, 7: 1000) comprising lower redistribution patterns stacked in a vertical direction ([0021] “The lower redistribution substrate 1000 may include a first protection layer 20, a first redistribution layer 100, a second redistribution layer 200, and a third redistribution layer 300, which are sequentially stacked.”; FIG 1, 3-4, 7: 1000, 100, 200, 300);
a first semiconductor chip on the lower redistribution layer ([0049] “the first semiconductor chip 700 may be provided on the lower redistribution substrate 1000”; FIG 1, 3H-J, 4, 7: 700);
a mold layer on the lower redistribution layer and covering the first semiconductor chip ([0054] “The first molding member 950 may be formed on the lower redistribution substrate 1000 to cover the lower redistribution substrate 1000 … The first molding member 950 may also cover top and side surfaces of the first semiconductor chip 700.”; FIG 1, 3I-J, 4, 7: 950);
an upper redistribution layer on the mold layer ([0056] “The upper redistribution substrate 2000 may be disposed on a top surface of the first molding member 950”; FIG 1, 3I-J, 4, 7: 2000);
and connection terminals on the upper redistribution layer ([0070] “The package coupling terminal 808 may be electrically connected to the second bonding pad 620…Thus, the second semiconductor package PK2 may be electrically connected … through the upper redistribution substrate 2000, the package coupling terminal 808”; FIG 1, 4, 7: 808),
wherein the upper redistribution layer comprises:
a first upper insulating pattern on a top surface of the mold layer ([0060] “The fourth redistribution layer 400 may include fourth redistribution patterns 410 and a fourth insulating layer 420.”; FIG 1, 3I-J, 4, 7: 410, 420);
a second upper insulating pattern in contact with the first upper insulating pattern ([0060] “The fifth redistribution layer 500 may include fifth redistribution patterns 510 and a fifth insulating layer 520.”; FIG 1, 3I-J 4, 7: 520);
upper redistribution patterns between the first upper insulating pattern and the second upper insulating pattern ([0060] “The fifth redistribution layer 500 may include fifth redistribution patterns 510 and a fifth insulating layer 520.”; FIG 1, 3I-J 4, 7: 510); and
bonding pads that penetrate the second upper insulating pattern and connect to the upper redistribution patterns ([0066] “The second bonding pad 620 may include a third metal pattern 621 and a fourth metal pattern 622… The third metal pattern 621 may be in contact with the fifth interconnection portion L5 of the fifth redistribution pattern 510… The fifth insulating layer 520 may be provided to cover an edge portion of a top surface of the second bonding pad 620 and to not cover a center portion of the second bonding pad 620.”; FIG 1, 3I-J, 4, 7: 620, 621, 622).
Kim does not teach under-bump patterns, wherein at least one of the under-bump patterns is connected to at least two of the connection terminals.
Lee teaches a semiconductor chip ([0023] “a semiconductor chip 100”; FIG. 5-7: 100, 100a, 100b) comprising of under-bump patterns connected to at least two of the connection terminals ([0061] “a first UBM layer 160 may include a plurality of pad connection portions 161 to which a plurality of first connection bumps 171 are attached”; FIG. 5-7: 160, 161, 163).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package described in Kim in view of Lee because of the reasoning described in Claim 1.
Regarding Claim 12, Kim in view of Lee teaches the semiconductor package of claim 11.
Kim does not teach the under-bum patterns connected to at least two of the connection terminals comprising of pad portions vertically overlapped with the connection terminals and at least one interconnection portion between the pad portions.
Lee teaches the first under-bump pattern comprising pad portions and an interconnection portion connecting the pad portions ([0061] “The bridge portion 163 may extend between the plurality of pad connection portions 161 to be connected to each of the plurality of pad connection portions 161”; FIG. 5-7: 161, 163), and the pad portions respectively overlapped with the two of the connection terminals connected to the first under-bump pattern ([0061] “a first UBM layer 160 may include a plurality of pad connection portions 161 to which a plurality of first connection bumps 171 are attached”; FIG 5-7: 161, 171).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package described in Kim in view of Lee because of the reasoning described in Claim 1.
Regarding Claim 13, Kim in view of Lee teaches the semiconductor package of claim 11. Kim further teaches the top surfaces of the under-bump patterns being coplanar with bottom surfaces of the under-bump patterns ([0066] “The third metal pattern 621 may be in contact with the fifth interconnection portion L5 of the fifth redistribution pattern 510, without any via interposed therebetween.” FIG 1, 3I-J, 4, 7: 621, 510).
Regarding Claim 14, Kim in view of Lee teaches the semiconductor package of claim 11.
Kim does not explicitly teach the under-bump patterns comprising of a seed/barrier pattern and a conductive pattern on the seed/barrier pattern.
Lee teaches an under-bump pattern comprising of a seed pattern and a copper pattern on the seed/barrier pattern ([0052] “For example, the first UBM layer 160 may include a first metal layer, a second metal layer, and a third metal layer sequentially stacked in the vertical direction (Z direction)… The second metal layer may be a seed layer for forming a third metal layer. The second metal layer may include, for example, at least one material selected from Ni and Cu. The third metal layer is a plating layer formed using the second metal layer as a seed, and may include Cu.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package described in Kim in view of Lee because of the reasoning described in Claim 1.
Regarding Claim 15, Kim in view of Lee teaches the semiconductor package of claim 11. Kim further teaches a connection substrate that is on the lower redistribution layer and includes an opening ([0111] “The connection substrate 901 may have a hole 990, which is provided to penetrate the same.”; FIG. 7: 901, 990),
wherein the first semiconductor chip is in the opening ([0111] “The first semiconductor chip 700 may be provided in the hole 990”; FIG 7: 990, 700).
Regarding Claim 16, Kim teaches a semiconductor package ([0019] “a semiconductor package 1”; FIG. 1-7, 1), comprising:
a lower redistribution layer ([0020] “a lower redistribution substrate 1000”; FIG. 1, 3-4, 7: 1000) comprising lower redistribution patterns stacked in a vertical direction ([0021] “The lower redistribution substrate 1000 may include a first protection layer 20, a first redistribution layer 100, a second redistribution layer 200, and a third redistribution layer 300, which are sequentially stacked.”; FIG 1, 3-4, 7: 1000, 100, 200, 300);
a first semiconductor chip on the lower redistribution layer ([0049] “the first semiconductor chip 700 may be provided on the lower redistribution substrate 1000”; FIG 1, 3H-J, 4, 7: 700);
a connection structure on the lower redistribution layer and horizontally spaced apart from the first semiconductor chip ([0111] “The connection substrate 901 may have a hole 990, which is provided to penetrate the same.”; FIG. 7: 901, 990);
an upper redistribution layer on the first semiconductor chip and the connection structure ([0119] “The upper redistribution substrate 2000 may be provided on the top surface of the first molding member 950.”; FIG. 7: 2000), the upper redistribution layer comprising bonding pads ([0120] “The second bonding pad 620”; FIG 7: 620);
a second semiconductor chip on the upper redistribution layer (FIG. 7: 800); and
connection terminals between the upper redistribution layer and the second semiconductor chip ([0120] “the package coupling terminal 808”; FIG. 7: 808),
wherein the upper distribution layer comprises upper redistribution patterns ([0060] “The fourth redistribution layer 400 may include fourth redistribution patterns 410 and a fourth insulating layer 420. The fifth redistribution layer 500 may include fifth redistribution patterns 510 and a fifth insulating layer 520.”; FIG 1, 3I-J, 4, 7: 410, 420, 510, 520), that are connected to the bonding pads ([0066] “The second bonding pad 620 may include a third metal pattern 621 and a fourth metal pattern 622… The third metal pattern 621 may be in contact with the fifth interconnection portion L5 of the fifth redistribution pattern 510… The fifth insulating layer 520 may be provided to cover an edge portion of a top surface of the second bonding pad 620 and to not cover a center portion of the second bonding pad 620.”; FIG 1, 3I-J, 4, 7: 620, 621, 622), and an upper insulating pattern, that is on the upper redistribution pattern ([0060] “The fifth redistribution layer 500 may include fifth redistribution patterns 510 and a fifth insulating layer 520.”; FIG 1, 3I-3J, 4, 7, 510, 520).
Kim does not teach the connection terminals being two-dimensionally arranged, when viewed in a plan view,
nor does it teach under-bump patterns comprising:
a first under-bump pattern connected to at least two of the connection terminals, the first under-bum pattern comprising pad portions and an interconnection portion between the pad portions; and
a second under-bump pattern connected to one of the connection terminals, wherein the interconnection portion of the first under-bump pattern is on the upper insulating pattern.
Lee teaches a semiconductor chip ([0023] “a semiconductor chip 100”; FIG. 5-7: 100, 100a, 100b) comprising:
connection terminals being two-dimensionally spaced apart in two directions ([0024] “The plurality of connection bumps may be arranged in the form of a two-dimensional array on the bottom surface of the semiconductor chip 100.”; FIG 1, 3, 5, 8: 171, 173), and
under-bump patterns comprising:
a first under-bump pattern connected to at least two of the connection terminals ([0061] “a first UBM layer 160 may include a plurality of pad connection portions 161 to which a plurality of first connection bumps 171 are attached”; FIG. 5-7: 160, 161, 163), the first under-bum pattern comprising pad portions and an interconnection portion between the pad portions ([0061] “The bridge portion 163 may extend between the plurality of pad connection portions 161 to be connected to each of the plurality of pad connection portions 161”; FIG. 5-7: 161, 163);
and a second under-bump pattern connected to one of the connection terminals ([0029] “and a second UBM layer 165 to which a plurality of second connection bumps 173 are attached.”; FIG. 5-7: 165, 173),
wherein the interconnection portion of the first under-bump pattern is on the upper insulating pattern (FIG 6-7: 163, 153).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package described in Kim in view of Lee because of the reasoning described in Claim 1.
Regarding Claim 17, Kim in view of Lee teaches the semiconductor package of claim 16.
Kim does not teach the first under-bump pattern being configured to receive a power or ground voltage of the second semiconductor chip, and
the second under-bump pattern being configured to receive an input/output signal of the second semiconductor chip.
Lee teaches the first under-bump pattern configured to receive a ground voltage ([0025] “the plurality of first connection bumps 171 may be configured to receive a ground voltage from an external device”), and
the second under-bump pattern configured to receive an input/output signal ([0025] “The plurality of second connection bumps 173 may include terminals configured to receive a data input/output signal, a driving voltage, and/or a ground voltage from an external device.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package described in Kim in view of Lee because of the reasoning described in Claim 1.
Regarding Claim 18, Kim in view of Lee teaches the semiconductor package of claim 16.
Kim further teaches a thickness of the lower distribution layer being larger than a thickness of the upper redistribution layer. ([0023] “A thickness H1 of the lower redistribution substrate 1000 in the second direction D2 may range from about 40 μm to 60 μm.”, [0058] “A thickness H2 of the upper redistribution substrate 2000 may range from about 10 to 60 μm.”; FIG 1: H1, H2).
Regarding Claim 19, Kim in view of Lee teaches the semiconductor package of claim 16.
Kim does not teach the first under-bump pattern comprising an additional interconnection portion between the pad portions.
While Lee does not explicitly teach multiple distinct interconnection portions, it does teach 3 different pad portions all interconnected through one interconnection portion.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the under-bump patterns of the Kim in view of Lee in a way that contains multiple interconnections. The pad portions and the under-bump patterns consist of the same material and are only distinguished by imaginary lines drawn across the structure. Configuring the structure in the claimed invention has no additional benefit or rational compared to configuring it in the way described in Lee. One can additionally break apart the bridge structure described in Lee into two or more parts (see annotated Fig. 5: 163a & 163b).
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Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lee as applied to claim 16 above, and further in view of Choi et al. (US 20220037261 A1), hereinafter referred to as Choi.
Regarding Claim 20, Kim in view of Lee teaches the semiconductor package of claim 16.
Kim does not teach the package further comprising a memory structure that is horizontally spaced apart from the first semiconductor chip and the second semiconductor chip, wherein the memory structure comprises memory chips stacked in the vertical direction.
Choi does teach a semiconductor package ([0115] “a semiconductor package 600”; FIG. 19-20: 4) further comprising a memory structure that is horizontally spaced apart from the first semiconductor chip,
wherein the memory structure comprises memory chips stacked in the vertical direction ([0118] “The second semiconductor chips 200 may be disposed on the redistribution substrate 300 to be spaced apart from the first semiconductor chip 100. Each of the second semiconductor chips 200 may include a plurality of memory chips 210, which are vertically stacked.”; FIG. 19-20: 200, 210).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package described in Kim in view of Lee such that the package also consists of a spaced apart memory structure consisting of stacks of memory chips, as described in Choi. Although the chip 100 in Choi is only considered a single chip, it would have been obvious to replace it with the more elaborate chip setup described in Kim in view of Lee, as the connection points are the same ([0119] “The first and second semiconductor chips 100 and 200 may be connected to the redistribution substrate 300 through the first connection terminals 150.”; FIG 20: 100, 150), and both the semiconductor package of Kim in view of Lee and the semiconductor chip 100 of Choi may serve as logic chips (Kim [0049] “The first semiconductor chip 700 may be, for example, a logic chip., [0068] “In an embodiment, the second semiconductor chip 800 may be a memory chip”; Choi [0117] “The first semiconductor chip 100 may be a micro electro mechanical systems (MEMS) device, an optoelectronic device, or a logic chip including processors (e.g., a central processing unit (CPU), a graphic processing unit (GPU), a mobile application chip, or a digital signal processor (DSP))”). As known in the art, a semiconductor package comprising of the logic chip and memory chip of Kim may be collectively substitute a logic chip.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Suk et al. (US 20220077048 A1), Lee et al. (US 20220310577 A1), Kim et al. (US 20220310496 A1), Hwang et al. (US 20220375829 A1), and Choi et al. (US 20220384324 A1) are cited to teach structurally similar semiconductor packages and manufacturing methods, relevant to claims 1-20 of the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW SHEN whose telephone number is (571)272-0642. The examiner can normally be reached M-Th 0730-1730.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MATTHEW L SHEN/ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights