DETAILED ACTION
Claim Objections
1. Claim 1 is objected to because of the following informalities: claim 1, line 7, recites: “adjacent second semiconductor layers” which should be changed to “adjacent the second semiconductor layers” because “second semiconductor layers” have been referred to earlier in the claim.
Appropriate correction is required.
Double Patenting
2. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/forms/. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
3. Claims 1-3, 6 and 8-14 are provisionally rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-3 and 8-15 of copending Application No. 18/799,397 (published as U.S. Patent Application Publication 2026/0047056 A1). Although the conflicting claims are not identical, they are not patentably distinct from each other because said claims of the above-identified copending Application recite all limitations of said claims of the present invention. Specifically, the conflicting claims are listed below:
Application Claims
Patent Claims
1. A method, comprising:
1. A method, comprising:
forming a multi-layer stack over a substrate, the multi-layer stack comprising alternating layers of first semiconductor layers and second semiconductor layers;
forming a multi-layer stack over a substrate, the multi-layer stack comprising alternating layers of first semiconductor layers and second semiconductor layers;
removing the first semiconductor layers in a first region of the substrate;
removing the first semiconductor layers in a first region of the substrate;
forming a disposable material between the second semiconductor layers in the first region;
forming a disposable material between the second semiconductor layers in the first region;
forming source/drain regions adjacent (the)second semiconductor layers and the disposable material in the first region; and
forming source/drain regions adjacent second semiconductor layers and the disposable material in the first region; and
replacing the disposable material in the first region with metal gate structures.
replacing the disposable material in the first region with metal gate structures, each of the second semiconductor layers having a different thickness.
2. The method of claim 1, wherein the disposable material is selected from the group consisting of silicon oxide, silicon oxynitride, and aluminum oxide.
2. The method of claim 1, wherein the disposable material is selected from a group consisting of silicon oxide, silicon oxynitride, and aluminum oxide.
3. The method of claim 1, further comprising:
3. The method of claim 1, further comprising:
performing an ion implantation process to introduce n-type dopants into the source/drain regions after forming the disposable material between the second semiconductor layers.
performing an ion implantation process to introduce n-type dopants into the source/drain regions after forming the disposable material between the second semiconductor layers.
Application Claims
Patent Claims
6. The method of claim 1, wherein replacing the disposable material in the first region with metal gate structures further comprises:
8. The method of claim 1, wherein replacing the disposable material in the first region with metal gate structures further comprises:
removing the disposable material using an etching process that is selective to the disposable material over the second semiconductor layers.
removing the disposable material using an etching process that is selective to the disposable material over the second semiconductor layers.
8. The method of claim 1, further comprising:
9. The method of claim 1, further comprising:
forming inner spacers on sidewalls of the disposable material before forming the source/drain regions.
forming inner spacers on sidewalls of the disposable material before forming the source/drain regions.
9. The method of claim 8, wherein the inner spacers comprise silicon nitride, silicon oxynitride, or a combination thereof.
10. The method of claim 9, wherein the inner spacers comprise silicon nitride, silicon oxynitride, or a combination thereof.
10. The method of claim 8, wherein the inner spacers have a convex shape facing the disposable material.
11. The method of claim 9, wherein the inner spacers have a convex shape facing the disposable material.
11. The method of claim 1 further comprising:
12. The method of claim 1 further comprising:
replacing the second semiconductor layers with metal gate structures in a second region of the substrate.
replacing the second semiconductor layers with metal gate structures in a second region of the substrate.
Application Claims
Patent Claims
12. A method, comprising:
13. A method, comprising:
forming fins of a multi-layer stack over a substrate, the multi-layer stack including alternating layers of first semiconductor layers and second semiconductor layers;
forming fins of a multi-layer stack over a substrate, the multi-layer stack including alternating layers of first semiconductor layers and second semiconductor layers;
forming first gate structures over the fins;
forming first gate structures over the fins;
etching first recesses into the fins in a first region and a second region of the substrate;
etching first recesses into the fins in a first region and a second region of the substrate;
in the first region of the substrate, removing the first semiconductor layers and forming a disposable material between the second semiconductor layers;
in the first region of the substrate, removing the first semiconductor layers and forming a disposable material between the second semiconductor layers;
forming source/drain regions in the first recesses adjacent to the disposable material and the second semiconductor layers in the first region and adjacent to the first semiconductor layers and the second semiconductor layers in the second region;
forming source/drain regions in the first recesses adjacent to the disposable material and the second semiconductor layers in the first region and adjacent to the first semiconductor layers and the second semiconductor layers in the second region;
replacing the first gate structures and the disposable material in the first region with a first set of metal gate structures; and
replacing the first gate structures and the disposable material in the first region with a first set of metal gate structures, the second semiconductor layers comprising a top layer and a bottom layer in the first region, the top layer having a different thickness than the bottom layer; and
replacing the first gate structures and the first semiconductor layers in the second region with a second set of metal gate structures.
replacing the first gate structures and the first semiconductor layers in the second region with a second set of metal gate structures.
13. The method of claim 12, wherein the first set of metal gate structures is for n-type nano-FETs and the second set of metal gate structures is for p-type nano-FETs.
14. The method of claim 13, wherein the first set of metal gate structures is for n-type nano-FETs and the second set of metal gate structures is for p-type nano-FETs.
14. The method of claim 12, wherein the disposable material is selected from the group consisting of silicon oxide, silicon oxynitride, and aluminum oxide.
15. The method of claim 13, wherein the disposable material is selected from a group consisting of silicon oxide, silicon oxynitride, and aluminum oxide.
This is a provisional obviousness-type double patenting rejection because the conflicting claims have not in fact been patented.
4. Claims 4-5, 7, and 15-17 are provisionally rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 3, 6 and 12 of copending Application No. 18/799,397 (published as U.S. Patent Application Publication 2026/0047056 A1) in view of Hashemi et al. U.S. Patent Application Publication 2025/0267899 A1.
Referring to claim 4, patent claim 3 recites performing an ion implantation process to introduce n-type dopants into the source/drain regions as detailed above for claim 3, but does not recite that the ion implantation process introduces dopants comprising phosphorus, arsenic, antimony, or a combination thereof.
Hashemi, in disclosing a method including performing an ion implantation process to introduce n-type dopants into source/drain regions, discloses that the ion implantation process introduces dopants comprising phosphorus, arsenic, antimony, or a combination thereof (para [103] (paragraph(s) [0103])), thereby teaching that phosphorus, arsenic, antimony, and a combination thereof are suitable dopants into source/drain regions.
Furthermore, referring to claim 5, although Hashemi does not teach temperature as claimed (wherein the ion implantation process is performed at a temperature range from −300° C. to 30° C), Hashemi teaches that the ion implantation performed at a certain suitable temperature range (“annealing”, para [27]).
Referring to claim 7, patent claim 6 recites replacing the disposable material in the first region with metal gate structures as detailed above, but does not recite replacing the disposable material in the first region with metal gate structures comprises depositing a gate dielectric layer on the second semiconductor layers, and forming a gate electrode material on the gate dielectric layer.
Hashemi, in disclosing a method comprising replacing a disposable material in a first region with metal gate structures (144, Fig. 21), teaches replacing the disposable material (sacrificial nanolayers 106, Fig. 12, para [51]) in the first region with metal gate structures comprises depositing a gate dielectric layer (a, high-k layer, para [90]) on second semiconductor layers (170, Fig. 21), and forming a gate electrode material (work function gate material, para [91]) on the gate dielectric layer (Fig. 21), for forming a working replacement gate.
Referring to claims 15-17, patent claim 12 recites forming source/drain regions as detailed above, but does not recite (claim 15) performing an ion implantation process to introduce n-type dopants into the source/drain regions in the first region after forming the disposable material between the second semiconductor layers, (claim 16) wherein the source/drain regions include materials exerting a tensile strain on the second semiconductor layers in the first region, and (claim 17) wherein the source/drain regions include materials exerting a compressive strain on the first semiconductor layers in the second region.
Hashemi, in disclosing a method comprising forming source/drain regions (134, Fig. 21), discloses performing an ion implantation process to introduce n-type dopants into the source/drain regions (para [103]), wherein the source/drain regions include materials exerting a tensile strain or a compressive strain on a semiconductor channel layer (para [35]: “increase the effectiveness of applied strain from the source/drain region 134 to the channel 170”, para [39]: relaxed or compressively strained), thereby teaching a method for introduction strain to channels of transistors.
This is a provisional obviousness-type double patenting rejection because the conflicting claims have not in fact been patented.
Allowable Subject Matter
5. Claims 18-20 are allowable over the prior art of record.
The following is an examiner's statement of reasons for allowance: The prior art of record fails to teach or render obvious a method with all limitations as recited in claim 18, which may be characterized in etching first recesses into the fins, in removing the first semiconductor layers from the fins, forming an oxide material between the second semiconductor layers and in the first recesses, recessing sidewalls of the oxide material in the first recesses to form second recesses between adjacent second semiconductor layers, in forming inner spacers on the recessed sidewalls of the oxide material, and in forming source/drain regions in the first recesses adjacent to the inner spacers and the second semiconductor layers.
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
09-22-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818
