Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Papers submitted under 35 U.S.C. 119(a)-(d) have been placed of record in the file.
2. Claims 1-19 and 21 are presented for examination.
Claim Rejections - 35 USC § 102
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
5. Claims 1-7 and 13-19 and 21 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Tsukada et la.US Pub. No. 20160049180.
As per claims 1, 13, 17 and 19, Figs. 1 and 8 of Tsukada is directed to an electronic system (Figl. 8) comprising: a main processor (4, Fig. 8, par. 16) configured to control the electronic system; and a storage device (11, Fig. 1 or 10A, Fig. 8) configured to store data, wherein the storage device includes a calibration circuit (50) configured to: generate a first ZQ code (ZQC) corresponding to a first reference (AQVREF, par. 37) voltage based on a resistance value (RZQ) and the first reference voltage, and generate a second ZQ code (ZQCODE2, par. 93) corresponding to a second reference voltage (generated by Fig. 6 or Fig. 4 and 5) based on the first ZQ code.
As per claims 2, 16 and 21, Figs. 3 -5 of Tsukada disclose wherein the code conversion circuit is configured to generate the second ZQ code based on a ratio of a first current level (PU or PD, par. 57 or 61) of the driver circuit and a second current level (PU or PD, par. 57 or 61) of the driver circuit, wherein the first current level is a current level of the driver circuit when an output voltage (DQ) of the driver circuit is the first reference voltage (Fig. 4 or 5), and wherein the second current level is a current level (Fig. 4 or 5) of the driver circuit when the output voltage of the driver circuit is the second reference voltage.
As per claim 3, a claim 10 of Tsukada discloses wherein the first ZQ code and the second ZQ code are binary codes with the same number of digits.
As per claims 4 and 18, Fig. 4-6 of Tsukada disclose wherein the code conversion circuit is further configured to: based on the first ZQ code, generate a third ZQ code corresponding to a third reference voltage different from the first reference voltage and the second reference voltage, wherein the first reference voltage, the second reference voltage, and the third reference voltage range between a power supply voltage (VDDQ, Fig. 4) of the memory device and a ground voltage (VSSQ, Fig. 1).
As per claims 5 and 14, Fig. 6 of Tsukada discloses wherein a first pull-up code for impedance matching of the pull-up driver (Fig. 6) is included in the first ZQ code, wherein the memory device comprises a pull-up calibration circuit (51) configured to generate the first pull-up code (CODPU, PAR. 67), wherein the resistance value(RZQ) is a value of a resistor (RZq), wherein the pull-up calibration circuit includes: a first comparator (54, par. 67) configured to compare (i) a voltage level of a ZQ node (ZQ, par. 67) connected to the resistor and (ii) the first reference voltage, to generate a first comparison output (CODEPU updated, par. 67); a pull-up control circuit (51) configured to generate a pull-up control signal based on the first comparison output; and a pull-up calibration circuit configured to generate a pull-up signal (CODEPU, par. 67) in response to the pull-up control signal and to provide the pull-up signal to the ZQ node, and wherein the first pull-up code is a pull-up control signal corresponding to a case where the voltage level of the ZQ node matches (equal, par. 67) the first reference voltage .
As per claims 6-7 and 15, Fig. 6 of Tsukada discloses wherein a first pull-down code for impedance matching of the pull-down driver (Fig. 6) is included in the first ZQ code, wherein the memory device comprises a pull-down calibration circuit (53) , wherein the pull-down calibration circuit and the driver circuit are configured to generate the first pull-down code (DODEPD), wherein the resistance value is a value of a resistor (RZQ, par. 68), wherein the pull-down calibration circuit includes: a second comparator (55, par. 68) configured to compare (i) an output voltage level of an output terminal (N) of the driver circuit and (ii) the first reference voltage, to generate a second comparison output; and a pull-down control circuit configured to generate a pull-down control signal based on the second comparison output (CODEPD, par. 68) and to provide the pull-down control signal to the driver circuit, and wherein the first pull-down code is a pull-down control signal corresponding to a case where the output voltage level matches (equal, par. 68) the first reference voltage.
5. The prior art made of record and not relied upon is considered pertinent to applicants’ disclosure. Note the additional references cited on the attached PTO-892 form which show further examples of a ZQ calibration.
Allowable Subject matter
6. Claims 8-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
7. The following is a statement of reasons for the indication of allowable subject matter:
Claims include allowable subject matter since the prior art made of record and considered pertinent to the applicants’ disclosure, taken individually or in combination, does not teach or suggest the claimed invention having wherein the first ZQ code and the second ZQ code are binary codes with the same number of digits, wherein the code conversion circuit includes a code converter, wherein the code converter includes: a converter control circuit configured to control the generation of the second ZQ code based on the first ZQ code and to generate a first modified code by padding the first ZQ code; shift registers configured to generate second modified codes by performing bit shifting with respect to the first modified code; and adders configured to generate a third modified code by adding the second modified codes, and wherein the code conversion circuit is configured to generate the second ZQ code based on the third modified code in claim 8.
8. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
9. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hoai V. Ho whose telephone number is (571) 272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Monday through Thursday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
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/HOAI V HO/Primary Examiner, Art Unit 2827