DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123.
Claim Status
Claims 1-20 are currently pending. Claim 10 is amended as per Applicant’s amendment filed on 05 June 2026.
Response to Arguments
Applicant's arguments filed 05 June 2026 with regards to claim 10 have been fully considered and are persuasive.
As no arguments or amendments are made regarding the remaining claims, their rejections are maintained.
Allowable Subject Matter
Claims 1-17 are allowed.
The following is an examiner’s statement of reasons for allowance: the prior art made of record teaches a method and memory subsystem for scalable queue processing but fails to teach the combination including the limitations of:
(Claim(s) 1) “determining, by the memory sub-system, priorities of the submission queues based on the analyzing the queue statuses that are obtained without accessing the submission queues and configured to provide information about commands to be retrieved from the submission queues for execution; selecting, by the memory sub-system, one or more submission queues based the priorities determined based on the analyzing of the queue statuses; retrieving, by the memory sub-system and from the one or more submission queues selected based on the priorities determined based on the analyzing of the queue statuses, a subset of storage access commands in the plurality of submission queues; and executing, by the memory sub-system, the subset of storage access commands”
Claims 10 have analogous limitations as independent claim 1 and are allowable for the same reasons as noted supra.
As dependent claims 2-9 and 11-17 depend from an allowable base claim; they are at least allowable for the same reasons as noted supra. Support for the above noted limitations can be found in at least paragraphs [0028-0034, 0064-0076, Figs. 6, 12] of Applicant' s specification.
The prior art made of record, Horspool (US 20220261183 A1), neither anticipates nor renders obvious the above recited combinations for at least the reasons specified.
The prior art made of record, on the 892 and/or 1449 forms, in the case does not fairly teach or suggest the claimed limitations, nor does it render the claimed invention obvious.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 18-20 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Horspool (US 20220261183 A1).
Referring to claims 18, Horspool teaches
A non-transitory computer storage medium storing instructions which, when executed in a memory sub-system, cause the memory sub-system to perform a method, comprising: analyzing, by the memory sub-system, queue statuses of a plurality of submission queues without accessing the submission queues; ([Horspool 0003, 0029-0030, 0036, 0042-0043] The NVMe controller 132 comprises a core (or processor) that utilizes a high priority command queue 412 (hereinafter “HPQ”) and a low priority command queue 414 (hereinafter “LPQ”) for further processing of commands received from the host 110. The read performance and read data latency (i.e. the time from the command being added to the submission queue to the time the data is returned to the host memory and the command status is added to the completion queue) are critical elements for the operation of the SSD. A queue group may comprise one or more submission queues 221-225 and a completion queue 226-229. Associated with each queue 221-229 there is a hardware doorbell register to facilitate the signaling of incoming commands and outgoing completion notifications from and to the host 110. When the SSD 120 completes processing of a command, it inserts an entry on a completion queue of a specific queue group 211-214 (that has been previously associated with the submission queue of the same queue group from which the command was initially retrieved by the SSD 120), and generates an interrupt signal MSI-X. After the driver completes processing a group of completion queue entries, it signals this to the SSD 120 by writing the completion queue's updated head pointer to the respective completion queue 226-229. According to embodiments of the present disclosure, the core of the NVMe controller 132 manages the submission and completion queues of the host 110 by tracking the number of in-flight commands in each of the HPQ 412 and LPQ 414.) determining, by the memory sub-system, priorities of the submission queues based on the analyzing; ([Horspool 0030-0034, 0036-0037, Figs. 3A, 3B, 4] As previously mentioned, when there is a plurality of submission queues from a host 110 to the SSD 120, the NVMe controller 132 adopts an arbitration scheme to determine the order in which a submission queue is to be selected for processing of the host commands contained therein. Arbitration is the method used to determine the submission queue from which the controller starts processing the next command(s). The NVMe controller 132 comprises a core (or processor) that utilizes a high priority command queue 412 (hereinafter “HPQ”) and a low priority command queue 414 (hereinafter “LPQ”) for further processing of commands received from the host 110.) selecting, by the memory sub-system, one or more submission queues based the priorities; ([Horspool 0030-0031] The NVMe controller 132 of the SSD 120 then selects a command from a submission queue of the plurality of submission queues 221-225 for processing using an arbitration scheme, which will be detailed below.) retrieving, by the memory sub-system and from the one or more submission queues, a subset of storage access commands in the plurality of submission queues; ([Horspool 0038, 0062, Figs. 4, 6] After receiving commands from a submission queue of the host 110, the NVMe controller 132 core may place the received commands into the HPQ 412 or the LPQ 414 for further processing. If the number of existing in-flight commands from the selected submission queue in the HPQ 412 does exceed a threshold in the HPQ 412, i.e. ‘Y’ in step 620, the at least one command received from the host 110 is added to a low priority command queue (LPQ) 414 of the NVMe controller 132 (step 630). However if the number of in-flight commands from the selected submission queue in the HPQ 412 does not exceed a threshold in the HPQ 412, i.e. ‘N’ in step 620, the at least one command received from the host 110 is added to the HPQ 412 of the NVMe controller 132, as shown in step 640. The commands in the HPQ 412 and LPQ 414 of the NVMe controller 132 are then relayed to the firmware control and configuration circuit 134 which maps the logical block addresses contained in the commands to physical NAND addresses.) and executing, by the memory sub-system, the subset of storage access commands ([Horspool 0062,Fig. 6] The commands are then processed by the remaining sub-controllers 136, 138 of the SoC controller 130, and the respective actions are then performed on the NAND devices 140 (step 650).).
Referring to claim 19, Horspool teaches
The non-transitory computer storage medium of claim 18, wherein the priorities are first priorities; the one or more submission queues are one or more first submission queues; and the subset of storage access commands is a first subset of storage access commands; and the method further comprises, after the retrieving of the subset of storage access commands: performing, by the memory sub-system, an analysis of current queue statuses of the plurality of submission queues without accessing the plurality of submission queues; ([Horspool 0003, 0029-0030, 0036, 0042-0043] The NVMe controller 132 comprises a core (or processor) that utilizes a high priority command queue 412 (hereinafter “HPQ”) and a low priority command queue 414 (hereinafter “LPQ”) for further processing of commands received from the host 110. The read performance and read data latency (i.e. the time from the command being added to the submission queue to the time the data is returned to the host memory and the command status is added to the completion queue) are critical elements for the operation of the SSD. A queue group may comprise one or more submission queues 221-225 and a completion queue 226-229. Associated with each queue 221-229 there is a hardware doorbell register to facilitate the signaling of incoming commands and outgoing completion notifications from and to the host 110. When the SSD 120 completes processing of a command, it inserts an entry on a completion queue of a specific queue group 211-214 (that has been previously associated with the submission queue of the same queue group from which the command was initially retrieved by the SSD 120), and generates an interrupt signal MSI-X. After the driver completes processing a group of completion queue entries, it signals this to the SSD 120 by writing the completion queue's updated head pointer to the respective completion queue 226-229. According to embodiments of the present disclosure, the core of the NVMe controller 132 manages the submission and completion queues of the host 110 by tracking the number of in-flight commands in each of the HPQ 412 and LPQ 414.) determining, by the memory sub-system, second priorities of the plurality of submission queues based on a result of the analysis of the current queue statues; ([Horspool 0030-0034, 0036-0037, Figs. 3A, 3B, 4] As previously mentioned, when there is a plurality of submission queues from a host 110 to the SSD 120, the NVMe controller 132 adopts an arbitration scheme to determine the order in which a submission queue is to be selected for processing of the host commands contained therein. Arbitration is the method used to determine the submission queue from which the controller starts processing the next command(s). The NVMe controller 132 comprises a core (or processor) that utilizes a high priority command queue 412 (hereinafter “HPQ”) and a low priority command queue 414 (hereinafter “LPQ”) for further processing of commands received from the host 110.) selecting, by the memory sub-system, one or more second submission queues based the second priorities; ([Horspool 0030-0031] The NVMe controller 132 of the SSD 120 then selects a command from a submission queue of the plurality of submission queues 221-225 for processing using an arbitration scheme, which will be detailed below.) retrieving, by the memory sub-system and from the one or more second submission queues, a second subset of storage access commands in the plurality of submission queues; ([Horspool 0038, 0062, Figs. 4, 6] After receiving commands from a submission queue of the host 110, the NVMe controller 132 core may place the received commands into the HPQ 412 or the LPQ 414 for further processing. If the number of existing in-flight commands from the selected submission queue in the HPQ 412 does exceed a threshold in the HPQ 412, i.e. ‘Y’ in step 620, the at least one command received from the host 110 is added to a low priority command queue (LPQ) 414 of the NVMe controller 132 (step 630). However if the number of in-flight commands from the selected submission queue in the HPQ 412 does not exceed a threshold in the HPQ 412, i.e. ‘N’ in step 620, the at least one command received from the host 110 is added to the HPQ 412 of the NVMe controller 132, as shown in step 640. The commands in the HPQ 412 and LPQ 414 of the NVMe controller 132 are then relayed to the firmware control and configuration circuit 134 which maps the logical block addresses contained in the commands to physical NAND addresses.) and executing, by the memory sub-system, the second subset of storage access commands after execution of the first subset of storage access commands ([Horspool 0062,Fig. 6] The commands are then processed by the remaining sub-controllers 136, 138 of the SoC controller 130, and the respective actions are then performed on the NAND devices 140 (step 650).).
Referring to claim 20, Horspool teaches
The non-transitory computer storage medium of claim 18, wherein the method further comprises: retrieving, by the memory sub-system, the queue statuses from a status array configured in a random access memory accessible to a host system that provides storage access commands in the plurality of submission queues; ([Horspool 0029-0030, Fig. 2] FIG. 2 shows further details of the host 110 and the NVMe controller 132 of the SSD 120 according to setup 200, according to an embodiment of the present disclosure. The host 110 may comprise a plurality of submission and completion queue groups 211-214 (i.e. status array) where some queue groups may be associated with a specific processor core such as Core 0, Core 1, . . . Core N, respectively, as shown in FIG. 2, where N is an integer. The controller management queue group 211 may be associated to any core, or may share the core with another core group. In general this is done to provide a form of isolation between the activities of different queue groups, which may be allocated by different application programs running on the host. One of the queue groups 211 may be allocated specifically for controller management and the handling of administrative commands. A queue group may comprise one or more submission queues 221-225 and a completion queue 226-229. Associated with each queue 221-229 there is a hardware doorbell register to facilitate the signaling of incoming commands and outgoing completion notifications from and to the host 110) wherein the plurality of submission queues are also configured in the random access memory ([Horspool 0003, 0025, 0030] SSD 120 also includes a memory external to the SoC controller 130, such as a dynamic random access memory (“DRAM”) 150. DRAM 150 comprises several buffers (not shown) used to buffer data during read and write operations between the host 110 and the storage elements 140 upon receipt of commands from the host 110. In some implementations, the whole or a part of the external memory DRAM 150 may be located within the SoC controller 130. When located within the SoC controller 130, at least a portion of the external memory may be implemented using a fast memory technology, such as static random access memory (RAM).).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRANCISCO A GRULLON whose telephone number is (571)272-8318. The examiner can normally be reached Monday - Friday, 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571)272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FRANCISCO A GRULLON/Primary Examiner, Art Unit 2132
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