DETAILED ACTION
The present application is being examined under the pre-AIA first to invent provisions.
Response to Amendment
This Office Action responses to the Applicant’s Amendment filed on 03/11/2026 in which claims 1 and 8 have been amended.
Claims 1-20 are pending for examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sforzin (US 2023/0005563) in view of Shen et al. (US 2013/0051143).
Regarding independent claim 1, Sforzin discloses an apparatus, comprising: a memory component including a plurality of groups of memory cells (see ABTRACT discloses: a memory having a plurality of groups of memory cells); and a processing device coupled to the memory component (304, figure 3, also see para.[0040]) and configured to: perform a sense operation on the plurality of groups of memory cells; and perform the corrective sense operation on a second one of the plurality of groups of memory cells using the corrective value (see paragraphs below). Noted: after perform a first sense operation, the controller perform a second sense operation) .
[0043] Memory device 302 may sense (e.g., read) data in memory array 306 by sensing voltage and/or current changes in the memory array columns using sense/buffer circuitry that in some examples may include read/latch circuitry 320 and/or sensing circuitry 305. Read/latch circuitry 320 may read and latch data from the memory array 306. Sensing circuitry 305 may include a number of sense amplifiers coupled to memory cells of memory array 306, which may operate in combination with the read/latch circuitry 320 to sense (e.g., read) memory states from targeted memory cells. I/O circuitry 312 may be included for bi-directional data communication over the I/O connections 310 with controller 304. Write circuitry 322 may be included to write data to memory array 306.
[0044] In some embodiments, controller 304 can concurrently (e.g., simultaneously) program (e.g., write) data to a single memory cell of each respective sub-group of one of the plurality of groups of memory cells, and can concurrently sense (e.g., read) data stored in a single memory cell of each respective sub-group of one of the plurality of groups of memory cells (e.g., a single memory cell in each respective tile of a partition can be simultaneously read or written). Further, controller 304 can perform program operations on each of the plurality of groups of memory cells in parallel, and can perform sense operations on each of the plurality of groups of memory cells in parallel (e.g., read and write operations can be performed in a staggered parallelism through the partitions).
[0017] Error correction operations can be used to correct such errors occurring in data sensed from the memory. For instance, error correction operations can utilize codewords to perform error correction operations on erroneous data sensed from the memory. To increase the effectiveness (e.g., the correction rate and/or uniformity) of the error correction operations, different portions of the codewords may be stored in different portions of the memory, and at different distances from the row and column decoders of their respective memory portions (e.g., the memory cells used to store the different portions of the codewords may be located in different partitions of the memory, and at different electrical distances from their respective row and column decoders).
[0038] Error correction operations can be used to correct such errors occurring in data sensed from memory cells 125. For instance, error correction operations can utilize codewords to perform error correction operations on erroneous data sensed from the memory cells. As an example, an error correction operation can utilize redundant data bits in addition to information bits to generate a codeword (e.g., a codeword data pattern). Error correction can be performed on a received word to recover the original codeword, and the presence of redundant bits enables the original data bits to be recovered even if some number of the original or redundant bits have been corrupted.
However, Sforzin is silent with respect to perform a corrective sense operation on a first one of the plurality of groups of memory cells using a corrective value that is equal to a voltage amount.
Shen et al. disclose perform a corrective sense operation on a first one of the plurality of groups of memory cells using a corrective value that is equal to a voltage amount (see para. below).
[0031] Since the aforementioned coupling effects can change the Vt of a programmed cell, sensing voltages previously associated with determining the state of a memory cell, e.g., the occurrence of the Vt change due to coupling effects, may not provide accurate and/or reliable sensing of the memory cell. One or more embodiments of the present disclosure can compensate for Vt shifts due to coupling effects by changing, e.g., adjusting, the sensing voltages associated with sensing the memory cells in order to provide accurate and/or reliable sensing of memory cells that have undergone a Vt change due to coupling effects. As described further below, in one or more embodiments, a memory cell can be sensed using a voltage that is changed in accordance with a memory cell coupling compensation voltage. If the memory cell fails an error check, e.g., an error detection/correction operation, the cell can be sensed using a voltage that is changed in accordance with a different memory cell coupling compensation voltage, such as where the memory cell coupling compensation voltage is added to or subtracted from an uncompensated sensing voltage, for instance. The particular memory cell coupling compensation voltages used can depend on various factors such as the program states of adjacent cells, e.g., the particular program states of cells adjacent to a target cell being sensed.
Since Sforzin and Shen et al. are both from the same field of endeavor, the purpose disclosed by Shen et al. would have been recognized in the pertinent art of Sforzin.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Sforzin to teaching of Shen etal. for purpose of performing an error check on the state of the memory cell.
Regarding claim 2, Sforzin and Shen et al. disclose the limitation of claim 1.
Sforzin further discloses wherein the processing device is configured to: determine an error rate associated with the sense operation performed on the plurality of groups of memory cells; and perform the corrective sense operation based on the error rate (see para.[0038] below).
[0038] Error correction operations can be used to correct such errors occurring in data sensed from memory cells 125. For instance, error correction operations can utilize codewords to perform error correction operations on erroneous data sensed from the memory cells. As an example, an error correction operation can utilize redundant data bits in addition to information bits to generate a codeword (e.g., a codeword data pattern). Error correction can be performed on a received word to recover the original codeword, and the presence of redundant bits enables the original data bits to be recovered even if some number of the original or redundant bits have been corrupted.
Regarding claim 3, Sforzin and Shen et al. disclose the limitation of claim 1.
Sforzin further discloses wherein the first one of the plurality of groups of memory cells and the second one of the plurality of groups of memory cells are binned together based on a threshold voltage value of their neighboring memory cells (see figure 2A and para.[0029] below).
[0029] In FIG. 2A, the voltage VCELL may correspond to a voltage differential applied to (e.g., across) the memory cell, such as the difference between a bit line voltage (VBL) and a word line voltage (VWL) (e.g., VCELL=VBL−VWL). The threshold voltage distributions (e.g., ranges) 201-1, 201-2, 202-1, and 202-2 may represent a statistical variation in the threshold voltages of memory cells programmed to a particular state. The distributions illustrated in FIG. 2A correspond to the current versus voltage curves described further in conjunction with FIGS. 2B and 2C, which illustrate snapback asymmetry associated with assigned data states.
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Regarding claim 4, Sforzin and Shen et al. disclose the limitation of claim 1.
Sforzin further discloses wherein the processing device is configured to perform the corrective sense operation on a third one of the plurality of groups of memory cells using the corrective value (see rejection of claim 1). Noted: after sense operation on a first and second groups, sense operation on a third).
Regarding claim 7, Sforzin and Shen et al. disclose the limitation of claim 1.
Sforzin further discloses wherein the processing device is configured to sort the memory cells into the plurality of groups based on a threshold voltage value of the memory cells (see para.[0030] below).
[0030] In some examples, the magnitudes of the threshold voltages of a memory cell 125 in a particular state may be asymmetric for different polarities, as shown in FIGS. 2A, 2B and 2C. For example, the threshold voltage of a memory cell 125 programmed to a reset state (e.g., state 0) or a set state (e.g., state 1) may have a different magnitude in one polarity than in an opposite polarity. For instance, in the example illustrated in FIG. 2A, a first data state (e.g., state 0) is associated with a first asymmetric threshold voltage distribution (e.g., threshold voltage distributions 201-1 and 201-2) whose magnitude is greater for a negative polarity than a positive polarity, and a second data state (e.g., state 1) is associated with a second asymmetric threshold voltage distribution (e.g., threshold voltage distributions 202-1 and 202-2) whose magnitude is greater for a positive polarity than a negative polarity. In such an example, an applied voltage magnitude sufficient to cause a memory cell 125 to snap back can be different (e.g., higher or lower) for one applied voltage polarity than the other.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sforzin (US 2023/0005563) in view of Shen et al. (US 2013/0051143) and further in view of Khayat et al. (US 2022/0044737).
Regarding claim 5, Sforzin and Shin et al. disclose the limitation of claim 1.
However, Sforzin and Shen et al. are silent with respect wherein a threshold voltage value of the memory cells of the first one of the plurality of groups and the second one of the plurality of groups have shifted due to charge loss.
Khayat et al. disclose wherein a threshold voltage value of the memory cells of the first one of the plurality of groups and the second one of the plurality of groups have shifted due to charge loss (see para.[0014] below, also see ABTRACT).
However, after the states of integrated circuit memory cells are configured/programmed using write operations to store data in the memory cells, the optimized threshold voltage for reading the memory cells can shift due to a number of factors, such as charge loss, read disturb, cross-temperature effect (e.g., write and read at different operating temperatures), etc., especially when a memory cell is programmed to store multiple bits of data.
Since Sforzin, Shenet al. and Khayat et al.are from the same field of endeavor, the purpose disclosed by Khayat et al. would have been recognized in the pertinent art of Sforzin and Shen et al.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Sforzin and Shen et al. to teaching of Khayat et al. for purpose of using threshold voltages to interpret different states of bits of that stored in the memory cell.
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is statement of reasons for the indication of allowable subject matter:
Regarding claim 6, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claim limitation of wherein the threshold value of the memory cells of a first subgroup of the first one of the plurality of groups and the second one of the plurality of groups have shifted less than the threshold voltage value of the memory cells of a second subgroup of the first one of the plurality of groups and the second one of the plurality of groups in combination with the other limitations thereof as is recited in the claim.
Claims 8-20 are allowed.
Regarding independent claim 8, the prior art does not teach or suggest the claimed invention having “performing a sense operation on a plurality of groups of memory cells within a memory device; performing a corrective sense operation on a first one of the plurality of groups of memory cells using a corrective value that is equal to a voltage amount that reduces an error rate associated with the sense operation performed on the plurality of groups of memory cells; and performing the corrective sense operation on a second one of the plurality of groups of memory cells using the corrective value”, in combination of other limitations thereof as recited in the claim.
Regarding claims 9-14, the claims have been found allowable due to their dependencies to claim 8 above.
Regarding independent claim 15, the prior art does not teach or suggest the claimed invention having “a memory component including a plurality of groups of memory cells; and a processing device coupled to the memory component and configured to: perform a sense operation on the plurality of groups of memory cells; bin a number of groups of the plurality of groups of memory cells together based on a threshold voltage value of the memory cells of the number of groups; and perform a corrective sense operation on the number of groups of memory cells using a corrective value”, in combination of other limitations thereof as recited in the claim.
Regarding claims 16-20, the claims have been found allowable due to their dependencies to claim 15 above.
Response to Arguments
Applicant's arguments filed 03/11/2026 have been fully considered but they are not persuasive.
Applicants argue that the reference of Sforzin does not teach that the codewords used to perform the error correction operation are a correction value equal to a voltage amount. Rather, Sforzin appears to teach that the codewords are data values.
The Examiner respectfully disagrees with Applicant’s argument because the combined references of Sforzin and Shen et al. disclose the above-noted claimed features as applied in the rejection of independent claim 1.
Regarding independent claim 1, Sforzin discloses an apparatus, comprising: a memory component including a plurality of groups of memory cells (see ABTRACT discloses: a memory having a plurality of groups of memory cells); and a processing device coupled to the memory component (304, figure 3, also see para.[0040]) and configured to: perform a sense operation on the plurality of groups of memory cells; and perform the corrective sense operation on a second one of the plurality of groups of memory cells using the corrective value (see paragraphs below). Noted: after perform a first sense operation, the controller perform a second sense operation) .
[0043] Memory device 302 may sense (e.g., read) data in memory array 306 by sensing voltage and/or current changes in the memory array columns using sense/buffer circuitry that in some examples may include read/latch circuitry 320 and/or sensing circuitry 305. Read/latch circuitry 320 may read and latch data from the memory array 306. Sensing circuitry 305 may include a number of sense amplifiers coupled to memory cells of memory array 306, which may operate in combination with the read/latch circuitry 320 to sense (e.g., read) memory states from targeted memory cells. I/O circuitry 312 may be included for bi-directional data communication over the I/O connections 310 with controller 304. Write circuitry 322 may be included to write data to memory array 306.
[0044] In some embodiments, controller 304 can concurrently (e.g., simultaneously) program (e.g., write) data to a single memory cell of each respective sub-group of one of the plurality of groups of memory cells, and can concurrently sense (e.g., read) data stored in a single memory cell of each respective sub-group of one of the plurality of groups of memory cells (e.g., a single memory cell in each respective tile of a partition can be simultaneously read or written). Further, controller 304 can perform program operations on each of the plurality of groups of memory cells in parallel, and can perform sense operations on each of the plurality of groups of memory cells in parallel (e.g., read and write operations can be performed in a staggered parallelism through the partitions).
[0017] Error correction operations can be used to correct such errors occurring in data sensed from the memory. For instance, error correction operations can utilize codewords to perform error correction operations on erroneous data sensed from the memory. To increase the effectiveness (e.g., the correction rate and/or uniformity) of the error correction operations, different portions of the codewords may be stored in different portions of the memory, and at different distances from the row and column decoders of their respective memory portions (e.g., the memory cells used to store the different portions of the codewords may be located in different partitions of the memory, and at different electrical distances from their respective row and column decoders).
[0038] Error correction operations can be used to correct such errors occurring in data sensed from memory cells 125. For instance, error correction operations can utilize codewords to perform error correction operations on erroneous data sensed from the memory cells. As an example, an error correction operation can utilize redundant data bits in addition to information bits to generate a codeword (e.g., a codeword data pattern). Error correction can be performed on a received word to recover the original codeword, and the presence of redundant bits enables the original data bits to be recovered even if some number of the original or redundant bits have been corrupted.
However, Sforzin is silent with respect to perform a corrective sense operation on a first one of the plurality of groups of memory cells using a corrective value that is equal to a voltage amount.
Shen et al. disclose perform a corrective sense operation on a first one of the plurality of groups of memory cells using a corrective value that is equal to a voltage amount (see para. below).
[0031] Since the aforementioned coupling effects can change the Vt of a programmed cell, sensing voltages previously associated with determining the state of a memory cell, e.g., the occurrence of the Vt change due to coupling effects, may not provide accurate and/or reliable sensing of the memory cell. One or more embodiments of the present disclosure can compensate for Vt shifts due to coupling effects by changing, e.g., adjusting, the sensing voltages associated with sensing the memory cells in order to provide accurate and/or reliable sensing of memory cells that have undergone a Vt change due to coupling effects. As described further below, in one or more embodiments, a memory cell can be sensed using a voltage that is changed in accordance with a memory cell coupling compensation voltage. If the memory cell fails an error check, e.g., an error detection/correction operation, the cell can be sensed using a voltage that is changed in accordance with a different memory cell coupling compensation voltage, such as where the memory cell coupling compensation voltage is added to or subtracted from an uncompensated sensing voltage, for instance. The particular memory cell coupling compensation voltages used can depend on various factors such as the program states of adjacent cells, e.g., the particular program states of cells adjacent to a target cell being sensed.
Therefore, in view of the above reasons, the Examiner maintains rejections.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MINH D DINH whose telephone number is (571)270-5375. The examiner can normally be reached Monday to Friday 8:00am 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MINH D DINH/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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