DETAILED ACTION
This action is responsive to the communications filed on 7/26/2024.
Currently, claims 1-20 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 7-8, 10-12, 14-15, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Valaee et al. (US 2023/0275792: hereinafter “Valaee”) in view of Seong et al. (US 2022/0057969: hereinafter “Seong”).
With regards to claims 1 and 7, Valaee teaches an apparatus and method (figs. 1-9: see the circuitry of the apparatus shown by at least figs. 6+7. Note that the method steps are implemented as functions of the cited hardware of Valaee), comprising (addressed below):
a driver circuit configured, based on a [received] data signal, to transmit a drive signal onto a signal wire (figs. 1-9: where at least fig. 6 show a data line driver 602 configured to transmit a drive signal onto a signal wire/channel 610 (using on the input data signal 612)); and
an equalization circuit (figs. 1-9: see figures 6+7: see timer and pulse generator 604 and the boosting circuitry 606 (of the Tx equalizer 600 ([0047] [Wingdings font/0xE0] “edge boosting equalizer”)) operating parallel with the data line driver 602) configured to (addressed below):
transmit, using a first current and the data signal, a first equalization signal onto an equalization node (figs. 1-9: see figs. 6+7; note that figure 7 shows the nested internal circuitry of the Tx equalizer of figure 6. Where the timer and pulse generator 604 of the Tx equalizer ‘receives’ and processes the input data signal and then generates/outputs a first equalization signal (using the data signal and equalizer boost current 730 of unit 626a/704a). Where the equalization node is mapped to the node at the output of the plurality of Tx equalization edge boosting circuits (see the node on the right/output side of unit 606 of figure 6 as well as ‘equalizer output node 720’ of figure 7)) that is coupled to the signal wire via a first resistor (figs. 1-9: see figs. 6+7: where said transmitted first equalization (output by 626a/704a and the ‘equalizer output node of 606/720) passes through a resistor (RLine) before being output to the wire/line and pad (as shown by figure 7)); and
in response to a detection of a transition of the data signal (figs. 1-9: see figs. 6+7: see [0040-0041] in regards to the Tx equalizer detecting and processing/boosting edge transition(s) in the data signal (as shown by figs. 3 and 8); also note the concept of pre-emphasis and de-emphasis in the cited paragraphs as well as the “Pemp” control signals in figs. 6 & 7. Note the ‘transition edge boosting equalizer’ of the transmitter was previously addressed; also ‘edge boosting equalization’ applies to both rising and falling edge transitions in the data signal, see [0053+0063]), transmit, using a second current greater than the first current, a second equalization signal onto the equalization node (figs. 1-9: see figs. 6+7: where the second current is mapped to the boosting current of at least boosting circuit 626b/704b which has a higher weighted current value (for the previously addressed Tx equalizer edge boosting), also at least see [0048+0060], where the current of equalization signal output by 626b is twice (i.e. 2X) as strong as the current of equalization signal output by 626a (i.e. 1X); as addressed by at least [0048+0060] as well as correct meaning of the values “1X, 2X, and 4X” as well as the equalization current and boosting current of . Additionally the equalizer boosting control signal is a 3-bit EQ code [0060] to select from eight different boosting states (ranging from zero to seven), see [0060]).
Limitation 1 (below)
Valaee is silent to disclosing the limitation “transmit, using a first current and the data signal, a first equalization signal onto an equalization node that is coupled to the signal wire via a first capacitor” (emphasis added).
However, secondary reference Seong shows a similar invention including a wire/line driver that receives and processes/transmits a input data signal to wire/line channel (see figs. 1b, 4a/b, 7a/b). Also the equalizer circuitry is in parallel to the Tx driver and also outputs to the wire/line channel and output pad (see figs. 1b, 4a/b, 7a/b and see [0043-0045]); where the equalizer output node (i.e. at the output of equalizer/pulse unit 122) is connect the wire/line channel (and pad) via a filtering circuit 124 that includes an in-line resistor and in-line capacitor (as shown in figs. 4a/b). Where the equalizer generates signal based on the rising and falling edge transitions based on the data signal [0045-0046].
Where [0045] states (with emphasis added):
[0045] The filtering circuit 124 may include a capacitor element C and a resistor element R. For example, the filtering circuit 124 may filter [out] a direct current (DC) component of the pulse signal PS and generate an equalization signal including an alternating current (AC) component of the pulse signal PS. In some embodiments, the equalization signal may include a falling edge component or a rising edge component of the pulse signal PS to suppress a reflected wave reaching the output pad 130. The configuration of the filtering circuit 124 is just an example, and embodiments are not limited thereto. The filtering circuit 124 may have various configurations. The output pad 130 may output a second input data signal IN′ resulting from a combination of the first input data signal IN, which has been driven, with the equalization signal.
Therefore, in view of the cited teachings of Seong above, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Valaee (specifically previously addressed in-line resistor RLine that connects the ‘equalization node’ and the ‘signal wire’ of the Valaee reference (as previously addressed) to also include an in-line capacitor C serially connected to in-line resistor R (see unit 124 as shown by figures 4a/b of Seong and [0045-0046]) in order to yield the corresponding disclosed benefits of DC filtering/isolation/removal of the equalization signal (as stated in [0045]).
With regards to claim 14, Valaee teaches a system (see figures 1-9, e.g. figs. 1+2 and figs. 6-8), comprising (addressed below):
a first device (figs. 1-9: where figure 1 shows a system that includes at least one ‘first device’) that includes a plurality of drive subsystems coupled to corresponding wires of a plurality of wires included in a communication bus (figs. 1-9: see figs. 1+2; where the ‘first device’ includes plurality of subsystems and drive subsystems connected via a communication bus including multiple wires; where figure 2 shows an example of one communication channel between at least two of the subsystems including multiple wires (of the bus) as well as multiple drive subsystems (in the Tx chip)), wherein the plurality of drive subsystems (previously addressed) includes a particular drive subsystem (figs. 1-9: where a single/particular drive(r) subsystem for a single/particular wire is shown by figs. 6+7) that includes (addressed below):
a driver circuit configured, based on a data signal, to transmit a drive signal onto a particular wire of the plurality of wires (figs. 1-9: where at least fig. 6 show a data line driver 602 configured to transmit a drive signal onto a single/particular signal wire/channel 610 (using on the input data signal 612). Where the limitation ‘a particular wire of the plurality of wires’ was previously addressed and/or is readily apparent); and
an equalization circuit (figs. 1-9: see figures 6+7: see timer and pulse generator 604 and the boosting circuitry 606 (of the Tx equalizer 600 ([0047] [Wingdings font/0xE0] “edge boosting equalizer”)) operating parallel with the data line driver 602) coupled to the particular wire via a first resistor (figs. 1-9: see figures 6+7: see timer and pulse generator 604 and the boosting circuitry 606 (of the Tx equalizer 600 ([0047] [Wingdings font/0xE0] “edge boosting equalizer”)) operating parallel with the data line driver 602. Note that figure 7 shows the nested internal circuitry of the Tx equalizer of figure 6; where the figure 7 discloses that the transmitted first equalization (output by 626a/704a and the ‘equalizer output node of 606/720) passes through a resistor (RLine) before being output to the particular wire/line and pad (as shown by figure 7)), wherein the equalization circuit (previously addressed) is configured to:
drive the first resistor using a first current and the data signal (figs. 1-9: see figs. 6+7; note that figure 7 shows the nested internal circuitry of the Tx equalizer of figure 6. Where the timer and pulse generator 604 of the Tx equalizer ‘receives’ and processes the input data signal and then generates/outputs a first equalization signal (using the data signal and ‘equalizer boost current’ 730 of unit 626a/704a). Where the equalization node is mapped to the node at the output of the plurality of Tx equalization edge boosting circuits (see the node on the right/output side of unit 606 of figure 6 as well as ‘equalizer output node 720’ of figure 7). Where the ‘first resistor’ (RLine) occurs after ‘equalizer output node 720’ of figure 7 and thus logical the ‘first resistor’ (RLine) is ‘driven’ by the first current (i.e. ‘equalizer boost current’ 730 of unit 626a/704a) and the data signal; as previously addressed); and
in response to a detection of a transition of the data signal (figs. 1-9: see figs. 6+7: see [0040-0041] in regards to the Tx equalizer detecting and processing/boosting edge transition(s) in the data signal (as shown by figs. 3 and 8); also note the concept of pre-emphasis and de-emphasis in the cited paragraphs as well as the “Pemp” control signals in figs. 6 & 7. Note the ‘transition edge boosting equalizer’ of the transmitter was previously addressed; also ‘edge boosting equalization’ applies to both rising and falling edge transitions in the data signal, see [0053+0063]), drive the first resistor using a second current greater than the first current (figs. 1-9: see figs. 6+7: where the second current is mapped to the boosting current of at least boosting circuit 626b/704b which has a higher weighted current value (for the previously addressed Tx equalizer edge boosting), also at least see [0048+0060], where the current of equalization signal output by 626b is twice (i.e. 2X) as strong as the current of equalization signal output by 626a (i.e. 1X); as addressed by at least [0048+0060] as well as correct meaning of the values “1X, 2X, and 4X” as well as the equalization current and boosting current of . Additionally the equalizer boosting control signal is a 3-bit EQ code [0060] to select from eight different boosting states (ranging from zero to seven), see [0060].
Where the ‘first resistor’ (RLine) occurs after ‘equalizer output node 720’ of figure 7 and thus logical the ‘first resistor’ (RLine) is ‘driven’ by the second current (i.e. ‘equalizer boost current’ 730 of unit 626b/704b) and the data signal; as previously addressed).
Limitation 1 (below)
Valaee is silent to disclosing the claimed ‘first capacitor’ (the later statements of “the first capacitor”).
With respect to the claim limitations Valaee is silent to disclosing “an equalization circuit coupled to the particular wire via a first capacitor, wherein the equalization circuit is configured to:
drive the first capacitor using a first current and the data signal; and
in response to a detection of a transition of the data signal, drive the first capacitor using a second current greater than the first current”
However, secondary reference Seong shows a similar invention including a wire/line driver that receives and processes/transmits a input data signal to wire/line channel (see figs. 1b, 4a/b, 7a/b). Also the equalizer circuitry is in parallel to the Tx driver and also outputs to the wire/line channel and output pad (see figs. 1b, 4a/b, 7a/b and see [0043-0045]); where the equalizer output node (i.e. at the output of equalizer/pulse unit 122) is connect the wire/line channel (and pad) via a filtering circuit 124 that includes an in-line resistor and in-line capacitor (as shown in figs. 4a/b). Where the equalizer generates signal based on the rising and falling edge transitions based on the data signal [0045-0046].
Where [0045] states (with emphasis added):
[0045] The filtering circuit 124 may include a capacitor element C and a resistor element R. For example, the filtering circuit 124 may filter [out] a direct current (DC) component of the pulse signal PS and generate an equalization signal including an alternating current (AC) component of the pulse signal PS. In some embodiments, the equalization signal may include a falling edge component or a rising edge component of the pulse signal PS to suppress a reflected wave reaching the output pad 130. The configuration of the filtering circuit 124 is just an example, and embodiments are not limited thereto. The filtering circuit 124 may have various configurations. The output pad 130 may output a second input data signal IN′ resulting from a combination of the first input data signal IN, which has been driven, with the equalization signal.
Therefore, in view of the cited teachings of Seong above, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Valaee (specifically previously addressed in-line resistor RLine that connects the ‘equalization node’ and the ‘signal wire’ of the Valaee reference (as previously addressed) to also include an in-line capacitor C serially connected to in-line resistor R (see unit 124 as shown by figures 4a/b of Seong and [0045-0046]) in order to yield the corresponding disclosed benefits of DC filtering/isolation/removal of the equalization signal (as stated in [0045]).
With regards to claims 2 and 8, Valaee as modified supra teaches the limitations of claims 1 and 7, above.
Valaee as modified supra teaches wherein the equalization circuit (previously addressed) includes a weak driver circuit (Valaee: figs. 1-9: see figs. 6+7+8: where the ‘weak driver circuit’ is mapped to 1X Tx equalizer current boost unit 626a/704a; which has the weakest equalization current boosting value equal to “1X”, versus the stronger values of 2X or 4X; as previously addressed) configured, using the data signal, to source the first current to the equalization node (and to a terminal of the first capacitor) (previously addressed and/or readily apparent).
With regards to claims 4 and 10, Valaee as modified supra teaches the limitations of claims 2 and 8, above.
Valaee as modified supra teaches wherein the equalization circuit (previously addressed) further includes a strong driver circuit (Valaee: figs. 1-9: see figs. 6+7+8: where the ‘strong driver circuit’ is mapped to 2X Tx equalizer current boost unit 626b/704b; which has a stronger equalization current boosting value equal to “2X” as compared to 1X value of 626a/704a) configured, in response to the detection of the transition of the data signal (previously addressed: see the previously addressed concept of edge boosting equalization for rising and/or falling edge transitions of the data signal), to source/transmitting the second (equalization signal) current to the equalization node (and driving the first capacitor using the second current of the strong driver) (previously addressed and/or readily apparent).
With regards to claims 5, 11, and 12; Valaee as modified supra teaches the limitations of claims 4 and 10, above.
Valaee as modified supra teaches wherein the equalization circuit (previously addressed) (transmitting the second equalization signal (previously addressed)) further includes an activation circuit configured to generate an activation pulse signal in response to the detection of the transition of the data signal (Valaee: figs. 1-9: see figs. 6+7+8: where the activation circuit is mapped to the ‘timer & pulse generator 604’ of figure 6 and/or ‘pulse generators 702a-702c & the Timer (delay element) 708’ of figure 7; which generate the activations pulse signal(s) in response to the detecting the rising/fall edge transitions of the data signal (for controlling the equalization boosting current values selectively output by boosting units 626a-626c of figure 6 and/or 704a-704c of figure 7. Note that figure 8 in section 800 shows an example where the pre-equalization current boosting is applied to a detect rising edge transition of the data signal), and wherein the strong driver circuit (previously addressed) is further configured to (addressed below):
activate in response to receiving the activation pulse signal (Valaee: figs. 1-9: see figs. 6+7+8: where figure 8 in section 800 addresses ‘activation (of the strong boosting/equalization driver 626b/704b) in response to receiving the activation pulse signal of boost signal (operations of the boosting circuitry), when the X2 boosting equalization current is selected (in the context addressed above). The remaining limitations were previously addressed and/or readily apparent); and
deactivate in response to a determination that a duration of the activation pulse signal has elapsed (Valaee: figs. 1-9: see figs. 6+7+8: where figure 8 in section 800 shows an example where the pre-equalization current boosting is applied to a detect rising edge transition of the data signal, afterward to the boost signal (operations of the boosting circuitry) is/are ‘deactivated’. The remaining limitations were previously addressed and/or readily apparent).
With regards to claim 15, Valaee as modified supra teaches the limitations of claim 14, above.
Valaee as modified supra teaches wherein the equalization circuit (previously addressed) includes a weak driver circuit (Valaee: figs. 1-9: see figs. 6+7+8: where the ‘weak driver circuit’ is mapped to 1X Tx equalizer current boost unit 626a/704a; which has the weakest equalization current boosting value equal to “1X”, versus the stronger values of 2X or 4X; as previously addressed) configured, using the data signal, to source the first current to the equalization node and to drive the first capacitor using the first current (previously addressed and/or readily apparent).
With regards to claim 17, Valaee as modified supra teaches the limitations of claim 14, above.
Valaee as modified supra teaches wherein the equalization circuit (previously addressed) further includes a strong driver circuit (Valaee: figs. 1-9: see figs. 6+7+8: where the ‘strong driver circuit’ is mapped to 2X Tx equalizer current boost unit 626b/704b; which has a stronger equalization current boosting value equal to “2X” as compared to 1X value of 626a/704a), and
wherein to drive the first capacitor using the second current (Valaee: the second current is the equalization boosting current signal at value 2X output 626b/704b. The other limitations were previously addressed and/or are readily apparent), the equalization circuit is further configured to activate the strong driver circuit in response to the detection of the transition of the data signal (Valaee: figs. 1-9: see figs. 6+7+8: where the activation circuit is mapped to the ‘timer & pulse generator 604’ of figure 6 and/or ‘pulse generators 702a-702c & the Timer (delay element) 708’ of figure 7; which generate the activations pulse signal(s) in response to the detecting the rising/fall edge transitions of the data signal (for controlling the equalization boosting current values selectively output by boosting units 626a-626c of figure 6 and/or 704a-704c of figure 7. Note that figure 8 in section 800 shows an example where the pre-equalization current boosting is applied to a detect rising edge transition of the data signal. Where figure 8 in section 800 addresses ‘activation (of the strong boosting/equalization driver 626b/704b) in response to receiving the activation pulse signal of boost signal (operations of the boosting circuitry), when the X2 boosting equalization current is selected (in the context addressed above). The remaining limitations were previously addressed and/or readily apparent).
With regards to claim 18, Valaee as modified supra teaches the limitations of claim 17, above.
Valaee as modified supra teaches wherein to activate the strong driver circuit (previously addressed), the equalization circuit (previously addressed) is further configured to (addressed below):
generate an activation pulse signal in response to the detection of the transition of the data signal (Valaee: figs. 1-9: see figs. 6+7+8: where the activation circuit is mapped to the ‘timer & pulse generator 604’ of figure 6 and/or ‘pulse generators 702a-702c & the Timer (delay element) 708’ of figure 7; which generate the activations pulse signal(s) in response to the detecting the rising/fall edge transitions of the data signal (for controlling the equalization boosting current values selectively output by boosting units 626a-626c of figure 6 and/or 704a-704c of figure 7. Note that figure 8 in section 800 shows an example where the pre-equalization current boosting is applied to a detect rising edge transition of the data signal. Where figure 8 in section 800 addresses ‘activation (of the strong boosting/equalization driver 626b/704b) in response to receiving the activation pulse signal of boost signal (operations of the boosting circuitry), when the X2 boosting equalization current is selected (in the context addressed above). The remaining limitations were previously addressed and/or readily apparent);
activate the strong driver circuit using the activation pulse signal (Valaee: figs. 1-9: see figs. 6+7+8: where figure 8 in section 800 addresses ‘activation (of the strong boosting/equalization driver 626b/704b) in response to receiving the activation pulse signal of boost signal (operations of the boosting circuitry), when the X2 boosting equalization current is selected (in the context addressed above). The remaining limitations were previously addressed and/or readily apparent); and
deactivate the strong driver circuit in response to a determination that a duration of the activation pulse signal has elapsed (Valaee: figs. 1-9: see figs. 6+7+8: where figure 8 in section 800 shows an example where the pre-equalization current boosting is applied to a detect rising edge transition of the data signal, afterward to the boost signal (operations of the boosting circuitry) is/are ‘deactivated’. The remaining limitations were previously addressed and/or readily apparent).
With regards to claim 19, Valaee as modified supra teaches the limitations of claim 18, above.
Valaee as modified supra teaches wherein to generate the activation pulse signal (previously addressed), the equalization circuit (previously addressed) is further configured to (addressed below):
generate a delayed version of the data signal (Valaee: figs. 1-9: see figs. 6+7+8: where figure 7 shows the Timer (delay element) 708 generating a delay version of the input data signal; where the data signal and the delay data signal are ‘combined’ in each of pulse generators 702a-702c); and
combine the data signal and the delayed version of the data signal (Valaee: figs. 1-9: see figs. 6+7+8: where figure 7 shows the Timer (delay element) 708 generating a delay version of the input data signal; where the data signal and the delay data signal are ‘combined’ in each of pulse generators 702a-702c).
With regards to claim 20, Valaee as modified supra teaches the limitations of claim 14, above.
Valaee as modified supra teaches wherein the transition of the data signal (previously addressed) includes a change in a voltage level of the data signal from a first value to a second value greater than the first value (Valaee: figs. 1-9: see figs. 6+7+8: where figure 8 in section 800 shows an example where the pre-equalization current boosting is applied to a detect rising edge transition of the data signal (i.e. the voltage level of the data signal changes from a lower first voltage to a higher second voltage). The remaining limitations were previously addressed and/or readily apparent).
Allowable Subject Matter
Claims 3, 6, 9, 13, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Martin et al. (US 2006/0290439), Li et al. (US 2016/0036470), Dong (US 2018/0278440), and Nguyen et al. (USPN 10,727,895). Additional reference are cited in the attached PTO-892 form.
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/JAMES M PEREZ/Primary Examiner, Art Unit 2635 5/2/2026
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