DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claims 1-5 and 10-12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim U.S. Patent Application Publication 2025/0095694 A1 (the ‘694 reference).
The reference discloses in Fig. 12 and related text a semiconductor device as claimed.
Referring to claim 1, the ‘694 reference discloses a semiconductor device comprising:
a first semiconductor structure including a first substrate (2SB, para [91] (paragraph(s) [0091])), circuit devices (“peripheral circuit”, para [91]) disposed on the first substrate, and first metal bonding layers (BPDp, para [91]) disposed on the circuit devices; and
a second semiconductor structure (CSTK, para [90]) including gate electrodes (gate lines GL, para [46]) spaced apart from each other and stacked in a first direction (Z direction), perpendicular to upper surfaces of the first metal bonding layers (BPDp), channel structures (plug PL, PLc, para [46, 92], see also Fig. 3) passing through the gate electrodes (GL), extending in the first direction (the Z direction), and respectively including a channel layer (CHL, para [50], see also Fig. 3), second metal bonding layers (BPDc, para [92]) disposed below the channel structures (PLc) and the gate electrodes (GL) and connected to the first metal bonding layers (BPDp), bit lines (BL, para [38]) disposed below the channel structures (PL), extending in a second direction (Y direction), perpendicular to the first direction (the Z direction), and spaced apart from each other, and source lines (SL, one depicted in Fig. 12, para [8, 38], para [8]:, claim 14: “gate lines alternately stacked on each other between bit lines and source lines”, see also Fig. 2) disposed on the channel structures (PLc), extending in a third direction (X direction), perpendicular to the second direction, and spaced apart from each other,
wherein the channel structures (PLc) are respectively disposed in intersection regions in which the bit lines (BL) and the source lines (SL) intersect each other.
Referring to claim 2, Fig. 4L depicts that the bit lines (BL) are respectively disposed below columns in the second direction (the Y direction) of the channel structures (including channel CHL).
Referring to claim 3, Fig. 12 depicts that the bit lines (BL) extend through central axes in the second direction (the Y direction) of the channel structures (PLc).
Referring to claim 4, the reference further discloses that the second semiconductor structure (CSTK) further includes channel contact plugs (BLC, para [67], see Fig. 4I) connecting the bit lines (BL) and the channel structures (PL, PLc) to each other.
Referring to claim 5, the reference further discloses that the second semiconductor structure (CSTK) further includes source contact plugs (SLC, one depicted in Fig. 4I, para [66]) connecting the source lines and the circuit devices to each other (see also Figs. 1 and 2).
Referring to claim 10, the reference further discloses that the channel structures (PLc) arranged in a line with respect to the third direction among the channel structures form row groups, respectively, and each of the source lines (one source line SL is depicted in Fig. 12, but a plurality of source lines is depicted in Fig. 2 and para [8], claim 14: “gate lines alternately stacked on each other between bit lines and source lines”) is connected to one row group among the row groups.
Referring to claim 11, Fig. 7 depicts that the channel structures (PL) arranged in a line with respect to the third direction (the X direction) among the channel structures (PL) form row groups, respectively, and each of the source lines (SL) is connected to a plurality of row groups (PL) among the row groups (in the X direction, best seen in combination of Figs. 7 and 12).
Referring to claim 12, the reference further discloses that:
each of the channel structures (PL) further includes dielectric BCL (Fig. 3, para [50]), which may be termed a gate dielectric layer as claimed, disposed between the gate electrodes (GL) and the channel layer (CHL), and an upper end of the gate dielectric layer (BCL) is positioned at a level that is substantially the same as that of an upper end of the channel layer (CHL).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. §103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim 8 is rejected under 35 U.S.C. §103 as being unpatentable over Kim U.S. Patent Application Publication 2025/0095694 A1 (the ‘694 reference) in view of Chiang et al. U.S. Patent Application Publication 20210408293.
Referring to claim 8, the reference discloses the source lines as detailed above for claim 1, but does not disclose that the source lines include a metal material.
Chiang, in disclosing a semiconductor device comprising a source line, discloses that the source line is made of a metal (para [124]), thereby teaching that metal is a material suitable for a source line. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have form the reference’s source lines utilizing metal. One would have been motivated to make such a modification in view of the teachings in Chiang that metal is a material suitable for a source line.
Allowable Subject Matter
4. Claims 16-20 are allowable over the prior art of record.
Claims 6-7, 9 and 13-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious a semiconductor device and an electronic system with all exclusive limitations as recited in claims 6, 7, 9, 13, 14, 15, 16 and 19, which may be characterized (claim 6) in that the source lines have an upper width greater than a lower width, and in that lower portions of the source lines are recessed into upper portions of the channel structures, (claim 7) the source lines have a lower width greater than an upper width, (claim 9) in that the second semiconductor structure further includes a via contact plug connecting each of the source lines and the channel layer to each other, (claim 13) the channel layer includes a contact doped region, and the contact doped region is in contact with each of the source lines, (claim 14) in that the source lines include block shared source lines overlapping the isolation regions and extending in the second direction, (claim 15) the gate electrodes include memory gate electrodes forming memory cells and at least one upper gate electrode positioned below the memory gate electrodes, and (claims 16 and 19) a second selection channel structure is selected from among the plurality of first selection channel structures by an electrical signal applied to the channel layer through the source lines.
Conclusion
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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09-09-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818
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