DETAILED ACTION
Response to Amendment
Applicants’ response filed 04/24/26 has been considered.
Claims 1, 11, and 19 have been amended. Claims 2 cancelled. Claims 1, 3-20 are pending.
Response to the Arguments
Applicants’ arguments have been fully considered but they are not persuasive. The Applicant’s argument pertains to the new claim limitation which has been addressed in appropriate claim rejections below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35
U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any
correction of the statutory basis for the rejection will not be considered a new ground of
rejection if the prior art relied upon, and the rationale supporting the rejection, would be
the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness
rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102 of this title, if the
differences between the claimed invention and the prior art are such that the claimed
invention as a whole would have been obvious before the effective filing date of the
claimed invention to a person having ordinary skill in the art to which the claimed
invention pertains. Patentability shall not be negated by the manner in which the
invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Ellis et al. “herein Ellis” (U.S. PN: 9,250,995) in view of Suzuki et al. “herein Suzuki” (U.S. PN: 7,739,559) and further in view of Cheng et al. “herein” Cheng (U.S. PN: 7,676,729).
Ellis substantially teaches or discloses a system comprising logic structure being configured to translate a current logical address to a current physical address (abstract and (see col. 5, lines 25-32, col. 7, lines 17-22 and col. 11, lines 33-50). However, Elli does not explicitly
teach a first register configured to hold the current physical address; a second register configured
to hold an address of a failed physical memory location; a comparator configured to compare the
current physical address in the first register with the address of the failed physical memory
location held in the second register. Suzuki, in an analogous art, teaches a first register configured to hold the current physical address; a second register configured to hold an address
of a failed physical memory location; a comparator configured to compare the current physical
address in the first register with the address of the failed physical memory location held in the
second register (see col. 3, lines 44-67 and col. 7, lines 38-48).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Ellis with the teachings of Suzuki by comparing the current physical address in the first register with the address of the failed physical memory location held in the second register.
This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention because one of ordinary skill in the art would have recognized that comparing the current physical address in the first register with the address of the failed physical memory location held in the second register would have heighten the correction efficiency and increase the flexibility of configuration.
The combination of teachings above does not explicitly teach wherein the bounds for physical address locations marked as failing and removed from use by the system are determined in connection with ignoring bit position values of the current physical address having exhibited previous errors, the physical address locations marked as failing and removed from use by the system being inclusive of those that consecutively span from the address stored in the second register to the address stored in the first register holding the current physical address. Cheng in an analogous art, teaches bounds for physical address locations marked as failing and removed from use by the system are determined in connection with ignoring bit position values of the current physical address having exhibited previous errors, the physical address locations marked as failing and removed from use by the system “sparing controller 230 may set the bound address to one extreme of the address range of the failed memory chip at the beginning of the sparing operation and as the sparing operation proceeds, progressively advance the bound address toward the other extreme of the address range until the entire contents of the failed memory chip have been remapped to the spare memory chip. During the sparing operation, arbiter 210 may determine how to handle a memory request from the host depending on a comparison of the values of address 242 and the bound address, and if the request is a read request or a write request (see col. 5, lines 7-18 ) and further a sparing process 400 that may be used to remap a failed memory chip to a spare memory chip. In the illustrated embodiment, a sparing operation is used to spare an entire memory chip and consists of a series of individual sparing transactions, one for each memory address. Sparing begins when failures of a given memory chip exceed a threshold value or as otherwise determined by software executing on host 110 (block 410). Next, the value of a bound address may be set to the lowest address of the failed memory (block 420) and data read from the location indicated by the bound address (block 430). Once the data has been read, errors may be corrected (block 440), such as through the use of error-correcting codes. Corrected data may then be written to a spare memory chip (block 450). If the value of the bound address is not equal to the highest address of the failed memory (decision block 460), the bound address may be incremented (block 470) and data may be read from the location indicated by the next address (block 430). Once the bound address determined to have reached the highest address of the failed memory (decision block 460), sparing is completed (block 480)” (see col. 6, lines 26-46).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Ellis with the teachings of Cheng by performing bounds for physical address locations marked as failing and removed from use by the system are determined in connection with ignoring bit position values of the current physical address having exhibited previous errors, the physical address locations marked as failing and removed from use by the system.
This modification would have been obvious to one of ordinary skills in the art before the effective filing date of the invention because one of ordinary skill in the art would have reduced the power consumption of the memory.
As per claim 3:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach bounds lie on a
single memory device (see figure 2 in Cheng).
As per claim 4:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach an error
correction code (ECC) controller coupled to the logic structure (see col. 5, lines 4-16 in Ellis)
As per claim 5:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach compute
express link (CXL) interface management circuitry coupled to the ECC (see col. 3 lines 55-65
and col. 5, lines 17-23 in Ellis).
As per claim 6:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach the ECC
controller corrects data errors held at the current physical address (see col. 8, lines 1-9 in Ellis).
As per claim 7:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach ECC controller
is configured to correct data errors according to a Reed - Solomon (RS) coding scheme (see col.
5, lines 4-16 in Ellis).
As per claim 8:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach ECC controller
comprises an ECC encoding system coupled to ECC decoding system (see col. 7, lines 32-41 and
col. 7, lines 63-67 to col. 8, lines 1-9 in Ellis).
As per claim 9:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach comparator
comprises a plurality of AND gates (see col. 7, lines 38-51).
As per claim 10:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach a dynamic
random-access memory (DRAM) system (see figure 1 element 118 and col. 5, lines 64-67).
Claim 11, and 19, these claims are directed to a method and computer readable medium
and are rejected for the same reasons as in claim 1.
As per claim 12:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach
determining whether a register at the current physical address holds faulty data as indicated in
connection with using an error correction code (ECC) scheme (see col. 5, lines 4-16 in Ellis).
As per claim 13:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach EEC scheme is
configured to correct errors using parity symbols (see col. 7, lines 32-46).
As per claim 14:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach wherein the
parity symbols include parity check symbols according to one or more Reed-Solomon (RS)
codes (see col. 5, lines 4-16 in Ellis).
As per claim 15:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach using the RS
codes to detect and correct multiple symbol errors at the current physical address (see col. 5,
lines 4-16 in Ellis).
As per claim 16:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach wherein the
boundary includes memory locations on more than one device (see col. 5, lines 7-18 in Cheng).
As per claim 17:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach device is a
memory device selected from the group consisting of a magnetic hard disk, random access
memory (RAM), read-only memory (ROM), dynamic random-access memory (DRAM),
synchronous dynamic RAM (SDRAM), static RAM (SRAM), and flash memory (see col. 13,
lines 17-36 in Ellis).
As per claim 18:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach wherein
DRAM memory is a compute express link (CXL) DRAM memory (see col. 3 lines 55-65 and
col. 5, lines 17-23 in Ellis).
As per claim 20:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach wherein the
boundary includes memory locations on more than one device (see col. 5, lines 7-18 in Cheng).
Conclusion
The following List of prior art, made of record and not relied upon, is/are considered pertinent to applicant's disclosure:
MacLaren et al. U.S. PN: 10,579,470) describes at operation 610, the memory controller 106 indicates an address error with respect to the memory transaction based on the memory controller 106 determining, at operation 608, whether the plurality of error checking results indicate a multiple data error condition. As noted herein, an address error (e.g., erroneously mapping /translating of inline memory addresses) with respect to a memory command can result in a mismatch with respect to the primary data and error checking data being operated upon by the memory command. To provide a contiguous address space, the ECC data storage in the memory (e.g., 408) may be mapped out of the primary data address space.
Chandramouliet al. (U.S. PN: 7,500,081) teach referring to FIG. 3, controller 12 sets a
block counter to zero (310) to start a latch update process on power up. The block counter value
represents the current physical block address of physical memory 13 being processed. Status
decision unit 115 of controller 12 reads bad block information from region 150 of physical
memory 13 (320) to determine whether the current block is bad (330). Status decision unit 115
may compare the physical address of the current block with the list of addresses stored
in region 150 to determine if there is a match. If the block is bad (e.g., a match is found),
controller 12 marks bad status field 44 of block status latches 145 for the block (370) and
increments the block counter by one (380).
Young (US 2007/0118778) describes when the processor 102 detects a failing RAM address
location. the processor 102 programs one of the N address registers with the failing memory
address. For example, if the processor 102 writes to a failed (or failing) address location, data is
written into redundant storage. Data may also simultaneously be written into the failed
address location if the memory 108 is not blocked. Alternately, the memory 108 may be
blocked when the failing address is accessed. Blocking failed address locations may
reduce the power consumption of memory 108. When the processor 102 reads from a
failed address location, the memory defect handler 110 may multiplex data from the
corresponding redundant storage registers onto the signal RDATA (through a readback bus)
instead of from failing memory
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Esaw T. Abraham whose telephone number is (571) 272-3812. The examiner can normally be reached on M-F 8am-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Albert DeCady can be reached on (571) 272-3819. The fax phone number for the organization where this application or proceeding is assigned is (703) 872-9306.
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/ESAW T ABRAHAM/Primary Examiner, Art Unit 2112
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