DETAILED ACTION
FINAL REJECTION
Response to Amendment
Applicant's response filed 01/06/2025 has been considered.
Claims 1-20 have been amended. Claims 1-20 are pending.
Rejections under 35 USC 112 are withdrawn in light of amendments.
Rejections under 35 USC 103 are withdrawn in light of amendments.
Applicant’s amendment claim(s) 1-20 have been fully considered and upon further consideration, a new ground(s) of rejection is made under 35 USC 103.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Ellis et al. “herein Ellis” (U.S. PN: 9,250,995) in view of Suzuki et al. “herein Suzuki” (U.S. PN: 7,739,559) and further in view of Cheng et al. “herein” Cheng (U.S. PN: 7,676,729).
As per claim 1:
Ellis substantially teaches or discloses a system comprising logic structure being configured to translate a current logical address to a current physical address (abstract and (see Col. 5, lines 25-32, col. 7, lines 17-22 and col. 11, lines 33-50). However, Elli does not explicitly teach a first register configured to hold the current physical address; a second register configured to hold an address of a failed physical memory location; a comparator configured to compare the current physical address in the first register with the address of the failed physical memory location held in the second register. Suzuki, in an analogous art, teaches a first register configured to hold the current physical address; a second register configured to hold an address of a failed physical memory location; a comparator configured to compare the current physical address in the first register with the address of the failed physical memory location held in the second register (see col. 3, lines 44-67 and col. 7, lines 38-48). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Ellis with the teachings of Suzuki by comparing the current physical address in the first register with the address of the failed physical memory location held in the second register. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention because one of ordinary skill in the art would have recognized that comparing the current physical address in the first register with the address of the failed physical memory location held in the second register would have heighten the correction efficiency and increase the flexibility of configuration. The combination of teachings above does not explicitly teach holding physical address bits defining bounds over a range of physical address locations marked as failing and removed from use by the system in connection with a determination that data held at the current physical address has been corrected. Cheng in an analogous art, teaches bounding over a range of physical address locations marked as failing and removed from use by the system (see col. 5, lines 7-18). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Ellis with the teachings of Cheng by bounding over a range of physical address locations marked as failing and removed from use by the system. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention because one of ordinary skill in the art would have recognized that bounding over a range of physical address locations marked as failing and removed from use by the system would have reduced the power consumption of the memory.
As per claim 2:
The combination of Ellis, Suzuki, and Cheng teach in the above rejection teach the bounds for physical address locations marked as failing and removed from use by the system span the address stored in the second register and the address stored in the first register holding the current physical address (see col. 5, lines 5-18 in Cheng).
As per claim 3:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach bounds lie on a single memory device (see figure 2 in Cheng).
As per claim 4:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach an error correction code (ECC) controller coupled to the logic structure (see col. 5, lines 4-16 in Ellis)
As per claim 5:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach compute express link (CXL) interface management circuitry coupled to the ECC (see col. 3 lines 55-65 and col. 5, lines 17-23 in Ellis).
As per claim 6:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach the ECC controller corrects data errors held at the current physical address (see col. 8, lines 1-9 in Ellis).
As per claim 7:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach ECC controller is configured to correct data errors according to a Reed- Solomon (RS) coding scheme (see col. 5, lines 4-16 in Ellis).
As per claim 8:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach ECC controller comprises an ECC encoding system coupled to ECC decoding system (see col. 7, lines 32-41 and col. 7, lines 63-67 to col. 8, lines 1-9 in Ellis).
As per claim 9:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach comparator comprises a plurality of AND gates (see col. 7, lines 38-51).
As per claim 10:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach a dynamic random-access memory (DRAM) system (see figure 1 element 118 and col. 5, lines 64-67).
Claim 11, and 19, these claims are directed to a method and computer readable medium and are rejected for the same reasons as in claim 1.
As per claim 12:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach
determining whether a register at the current physical address holds faulty data as indicated in connection with using an error correction code (ECC) scheme (see col. 5, lines 4-16 in Ellis).
As per claim 13:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach EEC scheme is configured to correct errors using parity symbols (see col. 7, lines 32-46).
As per claim 14:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach wherein the parity symbols include parity check symbols according to one or more Reed-Solomon (RS) codes (see col. 5, lines 4-16 in Ellis).
As per claim 15:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach using the RS codes to detect and correct multiple symbol errors at the current physical address (see col. 5, lines 4-16 in Ellis).
As per claim 16:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach wherein the boundary includes memory locations on more than one device (see col. 5, lines 7-18 in Cheng).
As per claim 17:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach device is a memory device selected from the group consisting of a magnetic hard disk, random access memory (RAM), read-only memory (ROM), dynamic random-access memory (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), and flash memory (see col. 13, lines 17-36 in Ellis).
As per claim 18:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach wherein DRAM memory is a compute express link (CXL) DRAM memory (see col. 3 lines 55-65 and col. 5, lines 17-23 in Ellis).
As per claim 20:
The combination of Ellis, Suzuki, and Cheng in the above rejection teach wherein the boundary includes memory locations on more than one device (see col. 5, lines 7-18 in Cheng).
Examiner's Note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. SEE MPEP 2141.02 [R-5] VI. PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS: A prior art reference must be considered in its entirety, i.e., as a whole, including portions that would lead away from the claimed invention. W.L. Gore & Associates, Inc. v. Garlock, Inc., 721 F.2d 1540, 220 USPQ 303 (Fed. Cir. 1983), cert, denied, 469 U.S. 851 (1984) In re Fulton, 391 F.3d 1195, 1201,73 USPQ2d 1141, 1146 (Fed. Cir. 2004). See also MPEP §2123.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The following List of prior art, made of record and not relied upon, is/are considered pertinent to applicant's disclosure:
MacLaren et al. U.S. PN: 10,579,470) describes at operation 610, the memory controller 106 indicates an address error with respect to the memory transaction based on the memory controller 106 determining, at operation 608, whether the plurality of error checking results indicates a multiple data error condition. As noted herein, an address error (e.g., erroneously mapping/translating of inline memory addresses) with respect to a memory command can result in a mismatch with respect to the primary data and error checking data being operated upon by the memory command. In order to provide a contiguous address space, the ECC data storage in the memory (e.g., 408) may be mapped out of the primary data address space.
Chandramouli et al. (U.S. PN: 7,500,081) teach referring back to FIG. 3, controller 12 sets a block counter to zero (310) to start a latch update process on power up. The block counter value represents the current physical block address of physical memory 13 being processed. Status decision unit 115 of controller 12 reads bad block information from region 150 of physical memory 13 (320) to determine whether the current block is bad (330). Status decision unit 115 may compare the physical address of the current block with the list of addresses stored in region 150 to determine if there is a match. If the block is bad (e.g., a match is found), controller 12 marks bad status field 44 of block status latches 145 for the block (370) and increments the block counter by one (380).
Young (US 2007/0118778) describe when the processor 102 detects a failing RAM address location, the processor 102 programs one of the N address registers with the failing memory address. For example, if the processor 102 writes to a failed (or failing) address location, data is written into the redundant storage. Data may also simultaneously be written into the failed address location if the memory 108 is not blocked. Alternately, the memory 108 may be blocked when the failing address is accessed. Blocking failed address locations may reduce the power consumption of the memory 108. When the processor 102 reads from a failed address location, the memory defect handler 110 may multiplex data from the corresponding redundant storage register onto the signal RDATA (through a readback bus) instead of from the failing memory
Takehara et al. (U.S. PN: 8,131,900) teaches the error address processing unit 22 includes an error address register 22a which temporarily stores error address data obtained at the time when a "difference-present signal" is output from the bus signal abnormality processing unit 23, and an address comparing unit 22b which compares the temporarily stored address with an address of an instruction to be executed next, to generate a signal for deleting, for example, the next instruction so that the error address data is not used.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ESAW T ABRAHAM whose telephone number is (571)272-3812. The examiner can normally be reached on 8AM-4:30PM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner'ssupervisor, Albert DeCady can be reached on (571) 272-3819. The fax phone number for the organization where this application or proceeding is assigned is (703) 872-9306.
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/ESAW T ABRAHAM/Primary Examiner,
Art Unit 2112