Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/23/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 16 recite the “the indication to output the processed video frame.” There is insufficient antecedent basis for this limitation in the claim.
Claims 1 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claims define “one or more memories,” store decoded video frame in “a memory,” retrieve the decoded video frame from “the memory,” and send the processed video frame to “display circuitry” without storing it in “the memory.” The claim language is ambiguous because the broadest reasonable interpretation of “display circuitry” comprises memory, such as a display buffer. The broadest reasonable interpretation of the claims also comprises storing the processed video frame in another one of the “one or more memories,” other than the memory that the decoded frame was stored to/retrieved from. Therefore, the claims do not make clear whether the claims are not stored in any memory at all post-processing, or stored in a different memory.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-6, 11-16, 19-21, 26-30 are rejected under 35 U.S.C. 103 as being unpatentable over Bhaskaran (US PG Publication 2013/0251281) in view of Aoyama (US PG Publication 2014/0178053).
Regarding Claim 1, Bhaskaran (US PG Publication 2013/0251281) discloses an apparatus for video processing, the apparatus (device 10 include, but are not limited to, video devices such as media players, set-top boxes, wireless handsets such as mobile telephones, personal digital assistants (PDAs), desktop computers, laptop computers, gaming consoles, video conferencing units, tablet computing devices [0018]) comprising:
one or more memories (device 10 may include display 12, video processor 14, graphics processing unit (GPU) 16, video encoder/decoder (codec) 18, memory 20, and post processor 22 [0018]);
and one or more processors (device 10 may include display 12, video processor 14, graphics processing unit (GPU) 16, video encoder/decoder (codec) 18, memory 20, and post processor 22. [0018]) coupled to the one or more memories (Fig. 1), the one or more processors being configured (software [0055]) to:
decode encoded video frame data to generate a decoded video frame (video codec 18 may decode received video content [0028]);
store the decoded video frame in a memory of the one or more memories (Video codec 18 may store these series of images in memory 20 [0028]; memory 20 may store image 24 which is a constructed image generated from video codec 18 [0021]);
…;
retrieve the decoded video frame from the memory (post processor 22 may retrieve images 24 from memory 20 [0028], [0021]) …;
modify … at least one pixel characteristic of the decoded video frame (contrast enhancement, sharpening and blurring, color enhancement [0017]) to generate the processed video frame (post processor 22 may enhance images 24 [0028]) …, wherein the at least one pixel characteristic is distinct form the size (contrast enhancement, sharpening and blurring, color enhancement [0017] is different than size);
and send the processed video frame (and display them via display 12 [0028]) to display circuitry associated with the display (present enhanced image 26 on display 12 [0021]) without storing the processed video frame in the memory (there is no depiction or description of memory between post processor 22 and display 12, Fig. 1, [0021]) ….
Bhaskaran does not disclose but Aoyama (US PG Publication 2014/0178053) teaches
receive an indication (display timing is YES at S1404, Fig. 14, [0114]; Fig. 14 implements step S1305 of Fig. 13, which is “generate a display screen” [0111], [0107]) that a processed video frame corresponding to the decoded video frame (resized decoded data, S1405, Fig. 14, [0144]) is to be displayed on a display (at the time of playback, Fig. 13, [0104]);
retrieve the decoded video frame from the memory (decoded moving image data in the memory 203, S1403, Fig. 14, [0113]; reduce the size of the decoded moving image data of one frame stored in memory 203, Fig. 14, [0114]) in response to the indication (if the display timing has arrived [0114], S1404, Fig. 14);
modify a size (reduce the size of, Fig. 14, [0114]) of the decoded video frame (the decoded moving image data of one frame stored in memory 203, Fig. 14, [0114]) … in response to the indication (at a timing based on a display clock [0112]);
and send the processed video frame (displays the screen on the display unit 208, step S1306 [0107]) … in response to the indication to output the processed video frame (display clock determined in accordance with the ability of the display unit 208 [0106]; display timing based on a display clock has arrived, step S1404, Fig. 14, [0114]).
One of ordinary skill in the art before the application was filed would have been motivated to resize the decoded image of Baskaran at the timing of the display clock as in Aoyama because Aoyama teaches that doing so minimizes the storage area for storing resized frames, and memory can be efficiently used [0119], improving the efficiency of the playback system.
Regarding Claim 4, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1, wherein, to output the processed video frame to the display circuitry, the one or more processors are configured to display the processed video frame on the display (present enhanced image 26 on display 12 [0021]).
Regarding Claim 5, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1, wherein, to output the processed video frame to the display circuitry, the one or more processors are configured to convey the processed video frame to the display (display [images] via display 12 [0027], see arrow between post-processor 22 and display 12 indicating conveyance).
Regarding Claim 6, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1, wherein, to output the processed video frame to the display circuitry, the one or more processors are configured to display the processed video frame on the display (display [images] via display 12 [0027]).
Regarding Claim 11, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1, wherein to modify the at least one pixel characteristic of the decoded video frame, the one or more processors are configured to modify at least one of a tone, a sharpness, a brightness, a contrast, or a color saturation of at least a portion of the decoded video frame (contrast enhancement, sharpening and blurring, color enhancement [0017]).
Regarding Claim 12, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1.
Bhaskaran does not disclose but Aoyama (US PG Publication 2014/0178053) teaches wherein, to decode the encoded video frame data, the one or more processors are configured to delay post-processing of the decoded video frame until after the receipt of the indication (display timing is YES at S1404, Fig. 14, [0114]; otherwise loop, Fig. 14).
One of ordinary skill in the art before the application was filed would have been motivated to post-process the decoded image of Baskaran based on the display clock of Aoyama because Aoyama teaches that it minimizes the storage area for storing resized frames, and memory can be efficiently used [0119], improving the efficiency of the playback system.
Regarding Claim 13, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1, wherein, to store the decoded video frame in the memory, the one or more processors are configured to avoid storing any modified instance of the decoded video frame in the memory (there is no depiction or description of memory between post processor 22 and display 12, Fig. 1, [0021]).
Regarding Claim 14, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1, wherein, to send the processed video frame to the display circuitry, the one or more processors are configured to send the processed video frame directly to the display circuitry (because the enhanced image from the post-processor is output to the display, it is not in “the memory” where the decoded image is extracted from, Fig. 1).
Regarding Claim 15, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1, wherein the one or more processors are configured to:
receive the encoded video frame data from an encoder (decoder 193 receives encoded video and decodes/ decompresses the encoded video [0042]).
Regarding Claim 16, the claim is rejected on the grounds provided in Claim 1.
Regarding Claim 19, the claim is rejected on the grounds provided in Claim 4.
Regarding Claim 20, the claim is rejected on the grounds provided in Claim 5.
Regarding Claim 21, the claim is rejected on the grounds provided in Claim 6.
Regarding Claim 26, the claim is rejected on the grounds provided in Claim 11.
Regarding Claim 27, the claim is rejected on the grounds provided in Claim 12.
Regarding Claim 28, the claim is rejected on the grounds provided in Claim 13.
Regarding Claim 29, the claim is rejected on the grounds provided in Claim 14.
Regarding Claim 30, the claim is rejected on the grounds provided in Claim 15.
Claim(s) 2-3, 7, 17-18, 22 are rejected under 35 U.S.C. 103 as being unpatentable over Bhaskaran (US PG Publication 2013/0251281) in view of Aoyama (US PG Publication 2014/0178053) and Abeydeera (NPL “4K Real-Time HEVC Decoder on an FPGA,” IEEE 2016).
Regarding Claim 2, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1.
Bhaskaran does not disclose, but Abeydeera (NPL “4K Real-Time HEVC Decoder on an FPGA,” IEEE 2016) teaches wherein, to decode the encoded video frame data, the one or more processors (FPGA, title) are configured to process the encoded video frame data using at least one video stream processor that parses a syntax of the encoded video frame data (defined in the Spec as performing bitstream parsing, separating a network abstraction layer, and a slice layer and entropy coding operations, Spec at [0124]; decoder front end having header parse, CABAC decoder, Slice Segment Data FSM, Fig. 1) and at least one video pixel processor that decodes the encoded video frame data based on the parsed syntax (in the Spec, VPP does not have a definition, but the decoder uses it to generate a reconstructed frame, Spec at [0155]; decoder back end having motion compensation, reconstruction, and filtering, Fig. 1).
One of ordinary skill in the art before the application was filed would have been motivated to implement the decoder of Bhaskaran using the architecture of Abeydeera because Abeydeera teaches that it achieves real-time 4K decoding on a commercially available chip and can be adapted to an ASIC environment, suggesting it is ready for commercial development (p. 237 left column).
Regarding Claim 3, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1, wherein, to output the processed video frame to the display circuitry (present enhanced image 26 on display 12 [0021]) ….
Bhaskaran does not disclose, but Abeydeera (NPL “4K Real-Time HEVC Decoder on an FPGA,” IEEE 2016) teaches one or more processors are configured to store the processed video frame in a display buffer of the display circuitry, wherein the display buffer is distinct from the memory (for displaying purpose, the frames are written to display buffer, Section V, p. 246 left column).
One of ordinary skill in the art before the application was filed would have been motivated to implement the decoder of Bhaskaran using the architecture of Abeydeera because Abeydeera teaches that it achieves real-time 4K decoding on a commercially available chip and can be adapted to an ASIC environment, suggesting it is ready for commercial development (p. 237 left column).
Regarding Claim 7, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1.
Bhaskaran does not disclose, but Abeydeera (NPL “4K Real-Time HEVC Decoder on an FPGA,” IEEE 2016) teaches wherein the memory is a Double Data Rate memory (The output frames are sent to an RPB that resides in the external DDR3 SDRAM, Section V, p. 246 left column).
One of ordinary skill in the art before the application was filed would have been motivated to implement the decoder of Bhaskaran using the architecture of Abeydeera because Abeydeera teaches that it achieves real-time 4K decoding on a commercially available chip and can be adapted to an ASIC environment, suggesting it is ready for commercial development (p. 237 left column).
Regarding Claim 17, the claim is rejected on the grounds provided in Claim 2.
Regarding Claim 18, the claim is rejected on the grounds provided in Claim 3.
Regarding Claim 22, the claim is rejected on the grounds provided in Claim 7.
Claim(s) 8, 10, 23, 25 are rejected under 35 U.S.C. 103 as being unpatentable over Bhaskaran (US PG Publication 2013/0251281) in view of Aoyama (US PG Publication 2014/0178053) and Sun (US 20180103261 A1).
Regarding Claim 8, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1.
Bhaskaran does not disclose, but Sun (US 20180103261 A1) teaches wherein to modify the at least one pixel characteristic of the decoded video frame, the one or more processors are configured to apply a color space conversion to the decoded video frame to convert the decoded video frame from a first color space to a second color space that is associated with the display (Post-processing can also include upsampling of chroma sample values and/or color space conversion [0085]).
One of ordinary skill in the art before the application was filed would have been motivated to supplement Bhaskaran with resolution and color-space conversion, as taught by Sun, because these are commonly known and used post-processing algorithms and implementing them generates predictable results (i.e., images in the new color space or new resolution).
Regarding Claim 10, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1.
Bhaskaran does not disclose, but Sun (US 20180103261 A1) teaches wherein to modify the at least one pixel characteristic of the decoded video frame, the one or more processors are configured to add film grain to the decoded video frame (post processing includes film-grain reproduction filtering, [0084]).
One of ordinary skill in the art before the application was filed would have been motivated to supplement Bhaskaran with resolution and color-space conversion, as taught by Sun, because these are commonly known and used post-processing algorithms and implementing them generates predictable results (i.e., images in the new color space or new resolution).
Regarding Claim 23, the claim is rejected on the grounds provided in Claim 8.
Regarding Claim 25, the claim is rejected on the grounds provided in Claim 10.
Claim(s) 9 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Bhaskaran (US PG Publication 2013/0251281) in view of Aoyama (US PG Publication 2014/0178053) and Doken (WO 2012058394 A1)
Regarding Claim 9, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1.
Bhaskaran does not disclose, but Doken (WO 2012058394 A1) teaches wherein to modify the at least one characteristic of the decoded video frame, the one or more processors are configured to apply a format conversion to the decoded video frame to convert the decoded video frame from a first format to a second format that is associated with the display (post-processor can encode/transcode into any format, p. 12 lines 25 - end).
One of ordinary skill in the art before the application was filed would have been motivated to supplement Bhaskaran with format conversion, as taught by Doken, because these are commonly known and used post-processing algorithms and implementing them generates predictable results (i.e., images in the new format).
Regarding Claim 24, the claim is rejected on the grounds provided in Claim 9.
Response to Arguments
Applicant’s remarks filed 2/5/2026 are unpersuasive.
Applicant submits that the combination of reference does not teach the amended claims. Remarks at 10, 11. Applicant supplies neither evidence nor reasoning. I.e., there are no arguments. Therefore, the remarks are unpersuasive.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20140180458 A1 – reducing the power consumed by the processor by delaying processing
US 20100158099 A1 - content adaptive postprocessor to change bitrate(s) and resolution(s) depending upon the capabilities of interface
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/SHADAN E HAGHANI/ Examiner, Art Unit 2485