Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 11-22, 26-30 are rejected under 35 U.S.C. 103 as being unpatentable over Bhaskaran (US PG Publication 2013/0251281) in view of Aoyama (US PG Publication 2014/0178053) and Abeydeera (NPL “4K Real-Time HEVC Decoder on an FPGA,” IEEE 2016).
Regarding Claim 1, Bhaskaran (US PG Publication 2013/0251281) discloses an apparatus for video processing, the apparatus (device 10 include, but are not limited to, video devices such as media players, set-top boxes, wireless handsets such as mobile telephones, personal digital assistants (PDAs), desktop computers, laptop computers, gaming consoles, video conferencing units, tablet computing devices [0018]) comprising:
one or more memories (device 10 may include display 12, video processor 14, graphics processing unit (GPU) 16, video encoder/decoder (codec) 18, memory 20, and post processor 22 [0018]), including a random access memory (RAM) (memory 20, Fig. 7, is RAM [0024]);
and one or more processors (device 10 may include display 12, video processor 14, graphics processing unit (GPU) 16, video encoder/decoder (codec) 18, memory 20, and post processor 22. [0018]) coupled to the one or more memories (Fig. 1), the one or more processors being configured (software [0055]) to:
decode encoded video frame data to generate a decoded video frame (video codec 18 may decode received video content [0028]), the encoded video frame data associated with a video in an encoded form (constructed image generated from video codec 18 [0021]), the decoded video frame associated with the video in a decoded form (constructed image generated from video codec 18 [0021]));
store the decoded video frame (Video codec 18 may store these series of images in memory 20 [0028]; memory 20 may store image 24 which is a constructed image generated from video codec 18 [0021]) in the RAM (memory 20, Fig. 7, is RAM [0024]);
…;
retrieve the decoded video frame (post processor 22 may retrieve images 24 from memory 20 [0028], [0021]) from the RAM (memory 20, Fig. 7, is RAM [0024]) …;
modify … at least one pixel characteristic of the decoded video frame (contrast enhancement, sharpening and blurring, color enhancement [0017]) to generate the processed video frame (post processor 22 may enhance images 24 [0028]) …, wherein the at least one pixel characteristic is distinct form the size (contrast enhancement, sharpening and blurring, color enhancement [0017] is different than size), and wherein modification of the at least one pixel characteristic (output of enhancement unit 36 is the pixel values for enhanced image 26 [0055]; post processor 22 having enhancement unit 36, Fig. 2; post processor 22 receives image 24 and outputs enhanced image 26 [0021]) is based on a parameter of the video (pixels of image 24 are modified by selectable or pre-programmed weights [0063]; and the value of depth map and perception map [0063]);
and send the processed video frame (and display them via display 12 [0028]) to … display (present enhanced image 26 on display 12 [0021]) without storing the processed video frame in the RAM (there is no depiction or description of memory between post processor 22 and display 12, Fig. 1, [0021]), wherein the display buffer is distinct from the RAM (inherent; display buffer is part of a display, and memory 20 is not part of the display).
Bhaskaran does not disclose but Aoyama (US PG Publication 2014/0178053) teaches
receive an indication (display timing is YES at S1404, Fig. 14, [0114]; Fig. 14 implements step S1305 of Fig. 13, which is “generate a display screen” [0111], [0107]) that a processed video frame corresponding to the decoded video frame (resized decoded data, S1405, Fig. 14, [0144]) is in a next sequence of frames of the video to be displayed on a display (at the time of playback, Fig. 13, [0104]; display clock determined in accordance with the ability of the display unit 208 [0106]; display timing based on a display clock has arrived, step S1404, Fig. 14, [0114]);
retrieve the decoded video frame … (decoded moving image data in the memory 203, S1403, Fig. 14, [0113]; reduce the size of the decoded moving image data of one frame stored in memory 203, Fig. 14, [0114]) in response to the indication (if the display timing has arrived [0114], S1404, Fig. 14);
modify a size (reduce the size of, Fig. 14, [0114]) of the decoded video frame (the decoded moving image data of one frame stored in memory 203, Fig. 14, [0114]) to generate the processed video frame (resized decoded data, S1405, Fig. 14, [0144]) in response to the indication (at a timing based on a display clock [0112]);
and send the processed video frame (execute processing for generating the display screen using the decoded moving image data [0107]) to display (displays the screen on the display unit 208, step S1306 [0107]).
Bhaskaran does not disclose but Abeydeera (NPL “4K Real-Time HEVC Decoder on an FPGA,” IEEE 2016) teaches a display buffer associated with the display (for displaying purpose, the frames are written to display buffer, Section V, p. 246 left column).
One of ordinary skill in the art before the application was filed would have been motivated to resize the decoded image of Baskaran at the timing of the display clock as in Aoyama because Aoyama teaches that doing so minimizes the storage area for storing resized frames, and memory can be efficiently used [0119], improving the efficiency of the playback system.
One of ordinary skill in the art before the application was filed would have been motivated to implement the decoder of Bhaskaran using the architecture of Abeydeera because Abeydeera teaches that it achieves real-time 4K decoding on a commercially available chip and can be adapted to an ASIC environment, suggesting it is ready for commercial development (p. 237 left column).
Regarding Claim 2, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1.
Bhaskaran does not disclose, but Abeydeera (NPL “4K Real-Time HEVC Decoder on an FPGA,” IEEE 2016) teaches wherein, to decode the encoded video frame data, the one or more processors (FPGA, title) are configured to process the encoded video frame data using at least one video stream processor that parses a syntax of the encoded video frame data (defined in the Spec as performing bitstream parsing, separating a network abstraction layer, and a slice layer and entropy coding operations, Spec at [0124]; decoder front end having header parse, CABAC decoder, Slice Segment Data FSM, Fig. 1) and at least one video pixel processor that decodes the encoded video frame data based on the parsed syntax (in the Spec, VPP does not have a definition, but the decoder uses it to generate a reconstructed frame, Spec at [0155]; decoder back end having motion compensation, reconstruction, and filtering, Fig. 1).
One of ordinary skill in the art before the application was filed would have been motivated to implement the decoder of Bhaskaran using the architecture of Abeydeera because Abeydeera teaches that it achieves real-time 4K decoding on a commercially available chip and can be adapted to an ASIC environment, suggesting it is ready for commercial development (p. 237 left column).
Regarding Claim 3, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1.
Bhaskaran does not disclose, but Abeydeera (NPL “4K Real-Time HEVC Decoder on an FPGA,” IEEE 2016) teaches wherein, to send the processed video frame to the display buffer (display buffer, Section V, p. 246 left column) one or more processors are configured to store the processed video frame in the display buffer to cause the display to display the processed video frame (for displaying purpose, the frames are written to display buffer, Section V, p. 246 left column).
One of ordinary skill in the art before the application was filed would have been motivated to implement the decoder of Bhaskaran using the architecture of Abeydeera because Abeydeera teaches that it achieves real-time 4K decoding on a commercially available chip and can be adapted to an ASIC environment, suggesting it is ready for commercial development (p. 237 left column).
Regarding Claim 4, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1.
Bhaskaran does not disclose, but Abeydeera (NPL “4K Real-Time HEVC Decoder on an FPGA,” IEEE 2016) teaches wherein, to send the processed video frame to the display buffer, the one or more processors are configured to display the processed video frame on the display through the display buffer (for displaying purpose, the frames are written to display buffer, Section V, p. 246 left column).
One of ordinary skill in the art before the application was filed would have been motivated to implement the decoder of Bhaskaran using the architecture of Abeydeera because Abeydeera teaches that it achieves real-time 4K decoding on a commercially available chip and can be adapted to an ASIC environment, suggesting it is ready for commercial development (p. 237 left column).
Regarding Claim 5, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1.
Bhaskaran does not disclose, but Abeydeera (NPL “4K Real-Time HEVC Decoder on an FPGA,” IEEE 2016) teaches wherein, to send the processed video frame to the display buffer, the one or more processors are configured to convey the processed video frame to the display through the display buffer (for displaying purpose, the frames are written to display buffer, Section V, p. 246 left column).
One of ordinary skill in the art before the application was filed would have been motivated to implement the decoder of Bhaskaran using the architecture of Abeydeera because Abeydeera teaches that it achieves real-time 4K decoding on a commercially available chip and can be adapted to an ASIC environment, suggesting it is ready for commercial development (p. 237 left column).
Regarding Claim 6, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1.
Bhaskaran does not disclose, but Abeydeera (NPL “4K Real-Time HEVC Decoder on an FPGA,” IEEE 2016) teaches wherein, to send the processed video frame to the display buffer, the one or more processors are configured to display the processed video frame on the display as part of playing the video on the display (for displaying purpose, the frames are written to display buffer, Section V, p. 246 left column).
One of ordinary skill in the art before the application was filed would have been motivated to implement the decoder of Bhaskaran using the architecture of Abeydeera because Abeydeera teaches that it achieves real-time 4K decoding on a commercially available chip and can be adapted to an ASIC environment, suggesting it is ready for commercial development (p. 237 left column).
Regarding Claim 7, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1.
Bhaskaran does not disclose, but Abeydeera (NPL “4K Real-Time HEVC Decoder on an FPGA,” IEEE 2016) teaches wherein the RAM includes a Double Data Rate RAM (The output frames are sent to an RPB that resides in the external DDR3 SDRAM, Section V, p. 246 left column).
One of ordinary skill in the art before the application was filed would have been motivated to implement the decoder of Bhaskaran using the architecture of Abeydeera because Abeydeera teaches that it achieves real-time 4K decoding on a commercially available chip and can be adapted to an ASIC environment, suggesting it is ready for commercial development (p. 237 left column).
Regarding Claim 11, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1, wherein to modify the at least one pixel characteristic of the decoded video frame, the one or more processors are configured to modify at least one of a tone, a sharpness, a brightness, a contrast, or a color saturation of at least a portion of the decoded video frame (contrast enhancement, sharpening and blurring, color enhancement [0017]).
Regarding Claim 12, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1.
Bhaskaran does not disclose but Aoyama (US PG Publication 2014/0178053) teaches wherein, to decode the encoded video frame data, the one or more processors are configured to delay post-processing of the decoded video frame until after the receipt of the indication (display timing is YES at S1404, Fig. 14, [0114]; otherwise loop, Fig. 14).
One of ordinary skill in the art before the application was filed would have been motivated to post-process the decoded image of Baskaran based on the display clock of Aoyama because Aoyama teaches that it minimizes the storage area for storing resized frames, and memory can be efficiently used [0119], improving the efficiency of the playback system.
Regarding Claim 13, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1, wherein, to store the decoded video frame in the RAM, the one or more processors are configured to avoid storing any modified instance of the decoded video frame in the RAM (there is no depiction or description of memory between post processor 22 and display 12, Fig. 1, [0021]).
Regarding Claim 14, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1.
Bhaskaran does not disclose, but Abeydeera (NPL “4K Real-Time HEVC Decoder on an FPGA,” IEEE 2016) teaches wherein, to send the processed video frame to the display buffer, the one or more processors are configured to send the processed video frame directly to the display buffer (for displaying purpose, the frames are written to display buffer, Section V, p. 246 left column).
One of ordinary skill in the art before the application was filed would have been motivated to implement the decoder of Bhaskaran using the architecture of Abeydeera because Abeydeera teaches that it achieves real-time 4K decoding on a commercially available chip and can be adapted to an ASIC environment, suggesting it is ready for commercial development (p. 237 left column).
Regarding Claim 15, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1, wherein the one or more processors are configured to:
receive the encoded video frame data from an encoder (decoder 193 receives encoded video and decodes/ decompresses the encoded video [0042]).
Regarding Claim 16, the claim is rejected on the grounds provided in Claim 1.
Regarding Claim 17, the claim is rejected on the grounds provided in Claim 2.
Regarding Claim 18, the claim is rejected on the grounds provided in Claim 3.
Regarding Claim 19, the claim is rejected on the grounds provided in Claim 4.
Regarding Claim 20, the claim is rejected on the grounds provided in Claim 5.
Regarding Claim 21, the claim is rejected on the grounds provided in Claim 6.
Regarding Claim 22, the claim is rejected on the grounds provided in Claim 7.
Regarding Claim 26, the claim is rejected on the grounds provided in Claim 11.
Regarding Claim 27, the claim is rejected on the grounds provided in Claim 12.
Regarding Claim 28, the claim is rejected on the grounds provided in Claim 13.
Regarding Claim 29, the claim is rejected on the grounds provided in Claim 14.
Regarding Claim 30, the claim is rejected on the grounds provided in Claim 15.
Claim(s) 8, 23 are rejected under 35 U.S.C. 103 as being unpatentable over Bhaskaran (US PG Publication 2013/0251281) in view of Aoyama (US PG Publication 2014/0178053), Abeydeera (NPL “4K Real-Time HEVC Decoder on an FPGA,” IEEE 2016), and Sun (US 20180103261 A1).
Regarding Claim 8, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1.
Bhaskaran does not disclose, but Sun (US 20180103261 A1) teaches wherein to modify the at least one pixel characteristic of the decoded video frame, the one or more processors are configured to apply a color space conversion to the decoded video frame to convert the decoded video frame from a first color space to a second color space that is associated with the display (Post-processing can also include upsampling of chroma sample values and/or color space conversion [0085]).
One of ordinary skill in the art before the application was filed would have been motivated to supplement Bhaskaran with resolution and color-space conversion, as taught by Sun, because these are commonly known and used post-processing algorithms and implementing them generates predictable results (i.e., images in the new color space or new resolution).
Regarding Claim 23, the claim is rejected on the grounds provided in Claim 8.
Claim(s) 9 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Bhaskaran (US PG Publication 2013/0251281) in view of Aoyama (US PG Publication 2014/0178053), Abeydeera (NPL “4K Real-Time HEVC Decoder on an FPGA,” IEEE 2016), and Doken (WO 2012058394 A1)
Regarding Claim 9, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1.
Bhaskaran does not disclose, but Doken (WO 2012058394 A1) teaches wherein to modify the at least one characteristic of the decoded video frame, the one or more processors are configured to apply a format conversion to the decoded video frame to convert the decoded video frame from a first format to a second format that is associated with the display (post-processor can encode/transcode into any format, p. 12 lines 25 - end).
One of ordinary skill in the art before the application was filed would have been motivated to supplement Bhaskaran with format conversion, as taught by Doken, because these are commonly known and used post-processing algorithms and implementing them generates predictable results (i.e., images in the new format).
Regarding Claim 24, the claim is rejected on the grounds provided in Claim 9.
Claims 10 and 25 are Bhaskaran (US PG Publication 2013/0251281) in view of Aoyama (US PG Publication 2014/0178053), Abeydeera (NPL “4K Real-Time HEVC Decoder on an FPGA,” IEEE 2016), and
Regarding Claim 10, Bhaskaran (US PG Publication 2013/0251281) discloses the apparatus of claim 1.
Bhaskaran does not disclose, but Norkin (NPL: “AHG17: Alternative film grain characteristics SEI message,” JVET-R0384; 2020) teaches wherein to modify the at least one pixel characteristic of the decoded video frame, the one or more processors are configured to reconstruct film grain to add to the decoded video frame based on the parameter, wherein the parameter is a film grain parameter associated with the film grain (film grain synthesis support with signalling the film grain parameters, Introduction).
One of ordinary skill in the art before the application was filed would have been motivated to implement film grain post processing in the post-processor of Bhaskaran because Norkin teaches that film grain processing is necessary in a standards-compatible decoder, and Norkin’s implementation of signaling enables re-use of existing post-processing modules, improving compression efficiency on movie and TV content with no cost to manufacturers (Abstract), improving quality for consumers.
Regarding Claim 25, the claim is rejected on the grounds provided in Claim 10.
Response to Arguments
Applicant’s remarks filed 6/25/2026 are unpersuasive.
Applicant argues that Aoyama’s display clock does not indicate when the next sequence of frames is to be displayed as part of playing the video Remarks at 11. This is not persuasive. The display clock indicates the display timing of the display. Aoyama at [0106]. The display screen is displayed on the display unit 208 at a timing based on a display clock. Aoyama at [0110]. Therefore, the display clock does indicate when the next sequence of frames is to be displayed.
Applicant argues that Bhaskaran does not modify a pixel based on a parameter. Remarks at 11. This is not persuasive because Bhaskaran modifies a pixel based on weight parameters. Bhaskaran at [0063].
Applicant argues that Aoyama does not teach a display buffer and instead stores the image data back into memory 203, which is the same memory in which its decoded frame was stored before processing. Remarks at 11. This is not persuasive for two reasons. Aoyama is not relied upon for teaching storing processed images in a display buffer. Therefore this argument is not pertinent to the rejection. However, as Applicant concedes, Aoyama stores the processed image in “storage area for display screens,” which is a display buffer. The decoded/unprocessed, full-sized image of Aoyama is not stored in memory dedicated to “display screens.” That means that the decoded/unprocessed and reduced-size images are not in the same memory segment/area. They are in distinct, non-overlapping spaces. Note that the claim language does not require two distinct hardware memory chips, just RAM and a display buffer. Technologically, display buffers are also RAM.
Applicant argues that Abeydeera does not make up for the deficiencies of Bhaskaran and Aoyama. This is not persuasive because Abeydeera recites a display buffer verbatim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20140180458 A1 – reducing the power consumed by the processor by delaying processing
US 20100158099 A1 - content adaptive postprocessor to change bitrate(s) and resolution(s) depending upon the capabilities of interface
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SHADAN E HAGHANI/ Examiner, Art Unit 2485
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