DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/11/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19-28, 30-40, 42 and 43 are rejected under 35 U.S.C. 103 as being unpatentable over Kang (US 2016/0154594), hereinafter referred to as Kang in view of Lee (US 2015/0347314), hereinafter referred to as Lee and Hahn (US 2016/0274797), hereinafter referred to Hahn.
Referring to claim 19, Kang teaches, as claimed, a memory controller, comprising: a cache memory (i.e.-buffer 1240, see fig. 2); and a host control circuit (i.e.-host interface 1220, see fig. 2) configured to read out mapping information corresponding to a logical address from the buffer memory device (i.e.-retrieve mapping information associated with a logical address form a memory system 1100, page 5, ¶91, lines 3-6; and ¶84), and cache the mapping information in the cache memory (i.e.-load the retrieved mapping information into buffer 1240, page 5, ¶91, lines 3-6).
However, Kang does not teach the caching of the mapping information being before transferring the logical address to a flash translation layer; and a buffer memory device configured to store address mapping information loaded from a nonvolatile memory device.
On the other hand, Lee teaches a nonvolatile memory system comprised of a memory controller and, a buffer memory device configured to store address mapping information loaded from a nonvolatile memory device (page 1, ¶5). Furthermore, Hahn discloses a method and system for prefetching mapping information (i.e.-storing FTL table in a host memory buffer, page 1, ¶19, lines 6-10 and page 2, ¶27), before transferring the logical address to a flash translation layer (i.e.-thereby, any logical address given by the host is converted to physical address, page 2, ¶34, lines 14-18).
Therefore, before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the teachings of Kang so that the caching of the mapping information being before transferring the logical address to a flash translation layer; and a buffer memory device configured to store address mapping information loaded from a nonvolatile memory device, as taught by Lee and Hahn. The motivation for doing so would have been to reduce command response time delay by loading mapping data form the nonvolatile memory into the buffer, thereby improving system performance.
As to claim 20, the modified Kang teaches the memory controller of claim 19, further comprising: a flash translation layer configured to read a physical address corresponding to the logical address from the mapping information cached in the cache memory (see Kang, page 5, ¶90, lines 6-7 and ¶96).
As to claim 21, the modified Kang teaches the memory controller of claim 19, wherein the host control circuit is configured to receive a read command including the logical address from a host (see Kang, page 5, ¶89 and ¶96).
As to claim 22, the modified Kang in view of Lee teaches the memory controller of claim 19, further comprising: a flash control circuit configured to read data corresponding to the read command from a nonvolatile memory device based on the physical address (see Lee, page 3, ¶52, lines 6-10).
As to claim 23, the modified Kang teaches the memory controller of claim 19, further comprising an error correction circuit coupled between the buffer memory device and the cache memory (see Kang, page 4, ¶73, lines 6-7 and see fig. 2).
As to claim 24, the modified Kang teaches the memory controller of claim 23, wherein the error correction circuit is configured to perform an ECC decoding operation on the mapping information output from the buffer memory device and to provide decoded mapping information (see Kang, page 5, ¶92).
As to claim 25, the modified Kang innately teaches the memory controller of claim 24, wherein the cache memory caches the decoded mapping information (see Kang, page 6, ¶111, lines 1-6 and page 7, ¶122).
As to claim 26, the modified Kang in view of Lee teaches the memory controller of claim 19, wherein the buffer memory device is configured to buffer the data read from the nonvolatile memory device (see Lee, ¶47, lines 12-16 and page 3, ¶48, lines 5-6).
As to claim 27, the modified Kang teaches the memory controller of claim 19, wherein when the host control circuit receives a write command, a write logical address, and write data from the host (see Kang, page 9, ¶152, lines 1-6), the flash translation layer is configured to map a write physical address to the write logical address (see Kang, page 4, ¶71), and to update mapping information stored in the buffer memory device with the write physical address mapped to the write logical address (see Kang, page 6, ¶112).
As to claim 28, the modified Kang teaches the memory controller of claim 22, wherein the flash control circuit programs the write data in the nonvolatile device based on the write physical address (see Kang, page 4, ¶67, lines 1-4 and page 5, ¶96).
As to claim 30, the modified Kang teaches the memory controller of claim 27, wherein the flash translation layer updates the mapping information stored in the buffer memory device by writing modified chunk data including the modified section data to the buffer memory device (see Kang, page 6, ¶111, lines 1-7 and ¶112, lines 4-8).
Referring to claims 31-40, 42 and 43, the claims are substantially the same as claims 21-28 and 30, hence the rejection of claims 21-28 and 30 is applied accordingly.
Examiner’s note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Claim Objections
Claims 29 and 41 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed on 11/26/2025 have been fully considered but they are moot in view of the new ground(s) of rejection.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS MAMO whose telephone number is (571)270-1726. The examiner can normally be reached Mon-Thu, 7 AM - 5 PM.
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/Elias Mamo/Primary Examiner, Art Unit 2184
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