DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 43 is rejected under 35 U.S.C. 112(a) first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claim 43 recites the limitation “…wherein the memory controller further comprises: a buffer memory interface configured to couple the memory controller to the buffer memory device, wherein the host control circuit accesses the mapping information stored in the buffer memory device via the buffer memory interface.” which is not supported by the specification as originally filed, and it introduces new matter. Applicants are required to cancel the new matter in reply to this Office Action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19-28, 30-40 and 42 are rejected under 35 U.S.C. 103 as being unpatentable over Kang (US 2016/0154594), hereinafter referred to as Kang in view of Lee (US 2015/0347314), hereinafter referred to as Lee.
Referring to claim 19, Kang teaches, as claimed, a memory controller, comprising: a cache memory (i.e.-buffer 1240, see fig. 2); and a host control circuit (i.e.-host interface 1220, see fig. 2) configured to read out mapping information corresponding to a logical address from the buffer memory device (i.e.-retrieve mapping information associated with a logical address form a memory system 1100, page 5, ¶91, lines 3-6; and ¶84), and cache the mapping information in the cache memory (i.e.-load the retrieved mapping information into buffer 1240, page 5, ¶91, lines 3-6).
However, Kang does not teach a buffer memory device configured to store address mapping information loaded from a nonvolatile memory device.
On the other hand, Lee teaches a nonvolatile memory system comprised of a memory controller and, a buffer memory device configured to store address mapping information loaded from a nonvolatile memory device (page 1, ¶5).
Therefore, before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the teachings of Kang and incorporate a buffer memory device configured to store address mapping information loaded from a nonvolatile memory device, as taught by Lee. The motivation for doing so would have been to reduce command response time delay by loading mapping data form the nonvolatile memory into the buffer.
As to claim 20, the modified Kang teaches the memory controller of claim 19, further comprising: a flash translation layer configured to read a physical address corresponding to the logical address from the mapping information cached in the cache memory (see Kang, page 5, ¶90, lines 6-7 and ¶96).
As to claim 21, the modified Kang teaches the memory controller of claim 19, wherein the host control circuit is configured to receive a read command including the logical address from a host (see Kang, page 5, ¶89 and ¶96).
As to claim 22, the modified Kang in view of Lee teaches the memory controller of claim 19, further comprising: a flash control circuit configured to read data corresponding to the read command from a nonvolatile memory device based on the physical address (see Lee, page 3, ¶52, lines 6-10).
As to claim 23, the modified Kang teaches the memory controller of claim 19, further comprising an error correction circuit coupled between the buffer memory device and the cache memory (see Kang, page 4, ¶73, lines 6-7 and see fig. 2).
As to claim 24, the modified Kang teaches the memory controller of claim 23, wherein the error correction circuit is configured to perform an ECC decoding operation on the mapping information output from the buffer memory device and to provide decoded mapping information (see Kang, page 5, ¶92).
As to claim 25, the modified Kang innately teaches the memory controller of claim 24, wherein the cache memory caches the decoded mapping information (see Kang, page 6, ¶111, lines 1-6 and page 7, ¶122).
As to claim 26, the modified Kang in view of Lee teaches the memory controller of claim 19, wherein the buffer memory device is configured to buffer the data read from the nonvolatile memory device (see Lee, ¶47, lines 12-16 and page 3, ¶48, lines 5-6).
As to claim 27, the modified Kang teaches the memory controller of claim 19, wherein when the host control circuit receives a write command, a write logical address, and write data from the host (see Kang, page 9, ¶152, lines 1-6), the flash translation layer is configured to map a write physical address to the write logical address (see Kang, page 4, ¶71), and to update mapping information stored in the buffer memory device with the write physical address mapped to the write logical address (see Kang, page 6, ¶112).
As to claim 28, the modified Kang teaches the memory controller of claim 22, wherein the flash control circuit programs the write data in the nonvolatile device based on the write physical address (see Kang, page 4, ¶67, lines 1-4 and page 5, ¶96).
As to claim 30, the modified Kang teaches the memory controller of claim 27, wherein the flash translation layer updates the mapping information stored in the buffer memory device by writing modified chunk data including the modified section data to the buffer memory device (see Kang, page 6, ¶111, lines 1-7 and ¶112, lines 4-8).
Referring to claims 31-40 and 42, the claims are substantially the same as claims 21-28 and 30, hence the rejection of claims 21-28 and 30 is applied accordingly.
Examiner’s note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Claim Objections
Claims 29 and 41 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed on 11/26/2025 have been fully considered but they are not persuasive.
Applicants argued:
Neither Kang nor Lee discloses movement of mapping data within the memory controller itself, specifically from the buffer memory device to the cache memory, as required by the pending claims. Therefore, neither Kang nor Lee, alone or in combination, discloses or suggests the internal controller-level operation in which mapping information already stored in the buffer memory of the memory controller is read out and cached in a separate cache memory of the memory controller.
The Examiner disagrees with the above statement. Kang teaches moving/caching of mapping information/data from internal memory system 1100 into a buffer 1240 of the memory controller. Please see page 5, ¶91, lines 3-6; and ¶84. Lee is cited as teaching a method of reading out mapping information from a memory cell array and, loading the mapping information into a page buffer (page 1, ¶5, ¶14 and ¶23), and further loading the mapping data from the page buffer into a storage unit provided in the memory controller 120 (page 3, ¶55, lines 14-17 and ¶56, lines 1-4). Therefore, the combined teaching of Knag and Lee do teach the claimed invention as stated in the claim rejections above.
Applicants argued:
Kang fails to disclose this staged hierarchy. Kang discloses loading mapping blocks from the memory device 1100 into a buffer 1240 located inside the controller to reconstruct the mapping table during a boot-time "Fast Open" operation. Kang utilizes this single internal buffer as its primary working memory and does not teach fetching data from an external system buffer to populate a separate internal cache during runtime.
The Examiner disagrees with the above statement. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e.- fetching data from an external system buffer to populate a separate internal cache during runtime.) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicants argued:
A person of ordinary skill in the art would not be motivated to modify Kang in view of Lee to create the claimed architecture. Because Kang's controller already possesses an internal Buffer 1240 for holding mapping data, adding a second layer of internal memory (a separate cache) to store data copied from that buffer would be redundant and add unnecessary hardware complexity without a suggested benefit in the references. The proposed combination effectively reconstructs the invention using the claims as a guide rather than relying on the prior art teachings. Claim 31 is allowable.
The Examiner disagrees with the above statement. Lee teaches, moving mapping data into a storage unit contained in the memory controller, the storage unit having a high read speed (see Lee, ¶56, lines 1-5). Bearing this in mind, the motivation for combining the cited arts (i.e.-Kang in view of Lee) is, to reduce command response time delay by loading mapping data form the nonvolatile memory into a buffer (i.e.-Lee’s storage unit with a high read speed).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS MAMO whose telephone number is (571)270-1726. The examiner can normally be reached Mon-Thu, 7 AM - 5 PM.
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/Elias Mamo/Primary Examiner, Art Unit 2184