DETAILED ACTION
Claims 1-20 are presented for examination.
This office action is in response to request for continued examination of application on 9-MARCH-2026, in view of the arguments and amendments in the response after final action filed 4-FEB-2026.
Claims 1-20 remain pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see page 11, filed 4-FEB-2026, with respect to the rejection of claim 1 under 35 U.S.C. 103 have been fully considered and are persuasive due to amendment. The rejection of claim 1 under 35 U.S.C. 103 has been withdrawn.
Applicant has amended subject matter which Examiner and Applicant’s Representative had previously discussed in an interview held on 2-FEB-2026 in an attempt to overcome the prior art used to reject claim 1. However, Examiner notes that due to the claim language, as drafted, the claim is not yet allowable due to confusion around a specific wording of the claims rendering the claim indefinite that could also present further confusion if Applicant attempts to fix the wording in a particular way, which will be discussed in further detail in the rejections below.
Applicant's arguments filed 4-FEB-2026 have been fully considered but they are not persuasive.
1. Regarding Applicant’s arguments that claims 9 and 17 should be patentable for the same reasons as for claim 1, Examiner respectfully disagrees. While not exactly the same as a contingent limitation, similar logic applies for the instant claims 9 and 17, as it is discussed in MPEP 2111.04(II), the broadest reasonable interpretation of a method claim requires only steps that must be performed, and may not include steps that are not required to be performed if the conditions precedent are not met. In other words, since claims 9 and 17 are method claims, the broadest reasonable interpretation of the claims encompasses a scenario in which the subject matter deemed allowable in claim 1 does not necessarily occur, and therefore the subject matter is not required for the claim, because the steps of the method claim can be completed without the features deemed allowable.
2. Further regarding claims 9 and 17, claims 9 and 17 also include the wording found to render claim 1 indefinite, and are further rejected for those reasons.
Information Disclosure Statement
Examiner notes that an Information Disclosure Statement has not been filed by the applicant as of the date of this office action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1: Claim 1 recites “wherein the single-fine program scheme or the multi-fine program scheme comprises…”. However, it is unclear whether Applicant intends for both the single-fine program scheme and the multi-fine program scheme to comprise the sequence of pulses, or whether Applicant intends for only one of the schemes to comprise the sequence of pulses, as the “or” in this limitation is unclear whether it refers to the schemes in a collective manner or in an alternative manner. As shown in [0052-0053] and in Fig. 2B, as well as [0073] and Fig. 4G of the instant disclosure, either of the interpretations are valid and supported, which renders the exact metes and bounds of the claim unclear, and therefore indefinite.
Examiner notes, however, that if Applicant amends claim 1 in a manner to positively recite that the multi-fine program scheme comprises the sequence (considered to be subblock-first as shown in Fig. 4B), then that limitation may conflict with claims 6 and 7. Regarding claim 6, the multi-fine scheme being associated with the word-line-first scheme would conflict with any positive recitation of the multi-fine scheme comprising a subblock-first programming sequence. Regarding claim 7, the multi-fine scheme being associated with the subblock-first program scheme lacks a further limitation of the subject matter of a positive recitation of the multi-fine scheme comprising a subblock-first programming sequence, which may be rejected under 35 U.S.C. 112(d).
For the purposes of Examining over prior art, “wherein the single-fine program scheme or the multi-fine program scheme comprises…” is interpreted to be referring to the schemes in an alternative manner. That is, the limitation is interpreted to mean that at least one (one or more of the schemes) of the schemes comprises the pulse sequence.
Claims 2-8 depend on claim 1, and inherit the deficiencies of claim 1, and are rejected for the same reasons.
Regarding claim 9: Claim 9 recites “wherein the single-fine program scheme or the multi-fine program scheme comprises…”. However, it is unclear whether Applicant intends for both the single-fine program scheme and the multi-fine program scheme to comprise the sequence of pulses, or whether Applicant intends for only one of the schemes to comprise the sequence of pulses, as the “or” in this limitation is unclear whether it refers to the schemes in a collective manner or in an alternative manner. As shown in [0052-0053] and in Fig. 2B, as well as [0073] and Fig. 4G of the instant disclosure, either of the interpretations are valid and supported, which renders the exact metes and bounds of the claim unclear, and therefore indefinite.
Further, since claim 9 is a method claim, this uncertainty is further exacerbated in the “executing… the program scheme… using the selected program scheme” limitation, as there is uncertainty as to whether the method must be completed with the sequence of pulses or not, as the method’s completion would be dependent upon the uncertain interpretation above.
Examiner notes, however, that if Applicant amends claim 9 in a manner to positively recite that the multi-fine program scheme comprises the sequence (considered to be subblock-first as shown in Fig. 4B), then that limitation may conflict with claims 14 and 15. Regarding claim 14, the multi-fine scheme being associated with the word-line-first scheme would conflict with any positive recitation of the multi-fine scheme comprising a subblock-first programming sequence. Regarding claim 15, the multi-fine scheme being associated with the subblock-first program scheme lacks a further limitation of the subject matter of a positive recitation of the multi-fine scheme comprising a subblock-first programming sequence, which may be rejected under 35 U.S.C. 112(d).
For the purposes of Examining over prior art, “wherein the single-fine program scheme or the multi-fine program scheme comprises…” is interpreted to be referring to the schemes in an alternative manner. That is, the limitation is interpreted to mean that at least one (one or more of the schemes) of the schemes comprises the pulse sequence.
Claims 10-16 depend on claim 9, and inherit the deficiencies of claim 9, and are rejected for the same reasons.
Regarding claim 17: Claim 17 recites “wherein the single-fine program scheme or the multi-fine program scheme comprises…”. However, it is unclear whether Applicant intends for both the single-fine program scheme and the multi-fine program scheme to comprise the sequence of pulses, or whether Applicant intends for only one of the schemes to comprise the sequence of pulses, as the “or” in this limitation is unclear whether it refers to the schemes in a collective manner or in an alternative manner. As shown in [0052-0053] and in Fig. 2B, as well as [0073] and Fig. 4G of the instant disclosure, either of the interpretations are valid and supported, which renders the exact metes and bounds of the claim unclear, and therefore indefinite.
Further, since claim 17 is a method claim, this uncertainty is further exacerbated in the “executing… the program scheme… using the selected program scheme” limitation, as there is uncertainty as to whether the method must be completed with the sequence of pulses or not, as the method’s completion would be dependent upon the uncertain interpretation above.
For the purposes of Examining over prior art, “wherein the single-fine program scheme or the multi-fine program scheme comprises…” is interpreted to be referring to the schemes in an alternative manner. That is, the limitation is interpreted to mean that at least one (one or more of the schemes) of the schemes comprises the pulse sequence.
Claims 18-20 depend on claim 17, and inherit the deficiencies of claim 17, and are rejected for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-11, 13-14, 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over
Luo et al., U.S. Pub. No. 20210149564 (hereinafter “Luo”) in view of
MU et al., U.S. Pub. No. 20140321212 (hereinafter “Mu”) further in view of
Lu et al., U.S. Patent No. 10665299 (hereinafter “Lu”)
Regarding claim 9: Examiner firstly notes that since the claim is interpreted with the “wherein the single-fine program scheme or the multi-fine program scheme comprises” in the alternative manner, the broadest reasonable interpretation of the claim encompasses a scenario in which, for example, only the multi-fine program scheme comprises the sequence of pulses (and not the single-fine scheme), but the determining a selected program scheme selects the single-fine scheme, and the executing the program command uses the single-fine scheme without the sequence of pulses.
As stated in MPEP 2111.04(II), the broadest reasonable interpretation of a method claim requires only steps that must be performed, and does not include steps that are not required to be performed because the conditions are not met. In this case, while the limitations of this claim are not explicitly contingent (if <condition>, then <action>), the described scenario still shows that the sequence of pulses are not required to be performed to complete the method of the claim if only one scheme comprises the sequence of pulses and the scheme that performs the sequence of pulses is not selected. Therefore, the broadest reasonable interpretation of the claim does not require the “a coarse pulse applied on each subblock of the first word line, followed by a subsequent coarse pulse applied to a first indexed subblock of the second word line followed by one or more fine pulses applied to a corresponding first indexed subblock of the first word line, followed by an additional coarse pulse applied to a second indexed subblock of the second word line” limitations to be performed.
Therefore, the claim is mapped to prior art with the interpretation that the selection and execution is performed with the word-line-first program scheme described in Fig. 4G and [0073], where coarse pulses are applied to each subblock of a first word line, followed by a coarse pulse applied to a first subblock of a second word line, followed by a fine pulse applied to the first subblock of the first word line, which is a supported embodiment as described in the previous presentation of the claim, and wherein the additional coarse pulse applied to a second indexed subblock of the second word line is not required.
Luo teaches A method, comprising:
receiving, by a memory device from a host device, a program command instructing the memory device to program host data to at least a first word line and a second word line associated with a memory; ([0085-0086], Luo teaches that a write command can be received by a memory device, from a host to write data into a storage region. Furthermore, in [0054], Luo teaches that programs and writes involves a selection to word lines. While not explicit, the described selected word lines are plural, and therefore, a first word line and a second word line are an obvious embodiment of multiple selected word lines, and the other parts of the writing process are interpreted to apply to a first and a second word line.).
determining, by the memory device, a program erase cycle (PEC) count associated with the first word line and the second word line; ([0085], Luo teaches to identify a P/E cycle metric associated with the region, which includes the selected word lines).
determining, by the memory device and based on the PEC count, a selected program scheme to be used to program the host data to the first word line and the second word line, wherein ([0086], Luo teaches that based on where the identified P/E cycle metric falls within the P/E cycle ranges, the memory controller selects one of the memory trim sets associated with the P/E cycle range which the identified P/E cycle metric falls within, the memory trim sets defining write operation parameters).
executing the program command by programming the host data to the memory using the selected program scheme. ([0086], Luo teaches the write command is executed to write data using the selected trim values of the trim set).
While Luo teaches several write operation parameters that are defined by trim values, Luo does not appear to explicitly disclose the selected program scheme is one of a single-fine program scheme or a multi-fine program scheme;
However, Mu teaches the selected program scheme is one of a single-fine program scheme or a multi-fine program scheme; ([0017], Mu teaches to increase a pulse count as the lifecycle age changes. The pulse counts are interpreted to be the claimed program scheme. Moreover, in [0021], Mu teaches an example where a programming may be started at a single pulse, and a single-fine program scheme is taught. Increasing the pulses relative to the single-fine program, as Mu teaches to do, is interpreted to be the claimed multi-fine program scheme).
Luo and Mu are analogous art because they are from the same field of endeavor, controlling memory write operations.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Luo and Mu to achieve determining a PEC count, and to select a write scheme associated with the PEC count to execute the write with, with the possible selected program schemes including a single-fine program scheme or a multi-fine program scheme.
One of ordinary skill in the art would have been motivated to make this modification in order to account for known affects that lifecycle age and temperature have on the number of pulses required to pass a verify operation as discussed in Mu [0017] “The number of series of pulses required to pass a verify operation will typically increase with lifecycle age and/or with changes in operating temperature, depending on the operation being performed.”
While Luo/Mu teaches generally varying a number of program pulses according to PEC count or temperature, to associate portions of memory with a reliability risk, Luo/Mu does not appear to explicitly disclose the single-fine program scheme or the multi-fine program scheme comprises a coarse pulse applied on each subblock of the first word line, followed by a subsequent coarse pulse applied to a first indexed subblock of the second word line followed by one or more fine pulses applied to a corresponding first indexed subblock of the first word line, followed by an additional coarse pulse applied to a second indexed subblock of the second word line.
However, Lu teaches the single-fine program scheme or the multi-fine program scheme comprises a coarse pulse applied on each subblock of the first word line, followed by a subsequent coarse pulse applied to a first indexed subblock of the second word line followed by one or more fine pulses applied to a corresponding first indexed subblock of the first word line. (Col. 16 line 51 to Col. 17 line 5, Lu teaches multi-pass (including two-pass) programming operations which apply a first coarse pass, then a second fine pass, which can extend to more than two passes. Furthermore, in Col. 15 lines 22-44, Lu teaches a programming order in which the subblocks in a first WL0 are all programmed first (From SB0 to SB3), followed by the subblocks in a second WL1 being programmed (from SB0 to SB3). Lu also teaches a back and forth word line programming order where for a multi-pass programming, a first program pass for WL0 is completed followed by a first program pass for WL1, before going back to WL0 to complete a second program pass. The combination of the teachings of Lu results in the claimed program schemes where a coarse pulse is applied to each subblock of the first word line, followed by coarse pulses on the first subblock of the second word line, followed by fine pulses on the first subblock of the first word line.)
Luo/Mu and Lu are analogous art because they are from the same field of endeavor, controlling memory write operations.
Considering the programming order of Lu to be a base memory device and the above combination of Luo and Mu as an improvement to memory devices, one of ordinary skill in the art would have recognized that applying the improvement of Luo/Mu to the base memory device of Lu would have predictably resulted in the memory device which selects a program scheme with various programming pulses based on the PEC count/temperature and their known effects on temperature, to be applied to a device with a programming order of applying a coarse pulse to subblocks of a word line first, before coarse pulses to subblocks in a second word line, before applying fine pulses afterwards in the same order.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Luo/Mu and Lu, to achieve the claimed method involving the memory device as described above.
Regarding claim 10: The combination of Luo, Mu, and Lu teaches all limitations of claim 9, from which claim 10 depends.
Luo/Mu/Lu further teaches determining the selected program scheme to be used to program the host data to the first word line and the second word line includes determining the selected program scheme using a lookup table ([0017], Mu teaches that the pulse count data according to the lifecycle age may be implemented as a lookup table. With the pulse count data interpreted to be the program scheme and the program scheme selection done according to the P/E cycle count, as explained with respect to claim 9, the pulse count data being implemented as a lookup table is interpreted to be determining the selected program scheme using a lookup table.)
One of ordinary skill would have been motivated to make this modification as lookup tables are a well-known and obvious possible implementation of correlating input data to an output.
Regarding claim 11: The combination of Luo, Mu, and Lu teaches all limitations of claim 10, from which claim 11 depends.
Luo/Mu/Lu further teaches the lookup table indicates multiple PEC count thresholds, and for each PEC count threshold, of the multiple PEC count thresholds, a corresponding program scheme ([0081], Luo teaches that the P/E cycle ranges, are defined as the P/E cycles between various threshold P/E cycle values. Luo also teaches in the same paragraph, that each of those P/E cycle ranges is associated with corresponding memory trim sets, which define program schemes.)
Luo/Mu/Lu further teaches associated with each word line group, of multiple word line groups ([0017], Luo teaches that P/E cycle metrics can be indicative of a number of P/E cycles performed in at least a region of the memory device, including of a memory block. Furthermore, in Fig. 2 and [0045-0048], Luo teaches that the word lines of the memory are associated with blocks, and that there are many blocks in a memory device. The blocks, as they are shown to connect to a plurality of word lines, is interpreted to be the claimed word line groups. Further, in [0032] and [0044], Luo teaches specific tables that stores, among other metrics, the P/E cycle metrics for each block which can be retrieved on request for the purpose of selecting a memory trim set. Therefore, since the program schemes and thresholds may be retrieved via lookup table, and the metrics associated with blocks are also in tables where they can be retrieved for the block, it would be an obvious embodiment to implement a table that is able to provide the lookup for the metrics associated with each block and how they associate with program schemes, which correspond to P/E cycle thresholds.)
Regarding claim 13: The combination of Luo, Mu, and Lu teaches all limitations of claim 9, from which claim 13 depends.
Luo/Mu/Lu further teaches determining that the single-fine program scheme is to be used to program the host data to the first word line and the second word line when the PEC count is associated with a first PEC threshold; determining that a double-fine program scheme is to be used to program the host data to the word line when the PEC count is associated with a second PEC threshold; and determining that a triple-fine program scheme is to be used to program the host data to the word line when the PEC count is associated with a third PEC threshold. ([0081], Luo teaches that there may be three P/E cycle ranges in an embodiment, each defined by representing the range between threshold values, where each range is associated with program schemes. As explained with respect to claim 9, Mu also teaches that a pulse count may be increased when the lifecycle age increases, due to the need to adjust to a higher pulse count. Hence, the combination of using the three P/E cycle ranges of Luo to define three different pulse counts to use, represented as three different program schemes, with one program scheme being a single-fine program scheme, a second program scheme being a double-fine program scheme with more pulses than the single, and a third program scheme being a triple-fine scheme with more pulses than the double, is an obvious embodiment.)
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as claim 9.
Regarding claim 14: The combination of Luo, Mu, and Lu teach all limitations of claim 9, from which claim 14 depends.
Luo/Mu/Lu further teaches wherein the multi-fine program scheme is associated with a word-line-first program scheme. (As discussed with respect to claim 9, Lu teaches a programming order in which all subblocks of a word line are programmed in a coarse pass, then all subblocks of a second word line are programmed in another coarse pass, before returning to perform a fine pass on the subblocks of the word lines in the same order, which is interpreted to be the claimed multi-fine program scheme associated with a word-line-first program scheme.)
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as claim 9.
Regarding claim 16: The combination of Luo, Mu, and Lu teaches all limitations of claim 9, from which claim 16 depends.
Luo/Mu/Lu further teaches the memory is associated with one of a triple-level cell memory, a quad-level cell memory, or a penta-level cell memory ([0021], Luo teaches that flash memory cells may be triple-level cells or quad-level cells, or broadly as cells that can store more than one bit per cell.)
Regarding claim 17: Examiner firstly notes that since the claim is interpreted with the “wherein the single-fine program scheme or the multi-fine program scheme comprises” in the alternative manner, the broadest reasonable interpretation of the claim encompasses a scenario in which, for example, only the multi-fine program scheme comprises the sequence of pulses (and not the single-fine scheme), but the determining a selected program scheme selects the single-fine scheme, and the executing the program command uses the single-fine scheme without the sequence of pulses.
As stated in MPEP 2111.04(II), the broadest reasonable interpretation of a method claim requires only steps that must be performed, and does not include steps that are not required to be performed because the conditions are not met. In this case, while the limitations of this claim are not explicitly contingent (if <condition>, then <action>), the described scenario still shows that the sequence of pulses are not required to be performed to complete the method of the claim if only one scheme comprises the sequence of pulses and the scheme that performs the sequence of pulses is not selected. Therefore, the broadest reasonable interpretation of the claim does not require the “a coarse pulse applied on each subblock of the first word line, followed by a subsequent coarse pulse applied to a first indexed subblock of the second word line followed by one or more fine pulses applied to a corresponding first indexed subblock of the first word line, followed by an additional coarse pulse applied to a second indexed subblock of the second word line” limitations to be performed.
Therefore, the claim is mapped to prior art with the interpretation that the selection and execution is performed with the word-line-first program scheme described in Fig. 4G and [0073], where coarse pulses are applied to each subblock of a first word line, followed by a coarse pulse applied to a first subblock of a second word line, followed by a fine pulse applied to the first subblock of the first word line, which is a supported embodiment as described in the previous presentation of the claim, and wherein the additional coarse pulse applied to a second indexed subblock of the second word line is not required.
Luo teaches A method, comprising:
receiving, by a memory device from a host device, a program command instructing the memory device to program host data to a first word line and a second word line associated with a memory; ([0085-0086], Luo teaches that a write command can be received by a memory device, from a host to write data into a storage region. Furthermore, in [0054], Luo teaches that programs and writes involves a selection to word lines. While not explicit, the described selected word lines are plural, and therefore, a first word line and a second word line are an obvious embodiment of multiple selected word lines, and the other parts of the writing process are interpreted to apply to a first and a second word line.).
determining, by the memory device, a temperature associated with the memory; ([0085], Luo teaches to identify a temperature metric associated with the region).
determining, by the memory device and based on the temperature, a selected program scheme to be used to program the host data to the first word line and the second word line, wherein ([0086], Luo teaches that based on where the identified temperature metric falls within the temperature ranges, the memory controller selects one of the memory trim sets associated with the temperature range which the identified temperature metric falls within, the memory trim sets defining write operation parameters).
executing, by the memory device, the program command by programming the host data to the memory using the selected program scheme ([0086], Luo teaches the write command is executed to write data using the selected trim values of the trim set).
While Luo teaches several write operation parameters that are defined by trim values, Luo does not appear to explicitly disclose the selected program scheme is one of a single-fine program scheme or a multi-fine program scheme;
However, Mu teaches the selected program scheme is one of a single-fine program scheme or a multi-fine program scheme; ([0017], Mu teaches to increase a pulse count as the temperature changes. The pulse counts are interpreted to be the claimed program scheme. Moreover, in [0021], Mu teaches an example where a programming may be started at a single pulse, and a single-fine program scheme is taught. Increasing the pulses relative to the single-fine program, as Mu teaches to do, is interpreted to be the claimed multi-fine program scheme).
Luo and Mu are analogous art because they are from the same field of endeavor, controlling memory write operations.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Luo and Mu to achieve determining a temperature, and to select a write scheme based on the temperature to execute the write with, with the possible selected program schemes including a single-fine program scheme or a multi-fine program scheme.
One of ordinary skill in the art would have been motivated to make this modification in order to account for known affects that lifecycle age and temperature have on the number of pulses required to pass a verify operation as discussed in Mu [0017] “The number of series of pulses required to pass a verify operation will typically increase with lifecycle age and/or with changes in operating temperature, depending on the operation being performed.”
While Luo/Mu teaches generally varying a number of program pulses according to PEC count or temperature, to associate portions of memory with a reliability risk, Luo/Mu does not appear to explicitly disclose the single-fine program scheme or the multi-fine program scheme comprises a coarse pulse applied on each subblock of the first word line, followed by a subsequent coarse pulse applied to a first indexed subblock of the second word line followed by one or more fine pulses applied to a corresponding first indexed subblock of the first word line, followed by an additional coarse pulse applied to a second indexed subblock of the second word line.
However, Lu teaches the single-fine program scheme or the multi-fine program scheme comprises a coarse pulse applied on each subblock of the first word line, followed by a subsequent coarse pulse applied to a first indexed subblock of the second word line followed by one or more fine pulses applied to a corresponding first indexed subblock of the first word line. (Col. 16 line 51 to Col. 17 line 5, Lu teaches multi-pass (including two-pass) programming operations which apply a first coarse pass, then a second fine pass, which can extend to more than two passes. Furthermore, in Col. 15 lines 22-44, Lu teaches a programming order in which the subblocks in a first WL0 are all programmed first (From SB0 to SB3), followed by the subblocks in a second WL1 being programmed (from SB0 to SB3). Lu also teaches a back and forth word line programming order where for a multi-pass programming, a first program pass for WL0 is completed followed by a first program pass for WL1, before going back to WL0 to complete a second program pass. The combination of the teachings of Lu results in the claimed program schemes where a coarse pulse is applied to each subblock of the first word line, followed by coarse pulses on the first subblock of the second word line, followed by fine pulses on the first subblock of the first word line.)
Luo/Mu and Lu are analogous art because they are from the same field of endeavor, controlling memory write operations.
Considering the programming order of Lu to be a base memory device and the above combination of Luo and Mu as an improvement to memory devices, one of ordinary skill in the art would have recognized that applying the improvement of Luo/Mu to the base memory device of Lu would have predictably resulted in the memory device which selects a program scheme with various programming pulses based on the PEC count/temperature and their known effects on temperature, to be applied to a device with a programming order of applying a coarse pulse to subblocks of a word line first, before coarse pulses to subblocks in a second word line, before applying fine pulses afterwards in the same order.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Luo/Mu and Lu, to achieve the claimed method involving the memory device as described above.
Regarding claim 18: The combination of Luo, Mu, and Lu teaches all limitations of claim 17, from which claim 18 depends.
Luo/Mu/Lu further teaches determining the selected program scheme to be used to program the host data to the first word line and the second word line includes determining the selected program scheme using a lookup table ([0017], Mu teaches that the pulse count data according to the temperature may be implemented as a lookup table. With the pulse count data interpreted to be the program scheme and the program scheme selection done according to the temperature, as explained with respect to claim 9, the pulse count data being implemented as a lookup table is interpreted to be determining the selected program scheme using a lookup table.)
One of ordinary skill would have been motivated to make this modification as lookup tables are a well-known and obvious possible implementation of correlating input data to an output.
Regarding claim 19: The combination of Luo, Mu, and Lu teaches all limitations of claim 18, from which claim 19 depends.
Luo/Mu/Lu further teaches the lookup table indicates multiple temperature ranges and, for each temperature range, of the multiple temperature ranges, a corresponding program scheme and ([0071-0072], Luo teaches three ranges, and that each of the temperature ranges is associated with a corresponding memory trim set, which each include memory operation parameters)
Luo/Mu further teaches a corresponding set of word lines associated with the corresponding program scheme ([0017], Luo teaches that temperature metrics can be indicative of a temperature of at least a region of the memory device, including of a memory block. Furthermore, in Fig. 2 and [0045-0048], Luo teaches that the word lines of the memory are associated with blocks. The blocks, as they are shown to connect to a plurality of word lines, is interpreted to be the claimed set of word lines. Further, in [0032] and [0044], Luo teaches specific tables that stores, among other metrics, the temperature metrics for each block which can be retrieved on request for the purpose of selecting a memory trim set. Therefore, since the program schemes and thresholds may be retrieved via lookup table, and the metrics associated with blocks are also in tables where they can be retrieved for the block, it would be an obvious embodiment to implement a table that is able to provide the lookup for the metrics associated with each block and how they associate with program schemes, which correspond to temperature ranges.)
Regarding claim 20: The combination of Luo, Mu, and Lu teaches all limitations of claim 17, from which claim 20 depends.
Luo/Mu/Lu further teaches determining that the single-fine program scheme is to be used to program the host data to the first word line and the second word line when the temperature is associated with a first temperature range; determining that a double-fine program scheme is to be used to program the host data to the first word line and second word line when the temperature is associated with a second temperature range; and determining that a triple-fine program scheme is to be used to program the host data to the first word line and the second word line when the temperature is associated with a third temperature range. ([0071-0072] and [0080], Luo teaches that there may be three temperature ranges in an embodiment, each defined by representing the range between threshold values, where each range is associated with program schemes. As explained with respect to claim 9, Mu also teaches that a pulse count may be increased when the temperature increases, due to the need to adjust to a higher pulse count. Mu further teaches example embodiments of pulse count increases according to the temperature range, in an increasing manner (see Mu Fig. 5). Hence, the combination of using the three temperature ranges of Luo to define three different pulse counts to use, represented as three different program schemes, with one program scheme being a single-fine program scheme, a second program scheme being a double-fine program scheme with more pulses than the single, and a third program scheme being a triple-fine scheme with more pulses than the double, is an obvious embodiment.)
One of ordinary skill in the art would have been motivated to make this modification for the same reasons as claim 17.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over
Luo et al., U.S. Pub. No. 20210149564 (hereinafter “Luo”) in view of
MU et al., U.S. Pub. No. 20140321212 (hereinafter “Mu”) further in view of
Lu et al., U.S. Patent No. 10665299 (hereinafter “Lu”) further in view of
CHO et al., U.S. Pub. No. 20220164144 (hereinafter “Cho”)
Regarding claim 12: The combination of Luo, Mu, and Lu teaches all limitations of claim 11, from which claim 12 depends.
Luo/Mu/Lu teaches the limitations of the first word line group, of the multiple word line groups, and multiple PEC count thresholds, but Luo/Mu/Lu does not appear to explicitly disclose sets of word lines as claimed: wherein a first word line group, of the multiple word line groups, is associated with a first set of one or more word lines at a first PEC count threshold, of the multiple PEC count thresholds, and wherein the first word line group is associated with a second set of one or more word lines, that is different from the first set of one or more word lines, at a second PEC count threshold, of the multiple PEC count thresholds.
However, Cho teaches wherein a first word line group, of the multiple word line groups, is associated with a first set of one or more word lines at a first PEC count threshold, of the multiple PEC count thresholds, and wherein the first word line group is associated with a second set of one or more word lines, that is different from the first set of one or more word lines, at a second PEC count threshold, of the multiple PEC count thresholds ([0035-0036], Cho teaches that a block may be divided into wordline groups having different characteristics, and that the wordlines connected to blocks may be divided accordingly. Further, in [0142-0144], Cho more explicitly teaches that a number of P/E cycles is obtained for each block and compared to a reference number, and that based on whether it is greater than or less than or equal to the reference numbers, a portion of the wordlines of a group can be moved to a different group or stay in the same group. The wordlines are separated according to the threshold that allows them to belong to one group or the other, but not both. Hence, the wordline groups of Cho are interpreted to correspond to the first and second sets of one or more word lines, different from the other set, at two different PEC count thresholds.)
Luo/Mu/Lu and Cho are analogous art because they are from the same field of endeavor, configurations of memory devices.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Luo/Mu/Lu and Cho to achieve a combined memory system with a block divided into sets of word lines, each set of word lines at one or another PEC count threshold, and where the sets contain word lines different from the word lines found in the other set.
One of ordinary skill in the art would have been motivated to make this modification as a possible embodiment when a system tracks the PEC count per word line, to provide an organization of the word lines that facilitates using look-up tables during data writing to quickly find the characteristics associated with the wordline groups as discussed in Cho [0058] “The control circuit 560 may perform the method of writing data according to an example embodiment. The control circuit 560 may include a look-up table (LUT) 570 that is used while performing the method of writing data according to an example embodiment. For example, the look-up table 570 may include information (e.g., wordline group information) associated with two or more wordline groups included in each memory block obtained by step S100 in FIG. 1.”.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over
Luo et al., U.S. Pub. No. 20210149564 (hereinafter “Luo”) in view of
MU et al., U.S. Pub. No. 20140321212 (hereinafter “Mu”) further in view of
Lu et al., U.S. Patent No. 10665299 (hereinafter “Lu”) further in view of
Prakash et al., U.S. Pub. No. 20210174886 (hereinafter “Prakash”)
Regarding claim 15: The combination of Luo, Mu, and Lu teach all limitations of claim 9, from which claim 15 depends.
While Lu teaches a particular order of programming subblocks and wordlines which programs all subblocks of a wordline first before a second wordline, and does so by doing all the coarse programming on all wordlines before the fine programmings to the same wordlines, Luo/Mu/Lu does not appear to explicitly disclose wherein the multi-fine program scheme is associated with a subblock-first program scheme.
However, Prakash teaches the multi-fine program scheme is associated with a subblock-first program scheme. ([0104], Prakash teaches a multi-pulse programming operation. Further, in [0140], Prakash teaches an option of programming each sub-block before proceeding to the next sub-block, for example, with SB0 being programmed from WL0 to WL95, before then programming SB1 from WL0 to WL95. The combination of the teachings results in a multi-pulse programming scheme that is associated with a subblock-first program scheme.)
Luo/Mu/Lu and Prakash are analogous art because they are from the same field of endeavor, controlling memory write operations.
Luo/Mu/Lu and Prakash each disclose a particular order in which subblocks within wordlines are programmed. One of ordinary skill in the art would have recognized that the order of applying programming to subblocks first of Prakash could have been substituted for the order of applying programming to wordlines first of Luo/Mu/Lu because both the subblock first order and wordline first order serve the purpose of designating an order to program specific subblocks in an array. Furthermore, one of ordinary skill in the art would have been able to carry out the substitution, as both describe a way to select subblocks, and Prakash teaches both orders with the subblock-first order as merely an option alternative to the wordline-first order in [0139-0140]. Finally, the substitution achieves the predictable result of claim 9, with a subblock-first order instead of a wordline-first order.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Luo/Mu/Lu and Prakash to achieve the result of claim 9, in which the multi-fine scheme is associated with a subblock-first program scheme.
Allowable Subject Matter
Claims 1-8 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
The reason for allowability of claim 1 are that the prior art of record, including the references cited in previous office actions, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of A memory device, comprising: one or more components configured to: receive, from a host device, a program command instructing the memory device to program host data to a portion of a memory, the portion of memory comprising at least a first word line and a second word line; determine one of a program erase cycle (PEC) count associated with the portion of the memory or a temperature associated with the portion of the memory; determine, based on the one of the PEC count or the temperature, whether the portion of the memory is associated with a reliability risk; determine, based on the reliability risk, a selected program scheme to be used to program the host data to the portion of the memory, wherein the selected program scheme is one of a single-fine program scheme or a multi-fine program scheme, and wherein the single-fine program scheme or the multi-fine program scheme comprises a coarse pulse applied on each subblock of the first word line, followed by a subsequent coarse pulse applied to a first indexed subblock of the second word line followed by one or more fine pulses applied to a corresponding first indexed subblock of the first word line, followed by an additional coarse pulse applied to a second indexed subblock of the second word line; and execute the program command by programming the host data to the portion of the memory using the selected program scheme.
The closest art of record is Luo, which teaches A memory device, comprising: one or more components configured to: receive, from a host device, a program command instructing the memory device to program host data to a portion of a memory, the portion of memory comprising at least a first word line and a second word line; determine one of a program erase cycle (PEC) count associated with the portion of the memory or a temperature associated with the portion of the memory; determine, based on the one of the PEC count or the temperature, whether the portion of the memory is associated with a reliability risk; determine, based on the reliability risk, a selected program scheme to be used to program the host data to the portion of the memory… execute the program command by programming the host data to the portion of memory using the selected program scheme. but does not teach the selected program scheme is one of a single-fine program scheme or a multi-fine program scheme, and wherein the single-fine program scheme or the multi-fine program scheme comprises a coarse pulse applied on each subblock of the first word line, followed by a subsequent coarse pulse applied to a first indexed subblock of the second word line followed by one or more fine pulses applied to a corresponding first indexed subblock of the first word line, followed by an additional coarse pulse applied to a second indexed subblock of the second word line;
As such, the prior art made of record neither anticipates, nor renders obvious the above-recited combinations for at least the reasons specified.
Regarding claim 1: Luo teaches A memory device, comprising:
one or more components configured to: ([0030], Luo teaches a memory controller component that performs the functionalities of the invention).
receive, from a host device, a program command instructing the memory device to program host data to a portion of a memory, the portion of memory comprising at least a first word line and a second word line; ([0085-0086], Luo teaches that a write command can be received from a host to write data into a storage region. Furthermore, in [0054], Luo teaches that to program data to a cell, programming voltages are applied to selected word lines. While not explicit, the described selected word lines are plural, and therefore, a first word line and a second word line are an obvious embodiment of multiple selected word lines, and the other parts of the writing process are interpreted to apply to a first and a second word line.).
determine one of a program erase cycle (PEC) count associated with the portion of the memory or a temperature associated with the portion of the memory; ([0085], Luo teaches to identify a temperature and P/E cycle metric associated with the region).
determine, based on the one of the PEC count or the temperature, whether the portion of the memory is associated with a reliability risk; ([0085], Luo teaches determining if the identified temperature and P/E cycle metrics fall within identified ranges. Moreover, in [0004] and [0015], Luo explains that temperatures outside of a normal and preferred temperature range results in a cross-temperature condition known to decrease the reliability of the device, and that under operating conditions that result in temperature differences outside of their acceptable ranges, the device may fail or experience unstable operation characteristics, causing reliability concerns. Hence, non-normal temperatures are interpreted to be associated with a reliability risk, and normal temperatures are interpreted to not be associated with a reliability risk.).
determine, based on the reliability risk, a selected program scheme to be used to program the host data to the portion of the memory, wherein ([0086], Luo teaches that based on where the identified temperature or P/E cycle metrics fall within the temperature and P/E cycle ranges, the memory controller selects one of the memory trim sets associated with the temperature range which the current temperature falls within, the memory trim sets defining write operation parameters. Furthermore, in Fig. 5 and [0070], Luo teaches that the there are three defined temperature ranges, with only one corresponding to a normal temperature range. Hence, selecting a trim according to which of a normal and two non-normal temperature ranges the region currently falls into is interpreted to be the claimed based on whether the portion of memory is associated with a reliability risk).
execute the program command by programming the host data to the portion of memory using the selected program scheme. ([0086], Luo teaches the write command is executed to write data using the selected trim values of the trim set).
While Luo teaches several write operation parameters that are defined by trim values, Luo does not appear to explicitly disclose the selected program scheme is one of a single-fine program scheme or a multi-fine program scheme; and wherein the single-fine program scheme or the multi-fine program scheme comprises a coarse pulse applied on each subblock of the first word line, followed by a subsequent coarse pulse applied to a first indexed subblock of the second word line followed by one or more fine pulses applied to a corresponding first indexed subblock of the first word line, followed by an additional coarse pulse applied to a second indexed subblock of the second word line.
Other prior art discloses the selected program scheme is one of a single-fine program scheme or a multi-fine program scheme; and wherein the single-fine program scheme or the multi-fine program scheme comprises a coarse pulse applied on each subblock of the first word line, followed by a subsequent coarse pulse applied to a first indexed subblock of the second word line followed by one or more fine pulses applied to a corresponding first indexed subblock of the first word line, but does not appear to disclose the followed by an additional coarse pulse applied to a second indexed subblock of the second word line.
Therefore, there is no teaching or motivation that would have been known to one of ordinary skill in the art before the effective filing date of the claimed invention to perform a programming scheme with the exact sequence of coarse pulses to every subblock of a first word line, followed by a subsequent coarse pulse to a first subblock of a second word line, followed by one or more fine pulses applied to a first indexed subblock of the first word line, then a coarse pulse applied to a second subblock of a second word line.
Therefore, a rejection for anticipation by Mui or obviousness over Mui in view of the other prior art would be improper.
Claims 2-8 depend on claim 1 and inherit these limitations of the exact sequence of programming pulses, and are allowable for the same reasons.
Conclusion
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/K.H.P./Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
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