DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the communication filed 7/26/2024.
Claims 1-20 are presented for examination.
Examiner Notes
Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirely as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/26/2024. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
“he device memory” at line 3 of page 5 should be: the device memory.
“zero of more” at lines 13 and 16 of page 10 should be: zero or more.
“accelerator 335” at line 1 of page 13 should be: accelerator 125.
Appropriate correction is required.
Claim Objections
Claim 9 is objected to because of the following informalities:
“the host processor” at line 1 of claim 9 should be: a host processor.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding to Claim 10, it is not clear that “the device” at line 1 of claim 10 is used to refer to “A device” at line 1 of claim 8 OR “a storage device” at line 2 of claim 8. If it is used to refer to “a storage device” at line 2 of claim 8, then the whole claim 10 would be same as the limitation “the storage device is configured to store the information regarding the storage device into the memory” at lines 4-5 of claim 8. In this way, such claim 10 would further trigger 112(d) issue since such claim 10 fails to further limit the subject matter of claim 8. If it is used to refer to “A device” at line 1 of claim 8, then such claim 10 without further amendment or clarification can still be interpreted as it is the storage device of the device to be configured to perform the same storing step/action cited at the claim 10 (i.e., it is still same meaning as the limitation at lines 4-5 of claim 8). For the purpose of examination, examiner interprets “the device” from claim 10 is used to refer to “A device” at line 1 of claim 8.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-8, 10-14 and 16-20 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Yarlagadda (US 20220301098 A1).
Regarding to claim 1, Yarlagadda discloses: A device (see computing device 210 from Fig. 2, [0005] and [0025]), comprising:
a memory to store information relating to a request (see Fig. 2, [0005] and [0042]; “a request to process … identifying, from the request, an indication of a region of interest (ROI) of the image to be processed, the ROI comprising a subset of the set of tiles ; generate, by the CPU, a plurality of threads to read tiles and queue the read tiles to be decoded by the GPU” and “Queue size is dynamically maintained based on the availability of free GPU and CPU memory … The queue storing tiles read is stored on CPU memory”); and
a processor to process a data based at least in part on the information relating to the request (see Fig. 2, [0005]; “queue the read tiles to be decoded by the GPU … generate, for the GPU, a plurality of threads to decode the queue of read tiles generated by the CPU; decode, by the GPU, each read tile included in the queue of read tiles according to a prefetching policy”),
wherein the data is stored on a storage device (see Fig. 2, [0005], [0042]; “decode, by the GPU, each read tile included in the queue of read tiles according to a prefetching policy … the second queue including the plurality of decoded tiles” and “The queue storing tiles read is stored on CPU memory”. Note1: either one of queue storing the un-decoded tiles, i.e., mapped to claimed information relating to the request, or the second queue storing the decoded tiles can be considered as this claimed storage device. Note2: the current claim does not specify or requires the relationship between claimed memory and claimed storage device, and thus claimed storage device can be part of the claimed memory); and
wherein a host processor is configured to store the information relating to the request into the memory (see Fig. 2, [0005] and [0042]; “a request to process … identifying, from the request, an indication of a region of interest (ROI) of the image to be processed, the ROI comprising a subset of the set of tiles ; generate, by the CPU, a plurality of threads to read tiles and queue the read tiles to be decoded by the GPU” and “Queue size is dynamically maintained based on the availability of free GPU and CPU memory … The queue storing tiles read is stored on CPU memory”).
Regarding to Claim 3, the rejection of Claim 1 is incorporated and further Yarlagadda discloses: wherein the information relating to the request includes at least one of a submission queue, a completion queue, a packet structure including the request, or a payload structure (see Fig. 2, [0005] and [0042]; “a request to process … identifying, from the request, an indication of a region of interest (ROI) of the image to be processed, the ROI comprising a subset of the set of tiles ; generate, by the CPU, a plurality of threads to read tiles and queue the read tiles to be decoded by the GPU” and “Queue size is dynamically maintained based on the availability of free GPU and CPU memory … The queue storing tiles read is stored on CPU memory”).
Regarding to Claim 4, the rejection of Claim 3 is incorporated and further Yarlagadda discloses: wherein the information relating to the request further includes a kernel (see Fig. 2, [0005], [0021], [0027]; “queue the read tiles to be decoded by the GPU” and “For tile-based scanning, a motorized slide stage can be used to capture a large number of square image frames (“tiles”) that can be assembled into one seamless image”. Note: current claim does not specify or requires what kind of kernel to be related to the request, and thus the queued/stored read tiles or square image frames related to the request are reasonable to be considered as claimed kernel).
Regarding to Claim 5, the rejection of Claim 1 is incorporated and further Yarlagadda discloses: wherein the memory is configured to store a result of the request (see Fig. 2, [0005], [0042]; “generate, for the GPU, a plurality of threads to decode the queue of read tiles generated by the CPU; decode, by the GPU, each read tile included in the queue of read tiles according to a prefetching policy; store, by the GPU, in a second queue, for each decoded tile, a corresponding tensor … the second queue including the plurality of decoded tiles” and “Queue size is dynamically maintained based on the availability of free GPU and CPU memory. Decoding may be performed by the GPU … the queue storing decoded tensors is maintained in the GPU memory”. Note1: either one of decoded tiles or tensors can be considered as claimed result of the request. Note2: the claimed memory can be mapped to the combination of CPU memory and GPU memory from Yarlagadda, and thus the second queue from GPU memory storing the decoded tiles or tensors is still reasonable to be considered as claimed memory storing a result of the request).
Regarding to Claim 6, the rejection of Claim 1 is incorporated and further Yarlagadda discloses: wherein the host processor is configured to allocate a portion of the memory to store the information relating to the request (see Fig. 2, [0005] and [0042]; “a request to process … identifying, from the request, an indication of a region of interest (ROI) of the image to be processed, the ROI comprising a subset of the set of tiles ; generate, by the CPU, a plurality of threads to read tiles and queue the read tiles to be decoded by the GPU … … allocate, in the memory of the CPU, a portion of the memory corresponding to the size of the tile” and “Queue size is dynamically maintained based on the availability of free GPU and CPU memory … The queue storing tiles read is stored on CPU memory”).
Regarding to Claim 7, the rejection of Claim 1 is incorporated and further Yarlagadda discloses: further comprising the storage device (see Fig. 2, [0005], [0042]; “decode, by the GPU, each read tile included in the queue of read tiles according to a prefetching policy; store, by the GPU, in a second queue, for each decoded tile, a corresponding tensor … the second queue including the plurality of decoded tiles” and “Queue size is dynamically maintained based on the availability of free GPU and CPU memory. Decoding may be performed by the GPU … the queue storing decoded tensors is maintained in the GPU memory”).
Regarding to Claim 8, Yarlagadda discloses: A device (see computing device 210 from Fig. 2, [0005] and [0025]), comprising:
a storage device (see Fig. 2, [0005], [0042]; “generate, by the CPU, a plurality of threads to read tiles and queue the read tiles to be decoded by the GPU … decode, by the GPU, each read tile included in the queue of read tiles according to a prefetching policy; store, by the GPU, in a second queue, for each decoded tile, a corresponding tensor … the second queue including the plurality of decoded tiles” and “The queue storing tiles read is stored on CPU memory and the queue storing decoded tensors is maintained in the GPU memory”. Note: either one of the queue storing “the read tiles” or the queue storing “decoded tile” and “tensor” can be considered as claimed storage device); and
a memory to store information regarding the storage device; and wherein the storage device is configured to store the information regarding the storage device into the memory (see Fig. 2, [0005] and [0042]; “a request to process … identifying, from the request, an indication of a region of interest (ROI) of the image to be processed, the ROI comprising a subset of the set of tiles ; generate, by the CPU, a plurality of threads to read tiles and queue the read tiles to be decoded by the GPU” and “Queue size is dynamically maintained based on the availability of free GPU and CPU memory … The queue storing tiles read is stored on CPU memory”. The queue storing un-decoded tiles, i.e., the claimed storage device, is configured to store the information regarding the storage device, i.e., the un-decoded tiles, into the memory, i.e., CPU memory).
Regarding to Claim 10, the rejection of Claim 8 is incorporated and further Yarlagadda discloses: wherein the device is configured to store the information regarding the storage device into the memory (see Fig. 2, [0005] and [0042]; “a request to process … identifying, from the request, an indication of a region of interest (ROI) of the image to be processed, the ROI comprising a subset of the set of tiles ; generate, by the CPU, a plurality of threads to read tiles and queue the read tiles to be decoded by the GPU” and “Queue size is dynamically maintained based on the availability of free GPU and CPU memory … The queue storing tiles read is stored on CPU memory”).
Regarding to Claim 11, the rejection of Claim 8 is incorporated and further Yarlagadda discloses: wherein the information regarding the storage device includes at least one of a static information or a dynamic information (see Fig. 2, [0005] and [0042]; “a request to process … identifying, from the request, an indication of a region of interest (ROI) of the image to be processed, the ROI comprising a subset of the set of tiles ; generate, by the CPU, a plurality of threads to read tiles and queue the read tiles to be decoded by the GPU … store, by the GPU, in a second queue, for each decoded tile, a corresponding tensor … the second queue including the plurality of decoded tiles”. Either one of the un-decoded read tiles, decoded tiles, or tensors are considered as claimed dynamic information. Note: even the two different queues from the CPU memory and GPU memory discussed at [0005] and [0042] are still reasonable to be considered as claimed dynamic information).
Regarding to Claim 12, the rejection of Claim 11 is incorporated and further Yarlagadda discloses: wherein the dynamic information includes runtime statistic information (see Fig. 2, [0005], [0021], [0027]-[0028]; “generating a mapping of the first image, the mapping comprising a set of tiles and, for each tile, a position indicator and a memory size indicator; and identifying, from the request, an indication of a region of interest (ROI) of the image to be processed, the ROI comprising a subset of the set of tiles”, “For tile-based scanning, a motorized slide stage can be used to capture a large number of square image frames (“tiles”) that can be assembled into one seamless image”. Based on the descriptions from [0005], [0021], [0027]-[0028], the tiles or square image frames from Yarlagadda contains certain runtime static information, and thus such tiles are reasonable to be mapped to claimed runtime statistic information).
Regarding to Claim 13, Yarlagadda discloses: A method, comprising:
loading, by a device, information relating to a request from a memory of the device (see Fig. 2, [0003], [0005] and [0042]; “a request to process … identifying, from the request, an indication of a region of interest (ROI) of the image to be processed, the ROI comprising a subset of the set of tiles ; generate, by the CPU, a plurality of threads to read tiles and queue the read tiles to be decoded by the GPU … generate, for the GPU, a plurality of threads to decode the queue of read tiles generated by the CPU” and “Queue size is dynamically maintained based on the availability of free GPU and CPU memory … The queue storing tiles read is stored on CPU memory”. Decoding the queue of read tiles stored on CPU memory requires loading the information, i.e., the queue storing read tiles OR the read tiles themselves, from the memory); and
executing the request on a data using a processor of the device, wherein the data is stored on a storage device (see Fig. 2, [0005]; “generate, by the CPU, a plurality of threads to read tiles and queue the read tiles to be decoded by the GPU … generate, for the GPU, a plurality of threads to decode the queue of read tiles generated by the CPU”. The read tiles, i.e., claimed data, are stored in the queue, i.e., claimed storage device).
Regarding to Claim 14, the rejection of Claim 13 is incorporated and further Yarlagadda discloses: storing, by a host processor, the information relating to the request into the memory of the device (see Fig. 2, [0005] and [0042]; “a request to process … identifying, from the request, an indication of a region of interest (ROI) of the image to be processed, the ROI comprising a subset of the set of tiles ; generate, by the CPU, a plurality of threads to read tiles and queue the read tiles to be decoded by the GPU” and “Queue size is dynamically maintained based on the availability of free GPU and CPU memory … The queue storing tiles read is stored on CPU memory”).
Regarding to Claim 16, Claim 16 is a method claim corresponds to system Claim 3 and is rejected for the same reason set forth in the rejection of Claim 3 above.
Regarding to Claim 17, Claim 17 is a method claim corresponds to system Claim 4 and is rejected for the same reason set forth in the rejection of Claim 4 above.
Regarding to Claim 18, Claim 18 is a method claim corresponds to system Claim 5 and is rejected for the same reason set forth in the rejection of Claim 5 above.
Regarding to Claim 19, the rejection of Claim 18 is incorporated and further Yarlagadda discloses: wherein storing, by the device, the result of the request in the memory of the device includes storing, by the processor, the result of the request in the memory of the device (see Fig. 2, [0005], [0042]; “generate, for the GPU, a plurality of threads to decode the queue of read tiles generated by the CPU; decode, by the GPU, each read tile included in the queue of read tiles according to a prefetching policy; store, by the GPU, in a second queue, for each decoded tile, a corresponding tensor … the second queue including the plurality of decoded tiles” and “Queue size is dynamically maintained based on the availability of free GPU and CPU memory. Decoding may be performed by the GPU … the queue storing decoded tensors is maintained in the GPU memory”).
Regarding to Claim 20, Claim 20 is a method claim corresponds to system Claim 6 and is rejected for the same reason set forth in the rejection of Claim 6 above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 9 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yarlagadda (US 20220301098 A1) in view of Ong et al. (US 10776308 B2, hereafter Ong).
Regarding to Claim 2, the rejection of Claim 1 is incorporated and further Yarlagadda discloses: wherein code or instructions executing on the host processor is configured to store the information relating to the request into the memory (see Fig. 2, [0005] and [0042]; “a request to process … identifying, from the request, an indication of a region of interest (ROI) of the image to be processed, the ROI comprising a subset of the set of tiles ; generate, by the CPU, a plurality of threads to read tiles and queue the read tiles to be decoded by the GPU” and “Queue size is dynamically maintained based on the availability of free GPU and CPU memory … The queue storing tiles read is stored on CPU memory”).
Yarlagadda does not disclose the code or instructions is/are a device driver.
However, Ong discloses: wherein a device driver executing on the [host] processor is configured to store the information [relating to the request] into the memory (see claim 1; “a driver operated by the processor to support an application operated by the processor, wherein the driver is arranged to perform location-aware memory-mapped device accesses to selectively store data into contiguous ones or aggregations of the memory units”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the processing of storing or generating queue or read tile into the memory from Yarlagadda by including storing data or information into memory via executing a device driver by processor from Ong, and thus the combination of Yarlagadda and Ong would disclose missing limitations from Yarlagadda, since a device driver is a well-known and understood software component at a computing device to permit a computer system to communicate with a device.
Regarding to Claim 9, the rejection of Claim 8 is incorporated and further Yarlagadda discloses: wherein code or instructions executing on the host processor is configured to load the information regarding the storage device from the memory (see Fig. 2, [0003], [0005] and [0042]; “a request to process … identifying, from the request, an indication of a region of interest (ROI) of the image to be processed, the ROI comprising a subset of the set of tiles ; generate, by the CPU, a plurality of threads to read tiles and queue the read tiles to be decoded by the GPU … generate, for the GPU, a plurality of threads to decode the queue of read tiles generated by the CPU” and “Queue size is dynamically maintained based on the availability of free GPU and CPU memory … The queue storing tiles read is stored on CPU memory”. Decoding the queue of read tiles stored on CPU memory requires loading the information, i.e., the queue storing read tiles OR the read tiles themselves, from the memory.
Yarlagadda does not disclose the code or instructions is/are a device driver.
However, Ong discloses: wherein a device driver executing on the [host] processor is configured to load the information [regarding the storage device] from the memory (see claim 1; “a driver operated by the processor to support an application operated by the processor, wherein the driver is arranged to perform location-aware memory-mapped device accesses to selectively … load data from selected contiguous ones or aggregations of the plurality of memory units”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the processing of loading read tile for decoding process from the memory from Yarlagadda by including loading data or information from memory via executing a device driver by processor from Ong, and thus the combination of Yarlagadda and Ong would disclose missing limitations from Yarlagadda, since a device driver is a well-known and understood software component at a computing device to permit a computer system to communicate with a device.
Regarding to Claim 15, Claim 15 is a method claim corresponds to system Claim 2 and is rejected for the same reason set forth in the rejection of Claim 2 above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Narayanan (US 20190243571 A1) discloses: receive, from the host processor, configuration commands to cause the control logic to configure read and write buffers in the memory space and configure submission queues in the memory space, wherein the control logic adds the read commands to the submission queues to cause source storage devices to transfer data to the read buffers and adds write commands to submission queues for the transfer data in the write buffers to cause destination storage devices to write the transfer data in the write buffers to the destination storage devices (see [0065]).
Shimada et al. (US 20230075635 A1) discloses: a queue region is set on the memory 102A in advance, and the read command received from the host computer is stored in the queue region. Further, the small CPU 101A acquires the read command from the queue region on the memory 102A and analyzes the read command (201) (see [0069]) and in response to the read request from the small CPU 101A, the large CPU 106A reads, from the SSD 109, the read data specified by the host computer (see [0071]).
Best et al. (US 20140351626 A1) discloses: Controller 68 comprises a controller processor 70, a non-volatile memory 72 and a volatile memory 74. Controller processor 70 is configured to execute a controller application 76 from non-volatile memory 72 that enables module 36 to access (i.e., read/write) data on storage media 66 in order to process I/O requests received from module processor 60. In embodiments where storage device 50 comprises a hard disk, processor 70 executes controller application 76 to control motors (not shown) on the storage device, and to command disk heads (not shown) to read or write data (see [0029]-[0032]).
Gibb et al. (US 20200050401 A1) discloses: NVMe disk access commands, such as for example read/write commands, are sent from the host CPU to the controller of the storage device using command queues (see [0038]).
Mak (US 9910705 B1) discloses: the processor 114 may be instructed by the offload driver 112 to load the appropriate data from the shared memory 106 into the memory 116 (see Fig. 1, lines 14-23 of col. 5).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHI CHEN whose telephone number is (571)272-0805. The examiner can normally be reached on M-F from 9:30AM to 5:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Y Blair can be reached on 571-270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Zhi Chen/
Patent Examiner, AU2196
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196
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