DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/14/2026 has been entered.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in France on 8/3/2023. It is noted, however, that applicant has not filed a certified copy of the FR 2308428 application as required by 37 CFR 1.55.
Claim Objections
Claims 1 – 13 are objected to because of the following informalities: Line 18 states, “the or each data producing/consuming partition…”. This is grammatically incorrect. Claims 2 – 13 inherit and do not correct this. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4, and 12 – 13 are rejected under 35 U.S.C. 103 as being unpatentable over Sanderson et al. US Patent Application Publication No. 2021/0081251 (herein after referred to as Sanderson) in view of Pop et al. US Application Publication No. 2010/0070730 (herein after referred to as Pop) in view of Brief US Patent No. 8286188 (herein after referred to as Brief).
Regarding claim 1, Sanderson describes a platform for executing avionics applications (…the avionics platform 10 includes a memory 12, an operating system 20, a processor 21, a set 19 of input/output peripherals and an electronic control device 24 (page 2, paragraph [0047])), comprising: a multi-core processor (The processor 21… is a multicore processor… (page 3, paragraph [0055])); a management unit (…an electronic control device 24 (page 2, paragraph [0047]). The electronic control device 24 for example includes a memory 26… and an electronic control unit 25 (page 3, paragraph [0059])); a plurality of shared resources (…the avionics platform 10 includes… a set 19 of input and/or output peripherals… (page 2, paragraph [0047]). According to the invention, the partitions PARTAPP1 and PARTAPP2 are defined such that these access commands to the IO peripherals are sent to the partition for access to the IO peripherals PARTSERV_IO (page 3, paragraph [0063])); and a memory comprising (…a memory 12 (page 2, paragraph [0047])): a plurality of avionics partitions executing a plurality of avionics applications by said multi-core processor (The memory 12 stores a plurality of partitions 14. These partitions 14 include the partitions PARTAPPi, with i=1 to m, m being an integer greater than or equal to 2, which are software applications also called avionics functions… (page 2, paragraphs [0049] – [0050]). The electronic control unit 25 of the electronic control device 24 is suitable for sequencing the execution of the partitions on the processor 21… (page 3, paragraph [0060])); an input/output (IO) server for access to shared resources by said avionics partitions (According to the invention, the partitions further include a specific partition PARTSERV_IO 14, called partition for access to the IO peripherals. This partition PARTSERV_IO 14 is suitable for centralizing the exchanges with the IO peripherals 18 (page 2, paragraph [0051])); and a shared memory space, access of which is controlled by said management unit (The allocations are determined by said control unit 25. The predetermined times are in particular calculated based on a time allocation budgeted for each partition during the installation thereof on the platform 1, according to targeted performance objectives (page 3, paragraph [0062]). The exchanges between the partition PARTSERV_IO for access to the IO resources and the avionics partitions PARTAPP1 and PARTAPP2, comprising the transmission of these commands, then the provision of the result of the implementation of these commands, are done via a memory, for example of the nondedicated volatile RAM type, referenced 15 in Fig. 1, in which the avionics partitions PARTAPP1 and PARTAPP2 write the access commands to the IO peripherals, in which the partition PARTSERV_IO reads these commands, then writes the result therein of the performance of these commands following the reading/writing in the IO peripherals indicated in the commands and lastly in which the avionics partitions PARTAPP1 and PARTAPP2 extract the result of their commands for access of the IO peripherals (page 3, paragraph [0070])). In one embodiment, the commands and results of commands assume the form of messages, based on the programming interface (API) of standard A653: the applications PARTAPP1 and PARTAPP2 acquire messages previously read by the partition PARTSERV_IO and push messages toward the partition PARTSERV_IO for the physical sending of these messages toward IO1 or IO2 during its next time allocation (page 3, paragraph [0071]). A budget in terms of the use of the memory and a budget in terms of usage time of the processor (based on which the predetermined time will be set indicated in each allocation of the allocation list 27)… (page 3, paragraph [0072])), the shared memory space performing data sharing between a data producing partition and a predetermined group of N data consuming partitions exclusively via a data sharing structure outside the data producing and data consuming partitions, allocated in the shared memory space (In one embodiment, the commands and results of commands assume the form of messages, based on the programming interface (API) of standard A653: the applications PARTAPP1 and PARTAPP2 acquire messages previously read by the partition PARTSERV_IO and push messages toward the partition PARTSERV_IO for the physical sending of these messages toward IO1 or IO2 during its next time allocation (page 3, paragraph [0071]). …The electronic control unit 25 of the electronic control device 24 is suitable for sequencing the execution of the partitions on the processor 21 based on a sequential list of allocations 27 stored for example in the memory 26 (page 3, paragraph [0060]). …During this time t2, each partition PARTAPPi, i=1, 2 writes, in the RAM 15, its commands for access to the peripherals IO1, IO2 18 (in the form of messages to be emitted in the API case of standard A653) and extracts, from the RAM, the access command results previously deposited in the RAM (in the form of acquired messages in the API case of standard A653) by the partition PARTSERV_IO 14 (page 4, paragraph [0081]). Fig. 1 shows RAM 15 being outside and separate from the producing/consuming partitions PARTAPP1 14, PARTAPP2 14, and PARTSERV_IO 14), the or each data producing/consuming partition corresponding to said IO server or to one of said avionics partitions, the data sharing structure comprising at least two saving addresses which are used by the data producing partition to write two different data (…During this time t2, each partition PARTAPPi, i=1, 2 writes, in the RAM 15, its commands for access to the peripherals IO1, IO2 18 (in the form of messages to be emitted in the API case of standard A653) and extracts, from the RAM, the access command results previously deposited in the RAM (in the form of acquired messages in the API case of standard A653) by the partition PARTSERV_IO 14 (page 4, paragraph [0081]). In the case that each of the two partitions are depositing messages in the memory RAM 15 they must be written to two different memory locations in order to be read out successfully). Sanderson does not specifically disclose the guarantee that the shared memory space is shared in accordance with read and write permissions for each partition at any given address, the data sharing structure comprising at least N+2 saving addresses, nor being enabling concurrent read and write whereby said IO sever writes a following datum at an address while said avionics partitions read a preceding datum at another address.
Pop describes a system for minimizing memory access conflicts of process communication channels. Specifically, the reference presents examples of synchronization that are used to ensure a producer and consumer do not concurrently access the same memory location. A producer may correspond to a processor core, such as processor core 112a in Fig. 1, supplying data, such as in an array, while executing a task or a thread. A consumer may correspond to a processor core, such as processor core 112b in Fig. 1, retrieving data, such as in an array, while executing a parallel task or a parallel thread. For example, referring to Fig. 3A, one embodiment of a source code pattern with regular data dependences within an array is shown. Automatic parallelization techniques based on data dependence analysis information (page 3, paragraph [0034]). While processor core 112b is executing a producer task, producing data for stream copies 440 and 460, and filling data copy 414b to be subsequently sent to producer sliding windows 444 and 464, processor core 112a may be concurrently executing a consumer task, reading data from stream copy 440, and reading from data copy 414a which was previously read from consumer sliding window 442. Consumer sliding window 442, and correspondingly 462, may be full and designated for reading data by core 112a. In fact, a snapshot in the middle of code execution may show core 112a is reading data for the loop of lines 9-11, which is presently stored in filled space 446. The pointers within stream 440 may have been updated and core 112a is now allowed to begin reading consumer sliding window 442 which has new data. More up-to-date copies of consumer sliding window 442 may be found in the cache hierarchy, such as data copies 418a and 414a. The size of the consumer sliding window may be the same size as the producer sliding window for ease of implementation sake. Alternatively, when core 112a has permission to read from a window due to no overlap of the producer and consumer sliding windows, rather than read data from stream copy 440, core 112a may send a communicative probe to locate required data. If a copy of the required updated data is in cache 416b or 412b of processing unit 420b, then a copy of the required data may be sent from processing unit 420b to cache 412a (page 4, paragraph [0047]). The embodiment shown in FIG. 4 is for illustrative purposes only. In other embodiments, more than two processing units 420 may be included in a system and more than one stream 440 may be concurrently implemented in shared cache memory 440 and main memory 450. In the above example, the producer sliding window 444 and consumer sliding window 442 are shown moving from left to right, but in other embodiments, they may move from right to left. Also, the producer sliding window 444 may wrap around stream 440 during execution and, in a snapshot, be located to the left of consumer sliding window 442. Also, for a multi-core processor implementation, a stream 440 may correspond to a single processor and to a single processing unit 420, wherein a producer sliding window 444 corresponds to a first core within a multi-core processor and consumer sliding window 442 corresponds to a second core within the same multi-core processor. Other combinations and embodiments are possible and contemplated (page 4, paragraph [0049]). Each sliding window has a size of 64 bytes (64B) and each element within a window has a size of 4B. Therefore, there are 16 elements per sliding window and the entire stream is 64KB in size (page 6, paragraph [0061]). In the example, one producer and consumer are described, therefore N+2 would be 4. There are 16 elements in each window in addition to the elements outside of the windows. This configuration would suggest “at least N+2 saving addresses”.
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Pop teachings in the Sanderson system. Skilled artisan would have been motivated to incorporate the method of sliding windows for consumers and producers as taught by Pop in the Sanderson system for effectively managing access to shared memory space without explicit locking. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as multi-core systems with shared memory. This close relation between both of the references highly suggests an expectation of success.
Brief discloses a method for advanced interprocess communication. Specifically, the described interprocess memory controller may maintain a set of permissions for each buffer allocated from shared memory by the respective processes in a multi-process device. For example, when a process allocates a buffer from the shared memory, the described interprocess memory controller may allocate permission to write to, and to free, the allocated buffer to the allocating process. Such allocated permissions may be stored by the described interprocess memory controller, in association with the allocated buffer, in physical memory. When a pointer to a buffer is passed, or transferred, from a first process, i.e., the sending process, to a second process, i.e., the receiving process, as part of an interprocess communication, the described interprocess memory controller may reallocate permission to write to, and to free, the allocated buffer to the receiving process by updating the buffer's permission data stored in physical memory. In this manner, the efficiency of interprocess communication is greatly increased and the integrity of the shared memory is maintained (column 3, lines 1 – 19).
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Brief teachings in the Sanderson in view of Pop system. Skilled artisan would have been motivated to incorporate the method of including an interprocess memory controller configured to maintain a set of permissions as taught by Brief in the Sanderson in view of Pop system for effectively managing permissions to shared memory in a way that the efficiency of interprocess communication is greatly increased and the integrity of the shared memory is maintained (column 3, lines 16 – 19). In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as multi-core systems with shared memory. This close relation between both of the references highly suggests an expectation of success.
Regarding claim 4, Sanderson in view of Pop and Brief describe the platform according to claim 1 (see above), wherein the data sharing structure further comprises at least one metadatum for determining a data saving address to be used by the or each data producing/consuming partition (Sanderson clearly discloses that the partitions write messages into RAM. In order to write data into memory it is necessarily inherent that some form of addressing is used).
Regarding claim 12, Sanderson in view of Pop and Brief describe a method for executing avionics applications, implemented by the platform according to claim 1 (see above), the method comprising writing two different data into two saving addresses of the or each data sharing structure, by the data producing partition (…During this time t2, each partition PARTAPPi, i=1, 2 writes, in the RAM 15, its commands for access to the peripherals IO1, IO2 18 (in the form of messages to be emitted in the API case of standard A653) and extracts, from the RAM, the access command results previously deposited in the RAM (in the form of acquired messages in the API case of standard A653) by the partition PARTSERV_IO 14 (Sanderson, page 4, paragraph [0081]). The act of writing data to a location may be interpreted as “producing” since stored data is produced from the perspective of the memory).
Regarding claim 13, Sanderson in view of Pop and Brief describe a non-transient computer-readable medium comprising instructions which, when executed by a programmable electronic system cause the programmable electronic system to, implement a method according to claim 12 (…software instructions of the compute program stored in a memory (Sanderson, page 5, paragraph [0095])).
Claims 2 – 3 are rejected under 35 U.S.C. 103 as being unpatentable over Sanderson in view of Pop and Brief, further in view of Polley et al. US Patent No. 11048548 (herein after referred to as Polley).
Regarding claim 2, Sanderson in view of Pop and Brief describe the platform according to claim 1 (see above), wherein said shared memory space comprises for each of said avionics partitions, a second shared memory zone (The exchanges between the partition PARTSERV_IO for access to the IO resources and the avionics partitions PARTAPP1 and PARTAPP2, comprising the transmission of these commands, then the provision of the result of the implementation of these commands, are done via a memory, for example of the nondedicated volatile RAM type, referenced 15 in Fig. 1, in which the avionics partitions PARTAPP1 and PARTAPP2 write the access commands to the IO peripherals, in which the partition PARTSERV_IO reads these commands, then write the result therein of the performance of these commands following the reading/writing in the IO peripherals indicated in the commands and lastly in which the avionics partitions PARTAPP1 and PARTAPP2 extract the result of their commands for access to the IO peripherals (Sanderson, page 3, paragraph [0070])) and each second shared memory zone being read/write accessible to the corresponding avionics partition (Sanderson, page 3, paragraph [0070]), wherein said management unit makes the different avionics partitions follow the reading/writing in the different zones. Sanderson does not specifically disclose first shared memory zone, wherein the first shared memory zone being read-only accessible to all of said avionics partitions.
Polley describes a multi-core processing environment capable of quantifying shared system resources access includes several processing cores, each core having several applications running thereon and accessing SSRs via virtual machines. Specifically, it is disclosed that each processing core may incorporate one or more guest operating systems 118 and user applications (e.g., avionics applications) executing thereon. Shared system resources may include but are not limited to, system memory, flash memory, non-volatile memory, or types of read-only memory (ROM) (column 4, lines 26 – 55).
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Polley teachings in the Sanderson in view of Pop and Brief system. Skilled artisan would have been motivated to incorporate the method of using read-only memory in an avionics system as taught by Polley in the Sanderson in view of Pop and Brief system for effectively providing a conventional memory type (read-only). In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as multi-core avionics systems. This close relation between both of the references highly suggests an expectation of success.
Regarding claim 3, Sanderson in view of Pop, Brief, and Polley describe the platform according to claim 2 (see above) wherein the data sharing structure is distributed between the zones according to the need thereof to write/read corresponding data (Sanderson, page 3, paragraph [0070]).
Claims 5 – 11 are rejected under 35 U.S.C. 103 as being unpatentable over Sanderson in view of Pop and Brief, further in view of Gayen et al. US Patent Application Publication No. 2024/0126555 (herein after referred to as Gayen).
Regarding claim 5, Sanderson in view of Pop and Brief describe the platform according to claim 1 (see above). While Sanderson discloses the partitions that act as consumers/producers it does not explicitly describe wherein the data sharing structure has a structure of a first type when N is strictly greater than 1, wherein the data producing partition corresponds to said IO server and each data consuming partition corresponds to one of said avionics partitions, and wherein the structure of the first type comprises N+2 saving addresses.
Gayen describes a method including receiving a request for a chained accelerator operation, and configuring a chain of accelerators to perform the chained accelerator operation. Specifically, several different addressing models may optionally be used to address data in the storage. In some embodiments, a “scratchpad address” addressing model may optionally be used. At configuration/allocation time, for a given operation in the chain, the producer and consumer accelerators may record which scratchpad they are respectively writing to or reading from and the starting location in that scratchpad for the respective output or input buffer. To access data, an accelerator addresses a specific location relative to the start address in the scratchpad. For example, to read the Xth byte of input data, it would load “start address+(X-1)” (page 29, paragraph [0279]). Additionally, in a “memory mapped” addressing model system software may directly read/write the buffers from other devices that have permission to that portion of the physical address space (page 29, paragraph [0280]).
Therefore, it would have been obvious to a person of ordinary skill in the computer art before the effective filing date of the claimed invention to incorporate the Gayen teachings in the Sanderson in view of Pop and Brief system. Skilled artisan would have been motivated to incorporate the method of providing access to shared memory space including using starting and ending address as taught by Gayen in the Sanderson in view of Pop and Brief system for effectively managing access to shared memory space. In addition, both of the references teach features that are directed to analogous art and they are directed to the same field of endeavor, such as multi-core systems with shared memory. This close relation between both of the references highly suggests an expectation of success.
Regarding claim 6, Sanderson in view of in view of Pop, Brief, and Gayen describe the platform according to claim 5 (see above), wherein among the N+2 saving addresses of the structure of the first type, two addresses are dedicated to the writing by the data producing partition of a preceding datum and a following datum, and N other addresses are dedicated to the reading by each of the N data consuming partitions of the predetermined group, of the preceding datum (Gayen, page 29, paragraphs [0279] and [0280]).
Regarding claim 7, Sanderson in view of Pop, Brief, and Gayen describe the platform according to claim 5 (see above), wherein said shared memory space comprises a structure of the first type for each group of N avionics partitions sharing the data produced by said IO server (Gayen, page 29, paragraphs [0279] and [0280]) (Sanderson, page 3, paragraph [0070]).
Regarding claim 8, Sanderson in view of Pop, Brief, and Gayen describe the platform according to claim 5 (see above), wherein the data sharing structure has a structure of a second type when N equals 1, the data producing partition corresponding to said IO server and the data consuming partition corresponding to a single avionics partition, wherein the at least two saving addresses form a queue for reading/writing a preceding datum and a following datum (Gayen, page 29, paragraphs [0279] and [0280]) (Sanderson, page 3, paragraph [0070]).
Regarding claim 9, Sanderson in view of Pop, Brief, and Gayen describe the platform according to claim 5 (see above), wherein the data sharing structure has a structure of a third type when N is equal to 1, the producer partition corresponding to a single avionics partition and the consumer partition corresponding to said IO server, and wherein the at least two saving addresses form a queue for reading/writing a preceding datum and a following datum (Gayen, page 29, paragraphs [0279] and [0280]) (Sanderson, page 3, paragraph [0070]).
Regarding claim 10, Sanderson in view of Pop, Brief, and Gayen describe the platform according to claim 5 (see above), wherein said shared memory space comprises a plurality of data sharing structures, each data sharing structure corresponding to a structure of the first type, a structure of a second type, or a structure of a third type (Gayen, page 29, paragraphs [0279] and [0280]) (Sanderson, page 3, paragraph [0070]).
Regarding claim 11, Sanderson in view of Pop, Brief, and Gayen describe the platform according to claim 5 (see above), wherein said shared memory space comprises: a plurality of data sharing structures, each data sharing structure corresponding to a structure of the first type, a structure of a second type or a structure of a third type; and a structure of the second type and/or a structure of the third type for each of said avionics partitions, wherein the data sharing structure has a structure of the second type when N equals 1, wherein the data producing partition corresponds to said IO server, wherein the data consuming partition corresponds to a single one of said avionics partitions, and wherein the at least two saving addresses form a queue for reading/writing a preceding datum and a following datum (Gayen, page 29, paragraphs [0279] and [0280]) (Sanderson, page 3, paragraph [0070]).
Response to Arguments
Applicant argues, with respect to claim 1, that Sanderson does not teach or suggest that the amended limitations. Examiner has clarified the rejection by adding the references Pop and Brief, which are believed to obviously suggest the amended limitations.
Applicant argues, with respect to the remaining claims, that they depend from claim 1 and are therefore allowable for the same reasons argued. Examiner refers to rejections and responses above as to why these claims are not currently allowable.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RALPH A VERDERAMO III whose telephone number is (571)270-1174. The examiner can normally be reached Monday through Friday 8:30 AM - 5:00 PM.
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/RALPH A VERDERAMO III/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
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May 23, 2026
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