DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement filed on July 28, 2024 has been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1, 4-6, 9-11, 14-16, 19-21 and 24-25, the terms “N” and “D” render the claims vague and indefinite because the claims and/or specification fail to explicitly define “N” nor “D” such that it unclear what is “N” and “D” referring to numerical value, and/or the range of the value. Claims 2-3, 7-8, 12-13, 17-18 and 22-23 are also rejected because of depending on independent claims 1, 6, 11, 16 and 21, respectively, containing the same deficiency.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 5-8, 10-13, 15-18, 20-23 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Dunaisky et al. (US 2015/0097847 A1, hereinafter Dunaisky) in view of Landers et al. (US 2024/0160571 A1, hereinafter Landers).
Regarding claim 1, Dunaisky discloses a computer-implemented method comprising: configuring a configuration of a crossbar of a memory management unit as shown in figure 2 comprising a set of regions of N workers (figure 2, 208(0)-208(C-1)) and D partitions (figure 2, 215(0)-215(D-1)); writing by a worker, to D partitions in the set of regions of the crossbar ([0035], a given GPCs may process data to be written to any of the DRAMs within PP memory, and crossbar unit is configured to route the output of each GPC to the input of any partition unit or to any other GPC for further processing); and reading by a partition, N regions in the set of regions of the crossbar ([0035], GPCs communicate with memory interface 214 via crossbar unit 210 to read from or write to various DRAMs) wherein each of the N regions is assigned an address that is mapped to a physical memory address ([0044], each GPC may have an associated memory management unit that is configured to map virtual addresses into physical addresses). Dunaisky also discloses a method for processing a request to access data via a virtual memory address as shown in figure 6. Dunaisky differs from the claimed invention in not specifically teaching that an access control is achieved by the configuration of a N plus D mapping of workers to partitions of the crossbar of the memory management unit. However, Landers teaches to configure the crossbars in each cache domain to use a hash function that only maps to the cache banks in that same cache domain, i.e., if the processor is partitioned, the crossbars of the first cache domain configured to use a hash function that only maps to the first cache bank and the second cache bank, in order to utilize different hash functions during operation of the distributed cache ([0143]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Dunaisky in having that an access control is achieved by the configuration of a N plus D mapping of workers to partitions of the crossbar of the memory management unit, as per teaching of Landers, in order to utilize different hash functions during operation of the distributed cache.
Regarding claim 2, Dunaisky teaches that mapping the address to a physical memory address is performed by a hardware interposer ([0077], the PPU implements sparse data memory management in hardware to efficiently and deterministically support sparse mappings).
Regarding claim 3, Dunaisky teaches that the configuring is performed offline and the memory management unit is statically configured ([0043], SMs also have access to off-chip "global" memory, which may include PP memory and/or system memory and a level one-point-five cache may be included within GPC and configured to receive and hold data requested from memory via memory interface by SM).
Regarding claim 5, Dunaisky discloses that addresses of the N regions are consecutive (figure 4).
Regarding claim 6, the claimed limitations are rejected as the same reasons as set forth in claim 1.
Regarding claim 7, the claimed limitations are rejected as the same reasons as set forth in claim 2.
Regarding claim 8, the claimed limitations are rejected as the same reasons as set forth in claim 3.
Regarding claim 10, the claimed limitations are rejected as the same reasons as set forth in claim 5.
Regarding claim 11, the claimed limitations are rejected as the same reasons as set forth in claim 1.
Regarding claim 12, the claimed limitations are rejected as the same reasons as set forth in claim 2.
Regarding claim 13, the claimed limitations are rejected as the same reasons as set forth in claim 3.
Regarding claim 15, the claimed limitations are rejected as the same reasons as set forth in claim 5.
Regarding claim 16, the claimed limitations are rejected as the same reasons as set forth in claim 1.
Regarding claim 17, the claimed limitations are rejected as the same reasons as set forth in claim 2.
Regarding claim 18, the claimed limitations are rejected as the same reasons as set forth in claim 3.
Regarding claim 20, the claimed limitations are rejected as the same reasons as set forth in claim 5.
Regarding claim 21, the claimed limitations are rejected as the same reasons as set forth in claim 1.
Regarding claim 22, the claimed limitations are rejected as the same reasons as set forth in claim 2.
Regarding claim 23, the claimed limitations are rejected as the same reasons as set forth in claim 3.
Regarding claim 25, the claimed limitations are rejected as the same reasons as set forth in claim 5.
Allowable Subject Matter
Claims 4, 9, 14, 19 and 24 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Steven et al. (US 2022/0067513 A1) discloses a system comprising a memory management unit providing translation of virtual addresses into physical addresses, memory protection, arbitration of memory requests, and routed to a different general processing cluster via the crossbar (figures 16-17 and [0123]-[0139]).
Lim et al. (US 2024/0403177 A1) discloses a memory management data structures modified to unmap the virtual address that points to the target physical page address to thereby make the OS unaware of the offlined page (abstract).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHUO H LI whose telephone number is (571)272-4183. The examiner can normally be reached Mon. Tue. and Thurs. 8:00-4:00 PM.
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/ZHUO H LI/Primary Examiner, Art Unit 2133