DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Email Communication
Applicant is encouraged to authorize the Examiner to communicate with applicant via email by filing form PTO/SB/439 either via USPS, Central Fax, or EFS-Web. See MPEP 502.01, 502.03, 502.05.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 9-11, & 13-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Naito et al. (US 6,549,395).
In regards to claim 1, Naito ‘395 discloses
A multilayer ceramic capacitor comprising:
a capacitor body (55 – fig. 13; C10:L65 to C11:L56) in which a plurality of dielectric layers (52 – fig. 13; C10:L65 to C11:L56), a plurality of first inner electrodes (53 – fig. 13; C10:L65 to C11:L56), and a plurality of second inner electrodes (54 – fig. 13; C10:L65 to C11:L56) are laminated;
first via conductors (56 – fig. 13; C10:L65 to C11:L56) provided inside the capacitor body and electrically connected to the plurality of first inner electrodes;
second via conductors (57 – fig. 13; C10:L65 to C11:L56) provided inside the capacitor body and electrically connected to the plurality of second inner electrodes;
first outer electrodes provided on a surface of the capacitor body and electrically connected to the first via conductors (C10:L65 to C11:L56); and
second outer electrodes provided on a surface of the capacitor body and electrically connected to the second via conductors (C10:L65 to C11:L56);
wherein in a reference layout in which m×n (m and n are each a natural number of 4 or more) virtual lattice points are set in a view of the capacitor body seen in a lamination direction of the dielectric layers, the first inner electrodes, and the second inner electrodes, and in which via conductors including the first via conductors and the second via conductors are arranged at all the virtual lattice points, the first via conductors and the second via conductors are not arranged at least in portion of (m-2)×(n-2) of the virtual lattice points located inside outermost peripheral virtual lattice points (fig. 13).
In regards to claim 2, Naito ‘395 discloses
The multilayer ceramic capacitor according to claim 1, wherein a difference between a number of the first via conductors and a number of the second via conductors is 1 or less (fig. 13).
In regards to claim 3, Naito ‘395 discloses
The multilayer ceramic capacitor according to claim 1, wherein the virtual lattice points at which the first via conductors and the second via conductors are not arranged are the virtual lattice points corresponding to the via conductors through each of which a current flows when a voltage is applied between the first outer electrodes and the second outer electrodes in the reference layout, among the virtual lattice points located inside the outermost peripheral virtual lattice points in the reference layout (fig. 13).
In regards to claim 4, Naito ‘395 discloses
The multilayer ceramic capacitor according to claim 1, wherein a plurality of the virtual lattice points at which the first via conductors and the second via conductors are arranged are in a symmetric layout (fig. 13).
In regards to claim 5, Naito ‘395 discloses
The multilayer ceramic capacitor according to claim 1, wherein the first outer electrodes and the second outer electrodes are provided on only one of a first major surface and a second major surface opposed to each other in the lamination direction among surfaces of the capacitor body (fig. 1-2; C10:L65 to C11:L56).
In regards to claim 6, Naito ‘395 discloses
The multilayer ceramic capacitor according to claim 1, wherein the capacitor body has a rectangular or substantially rectangular parallelepiped shape (fig. 1-2; C10:L65 to C11:L56).
In regards to claim 9, Naito ‘395 discloses
The multilayer ceramic capacitor according to claim 1, wherein a total number of the first inner electrodes and the second inner electrodes is about 10 to about 150 (C12:L21-28).
In regards to claim 10, Naito ‘395 discloses
The multilayer ceramic capacitor according to claim 1, wherein each of the first via conductors and the second via conductors has a columnar shape (fig. 1-2 & 13).
In regards to claim 11, Naito ‘395 discloses
The multilayer ceramic capacitor according to claim 1, wherein a diameter of each of the first via conductors and the second via conductors is about 30 μm or more and about 150 μm or less (C12:L21-28).
In regards to claim 13, Naito ‘395 discloses
The multilayer ceramic capacitor according to claim 1, wherein m and n are each equal to 5 (table 2).
In regards to claim 14, Naito ‘395 discloses
The multilayer ceramic capacitor according to claim 4, wherein the symmetric layout is line symmetric or point symmetric (fig. 13).
In regards to claim 15, Naito ‘395 discloses
The multilayer ceramic capacitor according to claim 1, wherein a number of the first via conductors and a number of the second via conductors is equal (fig. 13).
Claim(s) 1-2, 4, 6, 10, & 14-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Togashi et al. (US 2005/0207093).
In regards to claim 1, Togashi ‘093 discloses
A multilayer ceramic capacitor comprising:
a capacitor body (fig. 1-3; [0036]) in which a plurality of dielectric layers (14 – fig. 2; [0037]), a plurality of first inner electrodes (16 – fig. 2; [0037]), and a plurality of second inner electrodes (18 – fig. 2; [0037]) are laminated;
first via conductors (25 – fig. 2; [0046]) provided inside the capacitor body and electrically connected to the plurality of first inner electrodes;
second via conductors (26 – fig. 2; [0047]) provided inside the capacitor body and electrically connected to the plurality of second inner electrodes;
first outer electrodes (31 – fig. 2; [0042]) provided on a surface of the capacitor body and electrically connected to the first via conductors; and
second outer electrodes (32 – fig. 2; [0042]) provided on a surface of the capacitor body and electrically connected to the second via conductors;
wherein in a reference layout in which m×n (m and n are each a natural number of 4 or more) virtual lattice points are set in a view of the capacitor body seen in a lamination direction of the dielectric layers, the first inner electrodes, and the second inner electrodes, and in which via conductors including the first via conductors and the second via conductors are arranged at all the virtual lattice points, the first via conductors and the second via conductors are not arranged at least in portion of (m-2)×(n-2) of the virtual lattice points located inside outermost peripheral virtual lattice points (fig. 1).
In regards to claim 2, Togashi ‘093 discloses
The multilayer ceramic capacitor according to claim 1, wherein a difference between a number of the first via conductors and a number of the second via conductors is 1 or less (fig. 1).
In regards to claim 4, Togashi ‘093 discloses
The multilayer ceramic capacitor according to claim 1, wherein a plurality of the virtual lattice points at which the first via conductors and the second via conductors are arranged are in a symmetric layout (fig. 1).
In regards to claim 6, Togashi ‘093 discloses
The multilayer ceramic capacitor according to claim 1, wherein the capacitor body has a rectangular or substantially rectangular parallelepiped shape (fig. 1-3).
In regards to claim 10, Togashi ‘093 discloses
The multilayer ceramic capacitor according to claim 1, wherein each of the first via conductors and the second via conductors has a columnar shape (fig. 1; [0046-0047]).
In regards to claim 14, Togashi ‘093 discloses
The multilayer ceramic capacitor according to claim 4, wherein the symmetric layout is line symmetric or point symmetric (fig. 1).
In regards to claim 15, Togashi ‘093 discloses
The multilayer ceramic capacitor according to claim 1, wherein a number of the first via conductors and a number of the second via conductors is equal (fig. 1).
Claim(s) 1-4, 6, 10, 14-16, & 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakamura et al. (US 2009/0021887).
In regards to claim 1, Nakamura ‘887 discloses
A multilayer ceramic capacitor comprising:
a capacitor body in which a plurality of dielectric layers (2 – fig. 1; [0027]), a plurality of first inner electrodes (3a – fig. 1; [0027]), and a plurality of second inner electrodes (3b – fig. 1; [0027])are laminated;
first via conductors (4a – fig. 1; [0027]) provided inside the capacitor body and electrically connected to the plurality of first inner electrodes;
second via conductors (4b – fig. 1; [0027]) provided inside the capacitor body and electrically connected to the plurality of second inner electrodes;
first outer electrodes (5a – fig. 1; [0027]) provided on a surface of the capacitor body and electrically connected to the first via conductors; and
second outer electrodes (5b – fig. 1; [0027]) provided on a surface of the capacitor body and electrically connected to the second via conductors;
wherein in a reference layout in which m×n (m and n are each a natural number of 4 or more) virtual lattice points are set in a view of the capacitor body seen in a lamination direction of the dielectric layers, the first inner electrodes, and the second inner electrodes, and in which via conductors including the first via conductors and the second via conductors are arranged at all the virtual lattice points, the first via conductors and the second via conductors are not arranged at least in portion of (m-2)×(n-2) of the virtual lattice points located inside outermost peripheral virtual lattice points (fig. 3; [0032]).
In regards to claim 2, Nakamura ‘887 discloses
The multilayer ceramic capacitor according to claim 1, wherein a difference between a number of the first via conductors and a number of the second via conductors is 1 or less (fig. 2-3).
In regards to claim 3, Nakamura ‘887 discloses
The multilayer ceramic capacitor according to claim 1, wherein the virtual lattice points at which the first via conductors and the second via conductors are not arranged are the virtual lattice points corresponding to the via conductors through each of which a current flows when a voltage is applied between the first outer electrodes and the second outer electrodes in the reference layout, among the virtual lattice points located inside the outermost peripheral virtual lattice points in the reference layout (fig. 3).
In regards to claim 4, Nakamura ‘887 discloses
The multilayer ceramic capacitor according to claim 1, wherein a plurality of the virtual lattice points at which the first via conductors and the second via conductors are arranged are in a symmetric layout (fig. 3).
In regards to claim 6, Nakamura ‘887 discloses
The multilayer ceramic capacitor according to claim 1, wherein the capacitor body has a rectangular or substantially rectangular parallelepiped shape (fig. 3).
In regards to claim 10, Nakamura ‘887 discloses
The multilayer ceramic capacitor according to claim 1, wherein each of the first via conductors and the second via conductors has a columnar shape (fig. 1).
In regards to claim 14, Nakamura ‘887 discloses
The multilayer ceramic capacitor according to claim 4, wherein the symmetric layout is line symmetric or point symmetric (fig. 3).
In regards to claim 15, Nakamura ‘887 discloses
The multilayer ceramic capacitor according to claim 1, wherein a number of the first via conductors and a number of the second via conductors is equal (fig. 2-3).
In regards to claim 16, Nakamura ‘887 discloses
The multilayer ceramic capacitor according to claim 1, wherein each of the plurality of dielectric layers includes BaTiO3, CaTiO3, SrTiO3, SrZrO3, or CaZrO3 ([0029]).
In regards to claim 18, Nakamura ‘887 discloses
The multilayer ceramic capacitor according to claim 1, wherein each of the first inner electrodes and the second inner electrodes includes Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au, or an alloy including Ni, Cu, Ag, Pd, Pt, Fe, Ti, Cr, Sn, or Au ([0030]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7-8 & 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Naito ‘395 or Nakamura ‘887 in view of Muramatsu et al. (US 2019/0027312).
In regards to claim 7,
Naito ‘395 or Nakamura ‘887 fails to disclose wherein the capacitor body has a lengthwise dimension of about 0.3 mm or more and about 3.0 mm or less, a widthwise dimension of about 0.3 mm or more and about 3.0 mm or less, and a dimension in the lamination direction of about 50 μm or more and about 200 μm or less.
Muramatsu ‘312 discloses wherein the capacitor body has a lengthwise dimension of about 0.3 mm or more and about 3.0 mm or less, a widthwise dimension of about 0.3 mm or more and about 3.0 mm or less, and a dimension in the lamination direction of about 50 μm or more and about 200 μm or less ([0227]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the capacitor of Naito ‘395 or Nakamura ‘887 to have dimensions as taught by Muramatsu ‘312 to obtain capacitor with a smaller size. Furthermore, a change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
In regards to claim 8,
Naito ‘395 or Nakamura ‘887 fails to disclose wherein a thickness of each of the first inner electrodes and the second inner electrodes is about 0.3 μm or more and about 1.0 μm or less.
Muramatsu ‘312 discloses wherein a thickness of each of the first inner electrodes and the second inner electrodes is about 0.3 μm or more and about 1.0 μm or less ([0079]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the internal electrodes of Naito ‘395 or Nakamura ‘887 to have a thickness as taught by Muramatsu ‘312 to obtain capacitor with a smaller size and good volume efficiency. Furthermore, a change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
In regards to claim 17,
Naito ‘395 or Nakamura ‘887 fails to disclose wherein each of the plurality of dielectric layers includes a Mn compound, a Fe compound, a Cr compound, a Co compound, or a Ni compound.
Muramatsu ‘312 discloses wherein each of the plurality of dielectric layers includes a Mn compound, a Fe compound, a Cr compound, a Co compound, or a Ni compound ([0064]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the dielectric layer of Naito ‘395 or Nakamura ‘887 using a material as taught by Muramatsu ‘312 to obtain capacitor with a desired capacitance. Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Naito ‘395.
In regards to claim 12,
Naito ‘395 disclose all the claimed limitations discussed above with respect to claim 12, except for wherein a distance between one of the first via conductors and one of the second via conductors is about 50 μm or more and about 500 μm or less. However, Naito ‘395 discloses that the distance between via conductors is a result effective variable, particularly for reducing ESL (C6:L65 to C7:L10).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Naito ‘395 such that a distance between one of the first via conductors and one of the second via conductors is about 50 μm or more and about 500 μm or less to obtain a capacitor with a reduced ESL, as taught by Naito ‘395. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura ‘887.
In regards to claim 13,
Nakamura ‘887 fails to explicitly disclose wherein m and n are each equal to 5. However, Nakamura ‘887 discloses the arrangement (i.e. number/layout of vias) is a design choice based on the desired use (e.g. matching terminals of semiconductor device) and thus it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form m and n of Nakamura ‘887 to be 5 to match other components with a circuit design.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Naito ‘395 or Nakamura ‘887 in view of Ritter et al. (US 2004/0257748).
In regards to claim 19,
Naito ‘395 or Nakamura ‘887 fails to disclose wherein each of the first inner electrodes and the second inner electrodes includes a same dielectric ceramic material as that included in the plurality of dielectric layers.
Ritter ‘748 discloses wherein each of the first inner electrodes and the second inner electrodes includes a same dielectric ceramic material as that included in the plurality of dielectric layers ([0163]).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the inner electrodes of Naito ‘395 or Nakamura ‘887 using a material as taught by Ritter ‘748 to control shrinkage of the internal electrodes during firing.
In regards to claim 20,
Naito ‘395 or Nakamura ‘887 as modified by Ritter ‘748 further discloses wherein each of the first inner electrodes and the second inner electrodes includes about 20 vol% of less of a same dielectric ceramic material as that included in the plurality of dielectric layers ([0163] of Ritter ‘748).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2021/0249193 – [0035] US 20180277305 – [0046]
US 2007/0064374 – fig. 6 DE102006056872A1 – fig. 1
US 2008/0239685 – fig. 6-7
Communication
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM.
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/David M Sinclair/Primary Examiner, Art Unit 2848