Detailed Action
This communication is in response to applicants claims filed 01/15/2026. Claims 1-6, 9-10, 11-16, 19-20 are pending. Claims 7-8, 17-18 are cancelled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 07/29/2024 and 01/10/2025 appear to be in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Response to Arguments
Applicant's arguments filed on 01/15/2026 have been fully considered but are considered moot in view of the following new ground of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 and 11-16 are rejected under 35 U.S.C. 103 as being unpatentable over HYDE (US 20140016426 A1), hereafter HYDE in view of VACQUERIE (US 20230283891 A1), hereafter VACQUERIE.
Regarding claim 1, HYDE teaches:
1. An apparatus for protecting a memory, the apparatus comprising: a monitoring unit configured to monitor pieces of status data of an integrated circuit (IC) chip (HYDE [0051] “Accordingly, the thermoelectric generator 420 is configured to begin erasing or overwriting data stored in memory 404 in response to a change in temperature across a portion of the computing device 400 (e.g., a sudden change in temperature, a cold attack, etc.).”, [0052] “Whereas the embodiment of FIG. 3 detects a temperature change (and possible attack) across the memory chip 302, the embodiment of FIG. 4 detects a temperature change (and possible attack) across the entire computing device 400. However, the thermoelectric generator 420 may use a location 422c located on the memory chip 402 and thereby use a temperature change across the memory chip 402.”); and a processor configured to analyze the status data monitored by the monitoring unit (HYDE [0070] “The memory 1004 may be communicably connected to the processor 1002 and includes computer code or instructions for executing one or more processes described herein.”) to detect a cold boot attack on the IC chip (HYDE [0051] “Accordingly, the thermoelectric generator 420 is configured to begin erasing or overwriting data stored in memory 404 in response to a change in temperature across a portion of the computing device 400 (e.g., a sudden change in temperature, a cold attack, etc.). “[0052] According to the embodiment shown, the thermoelectric generator 420 is configured to use a temperature difference between two portions (e.g., a first location 422a and a second location 422b) of the computing device 400. Whereas the embodiment of FIG. 3 detects a temperature change (and possible attack) across the memory chip 302, the embodiment of FIG. 4 detects a temperature change (and possible attack) across the entire computing device 400.) and protect a memory in the IC chip from the cold boot attack according to a detection result (HYDE [0003] One embodiment of the disclosure relates to a system for preventing data remanence in memory. The system includes a computing device, a memory chip coupled to the computing device and including memory, and a heater, the heater configured to prevent data remanence in a memory by providing heat to at least a portion of the memory.),
Further regarding claim 1, HYDE teaches the limitations previously demonstrated, however does not appear to explicitly teach the following limitations demonstrated by VACQUERIE:
wherein the processor is configured to overclock the IC chip to raise a temperature of the IC chip ([0083] “In some implementations, the integrated circuit 422 may be configured to access the temperature measurement and set the clock frequency for the clock signal during an early phase of a boot sequence for the integrated circuit 422.”, [0085] “In some implementations, the processing apparatus 420 is configured to, responsive to the temperature measurement being below the threshold, apply automatic voltage scaling to one or more power domains of the integrated circuit 422.” [0088] “In some implementations, an idle mode may be used after the boot sequence at low temperature to heat up a device (e.g., the camera or the imaging device) that includes the integrated circuit to achieve a temperature (e.g., a battery temperature) needed to supply current sufficient for a selected use case for the device.”)
Since both HYDE and VACQUERIE are from the same field of endeavor as both are directed to secure boot processes, which is within the same field of endeavor as the claimed invention, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify and combine the teachings of HYDE and VACQUERIE by incorporating the teachings of VACQUERIE into HYDE for increasing device component temperatures as claimed. The motivation to combine is to improve component heating efficiency by circumventing the use of additional components, such as a heater. (HYDE [AB]; VACQUERIE [AB]).
Regarding claim 2, HYDE-VACQUERIE teaches:
2. The apparatus as claimed in claim 1, wherein the monitoring unit monitors at least one of power consumption, current consumption, voltage changes, and system performance changes of the IC chip (HYDE [0036] “The memory and sensitive information may be configured to be erased or lost when a trigger condition is met. The condition may be generally based on a power status change or threat on the memory chip.”, [0062] “In one embodiment, the trigger condition is a threat detection. The threat detection may occur in response to a power signal. For example, the power signal may indicate when a power supply to the computing device is cut off or otherwise changed.”).
Regarding claim 3, HYDE-VACQUERIE teaches:
3. The apparatus as claimed in claim 1, wherein the processor compares each pattern of the status data with a setting pattern set for each pattern to extract similarity and detects the cold boot attack according to the similarity (HYDE [0055] “The thermostat 522 of FIG. 5 is a device configured to regulate the temperature of the memory 504 such that the temperature of the memory 504 is maintained near a desired point (e.g., set point, specified temperature, etc.). When the thermostat 522 measures a current temperature that is not within a threshold, the thermostat 522 may permit heat from the heater 506 to pass to the memory 504.”, [0077] “In another embodiment, a threat detection may be provided to the activation module 1016 (e.g., via the activation circuit 926 of FIG. 9) and the activation module 1016 may determine whether or not the threat is legitimate, for example, by comparing the detected threat to other data, signals, inputs or thresholds.”).
Regarding claim 4, HYDE-VACQUERIE teaches:
4. The apparatus as claimed in claim 3, wherein, if the similarity of at least one of the pieces of status data is greater than or equal to a preset reference value, the processor determines that the cold boot attack has been made (HYDE [0055] “The thermostat 522 of FIG. 5 is a device configured to regulate the temperature of the memory 504 such that the temperature of the memory 504 is maintained near a desired point (e.g., set point, specified temperature, etc.). When the thermostat 522 measures a current temperature that is not within a threshold, the thermostat 522 may permit heat from the heater 506 to pass to the memory 504.”, [0077] “In another embodiment, a threat detection may be provided to the activation module 1016 (e.g., via the activation circuit 926 of FIG. 9) and the activation module 1016 may determine whether or not the threat is legitimate, for example, by comparing the detected threat to other data, signals, inputs or thresholds.”).
Regarding claim 5, HYDE-VACQUERIE teaches:
5. The apparatus as claimed in claim 1, wherein the processor compares the status data with a critical range preset for each piece of status data to detect the cold boot attack according to a comparison result (HYDE [0065] The threat detection may occur in response to a stress signal or strain signal. For example, a physical attack on a memory chip 902 or computing device 900 may be detected via a stress or strain gauge. If pressure or force is exerted on the memory chip 902 or computing device 900 beyond a normal or expected level, a stress signal or strain signal may be used to indicate a current threat.).
Regarding claim 6, HYDE-VACQUERIE teaches:
6. The apparatus as claimed in claim 5, wherein, if at least one of the pieces of status data is out of the critical range, the processor determines that the cold boot attack has been made (HYDE [0051] “Accordingly, the thermoelectric generator 420 is configured to begin erasing or overwriting data stored in memory 404 in response to a change in temperature across a portion of the computing device 400 (e.g., a sudden change in temperature, a cold attack, etc.).”).
Regarding claims 11-16, claims 11-16 recite similar limitations as claims 1-6, but for recitation in the form of a method. HYDE-VACQUERIE teaches a method (HYDE [0004] “Another embodiment relates to a method for preventing data remanence in a memory in a computing device,”), thus claims 11-16 are rejected under similar rationale and reasoning applied to the rejections of claims 1-6.
Claim(s) (9-10) & (19-20) are rejected under 35 U.S.C. 103 as being unpatentable over HYDE-VACQUERIE in further view of BOEHM (US 20230205874 A1), hereafter BOEHM.
Regarding claim 9, HYDE-VACQUERIE teaches the limitations of claim 1, however does not appear to explicitly teach the following limitations demonstrated by BOEHM:
9. The apparatus as claimed in claim 1, wherein, if the cold boot attack is detected, the processor protects data of the memory in the IC chip (Boehm [0059] “The detection circuit 310 may detect whether a change to an input 315 (e.g., the voltage input, the clock speed) has occurred and—if a change is detected—may signal the DRAM 305 to perform one or more protective actions. In some examples, the protective actions may involve clearing contents of the memory (e.g., in the array of memory cells 345)”).
Since both HYDE-VACQUERIE and BOEHM are from the same field of endeavor as both are directed to detection or mitigation of physical attacks on cybersecure systems, which is within the same field of endeavor as the claimed invention, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify and combine the teachings of HYDE and BOEHM by incorporating the teachings of BOEHM into HYDE for detection or mitigation of physical attacks on cybersecure systems as claimed. The motivation to combine is to improve detection or mitigation of physical attacks on cybersecure systems (HYDE [AB]; VACQUERIE [AB]; BOEHM [AB]).
Regarding claim 10, HYDE-VACQUERIE in view of BOEHM teaches:
10. The apparatus as claimed in claim 9, wherein the processor replaces the data of the memory in the IC chip with null data (Boehm [0059] “In some examples, the protective actions may involve clearing contents of the memory (e.g., in the array of memory cells 345), locking specific access operations, or similarly disabling one or more features of the DRAM 305. For example, the DRAM 305 may erase one or more keys (e.g., secret keys, encryption keys), erase sensitive information, or both from memory if a potential attack is detected”).
Regarding claims 19-20, claims 19-20 recite similar limitations as claims 9-10, but for recitation in the form of a method. HYDE-VACQUERIE in view of BOEHM further teaches a method (HYDE [0004] “Another embodiment relates to a method for preventing data remanence in a memory in a computing device,”), thus claims 19-20 are rejected under similar rationale and reasoning applied to the rejections of claims 9-10.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kamryn Gillespie whose telephone number is 703-756-5498. The examiner can normally be reached on Monday through Thursday from 9am to 6pm.
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/K.J.G./Examiner, Art Unit 2408
/LINGLAN EDWARDS/Supervisory Patent Examiner, Art Unit 2408
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