CTFR 18/786,741 CTFR 83258 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ghai et al. (U.S. Publication 2013/0262777), hereinafter Ghai in view of Jones et al (U.S. Publication 2006/0179439), hereinafter Jones further in view of Tran (U.S. Pub. 2024/0020120), hereinafter Tran . Referring to claim 1, Ghai teaches, as claimed, a method comprising: receiving an instruction (instruction, see Paragraph 26) by a processor (processor, see Paragraph 26); and based on the instruction, causing a memory access (memory access, see Paragraph 26) circuit to: generate the set of cache memory (cache memory, see Paragraph 27) operations directed to a first cache circuit (L1 cache, see Paragraph 27); determine whether to delay providing of the set of cache memory operations based on whether an access of a second cache (see Fig. 2B, L2 Cache 230) circuit is pending; and provide the set of cache memory (cache management instruction, see Paragraph 26) operations to the first cache circuit. Ghai does not disclose expressly determine whether to delay providing of the set of cache memory operations based on whether an access of a second cache circuit is pending. Jones does disclose determine whether to delay (stall, see Paragraph 40) providing of the set of cache memory operations based on whether an access of a second cache circuit is pending (cache management instruction must stall waiting for the first to finish, see Paragraph 40). At the time of the invention it would have been obvious to a person of ordinary skill in the art to incorporate Jones in to Ghai. The suggestion/motivation for doing so would have been to prevent or clear hazards so that second operation/instruction would properly execute (see Jones, Paragraph 40). Still, Ghai/Joes does not expressly disclose, wherein the instruction specifies a base address, a size, and a type of a set of cache memory operations. Tran does disclose wherein the instruction specifies a base address (base address, see Paragraph 43), a size (cache line size, see Paragraph 43), and a type (memory types, see Paragraph 43) of a set of cache memory (cache, see Paragraph 43) operations. At the time of the invention it would have been obvious to a person of ordinary skill in the art to incorporate Tran into (inventor/author). The suggestion/motivation for doing so would have been to (motivation). As to claim 19 the modification teaches the method of claim 18, wherein the first cache circuit is a level-two (L2) cache (L2 cache, see Paragraph 27) circuit and the second cache circuit is a level-one (L1) cache circuit. As to claim 20 the modification teaches the method of claim 18, wherein the instruction specifies a level of a cache memory hierarchy (hierarchy, see Paragraph 26) associated with the set of cache memory operations . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 1-5, 7-14, and 16-17 are allowed. Response to Arguments Applicant's arguments filed 7/9/2024 have been fully considered but they are moot in view of new grounds of rejections. Applicant argues, independent claim 18 is presently amended to incorporate portions of the subject matter of dependent claim 20 that correspond to subject matter similar to dependent claim 6. Examiner disagrees with applicant. The limitations in claims 6 by themselves was not the reason examiner construed the claims allowable. Examiner maintains, cache having a base address, a size, and being of any particular type implicitly true of any give cache. . Conclusion 07-39 AIA THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hyun Nam whose telephone number is (571) 270-1725 and fax number is (571) 270-2725. The examiner can normally be reached on Monday through Friday 8:30 AM to 5:00 PM EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HYUN NAM/Primary Examiner, Art Unit 2183 Application/Control Number: 18/786,741 Page 2 Art Unit: 2183 Application/Control Number: 18/786,741 Page 3 Art Unit: 2183 Application/Control Number: 18/786,741 Page 4 Art Unit: 2183 Application/Control Number: 18/786,741 Page 5 Art Unit: 2183 Application/Control Number: 18/786,741 Page 6 Art Unit: 2183
Prosecution Insights