Prosecution Insights
Last updated: April 19, 2026
Application No. 18/786,809

LOCKING CURRENT TRANSFORMER

Non-Final OA §103
Filed
Jul 29, 2024
Examiner
HAWKINS, DOMINIC E
Art Unit
2858
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Schneider Electric
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
99%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allow Rate
625 granted / 720 resolved
+18.8% vs TC avg
Moderate +12% lift
Without
With
+12.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
28 currently pending
Career history
748
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
59.2%
+19.2% vs TC avg
§102
25.4%
-14.6% vs TC avg
§112
10.6%
-29.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 720 resolved cases

Office Action

§103
Detailed Action The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 21-40 of U.S. Application 18/786,809 filed on September 06, 2024 are presented for examination. Information Disclosure Statement The information disclosure statement (IDS) submitted on 08/09/2024 and 08/09/2024 has been considered by the examiner. Priority Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claims 21, 22, 24, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Hannam et al (US Pat No 10677621) in view of Spitaels et al (USPGPub 20110136353). PNG media_image1.png 452 764 media_image1.png Greyscale Prior Art: Hannam Regarding claim 21, Hannam discloses an assembly (100) comprising: a cord (114); a plug (J1) operatively connected to the cord (shown in fig 3), wherein the plug is adapted to be plugged into a power monitor (plug into meter 108 as shown in fig 3); a first connection (along 117) operatively connected to the cord (shown in fig 3), configured to be connected to a first current transformer (104. Col 8 lines 1-15 and claim 3 discloses the transformer contains a current transformer); and a memory chip (106). Hannam does not fully disclose a memory chip situated within the plug. However, Spitaels discloses a memory chip (69) situated within the plug (20. Par 61 discloses plug-in module contains memory). It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to combine Hannam in view of Spitaels in order to determine information concerning to the plug-in module based on user needs (Spitaels par 61). Regarding claim 22, Hannam discloses wherein the memory chip is adapted to store a first scale factor of the first current transformer (col 2 lines 50-62 discloses storing information such as correction data correction). Regarding claim 24, Hannam discloses wherein the cable is a multi-wire cable including: a first wire (110) configured to connect between the first current transformer and the plug; and a second wire (112) configured to connect between the first current transformer and the plug (shown in fig 2 as having the cables in between the plug and transformer). Regarding claim 25, Hannam discloses wherein the memory chip is connected to at least one of the first and second wires (shown in figs 2-9 as the memory is connected to the wires through 134 and 136). Allowable Subject Matter Claims 23 and 26-33 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 23, the prior art of record taken alone or in combination fail to teach or suggest an assembly comprising: the first current transformer, wherein the first current transformer includes a first housing having a first handle portion and a first distal portion; a second housing having a second handle portion, a second distal portion, and a connector connected to the first connection; a first core, wherein the first core is mounted within the first distal portion; and a second core, wherein the second core is mounted within the second distal portion in combination with the other limitation of the claim. Regarding claim 26, the prior art of record taken alone or in combination fail to teach or suggest an assembly comprising: a second connection connected to the cord, configured to be connected to a second current transformer in combination with the other limitation of the claim. Claims 27-33 are also objected to as they depend on claim 26. Reasons for Allowance Claims 34-40 are allowed. The following is an examiner’s statement of reasons for allowance: Regarding claim 34, the prior art of record taken alone or in combination fail to teach or suggest a power monitor comprising: a power and I/F circuit operatively connected to the SoC, wherein the power and I/F circuit is configured to connect to an interface to control a memory chip of a current transformer assembly; wherein the SoC, the power and I/F circuit, and A/D are configured to: read a first scale factor for the first current transformer from the memory chip, receive a first sensor value from the first current transformer, compute a second sensor value from the first sensor value using the first scale factor, and use the second sensor value to determine information about energy consumption in a building in combination with the other limitations of the claim. Claims 35-40 are also objected to as they depend on claim 34. Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Mitchell et al (US Pat No. 10432258): discloses a connector with memory inside. McGinley et al (USPGPub 20070164704): discloses memory inside of the plug. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOMINIC E HAWKINS whose telephone number is (571)272-2647. The examiner can normally be reached Monday-Friday 7:30am-5:00pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached at (571) 272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DOMINIC E HAWKINS/Primary Examiner, Art Unit 2858
Read full office action

Prosecution Timeline

Jul 29, 2024
Application Filed
Sep 06, 2024
Response after Non-Final Action
Mar 19, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
99%
With Interview (+12.1%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 720 resolved cases by this examiner. Grant probability derived from career allow rate.

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