DETAILED ACTION
The current Office Action is in response to the papers submitted 03/05/2026. Claims 1 - 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 1 - 20 objected to because of the following informalities:
Claim 1 is worded oddly to the examiner in multiple locations. Line 7 contains the phrase “the at least one at least one processing device”. It appears the phrase should be “the at least one processing device”. Line 14 contains the phrase “be the at least one processing device”. It appears the phrase should be “by the at least one processing device”.
Claims 11 and 20 are objected for containing similar language objected in claim 1.
All remaining claims are objected to for being dependent on an objected base claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 - 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the at least one processing device implemented by the memory sub-system" in lines 5 - 6. The claim previously discloses a set of memory components of a memory sub-system and at least one processing device coupled to the set of memory components. There is no mention of any processing device being implemented by the memory sub-system. It is unclear if the processing device implemented by the memory sub-system is meant to refer to the processing device operatively coupled to the set of memory components in line 3 of the claim or another processing device. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 is rejected for containing the phrase "the at least one processing device implemented by the memory sub-system" which is rejected in claim 1 above.
Claim 20 is rejected for containing similar language rejected in claim 1.
All remaining claims are rejected for being dependent on a rejected base claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4 – 5, 10 – 11, and 18 - 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Devendrappa et al. (Pub. No.: US 2017/0115890) referred to as Devendrappa.
Regarding claims 1, Devendrappa teaches a set of memory components [202, Fig 2; Paragraphs 0036, 0042, 0046, and 0048; The blocks of memory are memory components] of a memory sub-system [202, 204, and 206, Fig 2]; and
at least one processing device [206 and 314, Figs 3 and 5] operatively coupled to the set of memory components [202, Fig 2], the at least one processing device [206 and 314, Figs 3 and 5] being programmed to perform operations [Figs 4 – 6; The figures show processes that are performed] comprising:
receiving, by the at least one processing device [206 and 314, Figs 3 and 5] implemented by the memory sub-system [202, 204, and 206, Fig 2], from a host [100, Fig 1; 208, Figs 2 – 3; Paragraphs 0034, 0038, 0041, and 0049; The computing device is a host that sends commands to the memory through the host interface], data identifying a set of storage locations associated with invalidated data [502, Fig 5; The delete command identifies locations in logical blocks that will be invalidated and is associated with other data in the logical block that was previously invalidated] stored in the set of memory components [202, Fig 2], the at least one at least one processing device [206 and 314, Figs 3 and 5] coupled to the host that is external [100, Fig 1; 208, Figs 2 – 3; Paragraphs 0034, 0038, 0041, and 0049; The host is external to the memory sub-system 202, 204, and 206 and interacts with the memory sub-system using the host interface 208] to the memory sub-system [202, 204, and 206, Fig 2];
based on the at least one processing device [206 and 314, Figs 3 and 5] receiving the data from the host [100, Fig 1; 208, Figs 2 – 3; 502, Fig 5; Paragraphs 0034, 0038, 0041, and 0049] and prior to receiving a trim command [510, Fig 5] from the host [100, Fig 1; 208, Figs 2 – 3; Paragraphs 0034, 0038, 0041, and 0049; The host sends the trim command to the processing device through host interface 208 after the data], performing staging activity for the invalidated data stored in the set of storage locations [206, 306, and 314, Fig 3; 504, Fig 5; Paragraph 0048; The setting of a flag to indicate data is invalidated is a staging activity to get ready for a trim operation is performed by both the controller 206 and application 314. The map of logical block identifiers and locations within memory blocks is located in the mapping 306 in controller 206 showing the controller is involved in the staging];
receiving, by the at least on processing device [206 and 314, Figs 3 and 5] from the host [100, Fig 1; 208, Figs 2 – 3; Paragraphs 0034, 0038, 0041, and 0049; The host sends the trim command to the processing device through host interface 208], a trim command for one or more storage locations in the set of storage locations [510, Fig 5]; and
performing, be the at least one processing device [206 and 314, Figs 3 and 5], trim operations for the one or more storage locations for which staging activity has already been performed [514, Fig 5; The trim command is executed on the storage locations that the flag is set indicating the data is invalid].
Claims 11 and 20 are method and medium claims corresponding to claim 1 and are rejected using the same prior art and similar reasoning. Devendrappa teaches the method [Fig 5] and storage medium [Paragraphs 0019 – 0020].
Regarding claim 4, Devendrappa discloses marking the one or more storage locations as invalid in response to performing the trim operations [514, Fig 5; Erasing blocks in SSD sets the data to a certain value that is considered invalid that can be overwritten with new data when needed].
Regarding claim 5, Devendrappa teaches the staging activity [504, Fig 5; Paragraph 0048] is performed during a time between receiving the data identifying the set of storage locations [502, Fig 5] and receiving the trim command [510, Fig 5; Step 504 is performed in between steps 502 and 510].
Regarding claim 10, Devendrappa teaches the invalidated data stored in the set of storage locations is not deleted by the staging activity [504, Fig 5] until the trim command is subsequently received from the host [514, Fig 5; The deleting in 514 occurs after step 504].
Regarding claim 18, Devendrappa teaches the data identifying the set of storage locations comprises a set of logical block addresses (LBAs) [Paragraphs 0036 – 0037, 0041, 0043, 0047 – 0051; The logical block identifiers are logical block addresses].
Regarding claim 19, Devendrappa teaches the host [100, Fig 1; Paragraphs
0034, 0038, 0041, and 0049] performs operations comprising:
identifying, by the host [100, Fig 1; Paragraphs 0034, 0038, 0041, and 0049], a
file to be deleted [502, Fig 5; Paragraphs 0039 - 0040; The application is run on the host and the delete command is a result of a determination of what data can be deleted];
determining, by the host [100, Fig 1; Paragraphs 0034, 0038, 0041, and 0049], the set of LBAs associated with the file [502, Fig 5; The delete command include logical block identifiers, which are LBAs, of the data that is to be deleted allowing the data to be invalidated in step 504];
tagging the set of LBAs associated with the file as invalid [502, Fig 5; The logical block identifiers in the delete command have been tagged as being associated with data that is to be deleted and thus put in the delete command];
transmitting a communication to the at least one processing device [206, Figs 2 - 3] associated with the set of memory components [202, Fig 2; Paragraphs 0036, 0042, 0046, and 0048] identifying the set of LBAs tagged as invalid [502, Fig 5; The delete command is a communication to the processing device identifying the LBAs that are tagged as invalid since they are to be deleted. Step 502 is performed before step 508 is performed] prior to transmitting the trim command [100, Fig 1; 208, Figs 2 – 3; Paragraphs 0034, 0038, 0041, and 0049; The host sends the trim command to the processing device through host interface 208 after the data].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Devendrappa et al. (Pub. No.: US 2017/0115890) referred to as Devendrappa as applied to claim 1 above, and further in view of Chris Sabol et al. (Hyperscale Innovation: Flexible Data Placement mode (FDP) referred to as Sabol.
Regarding claim 2, Devendrappa teaches the memory sub-system [202, 204, and 206, Fig 2].
However, Devendrappa may not specifically disclose the limitation of memory including Flexible Data Placement (FDP).
Sabol discloses memory including Flexible Data Placement (FDP) [Slides 6 – 9].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Sabol in Devendrappa, because it reduces write amplification[Slide 9].
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Devendrappa et al. (Pub. No.: US 2017/0115890) referred to as Devendrappa in view of Chris Sabol et al. (Hyperscale Innovation: Flexible Data Placement mode (FDP) referred to as Sabol as applied to claim 2 above, and further in view of Gorobets (Pub. No.: US 2008/0082596) referred to Gorobets.
Regarding claim 3, Devendrappa teaches memory components [202, Fig 2; Paragraphs 0036, 0042, 0046, and 0048; The blocks of memory are memory components] and at least one processing device [206 and 314, Figs 3 and 5] being configured to perform operations [Figs 4 – 6; The figures show processes that are performed].
However, Devendrappa in view of Sabol may not specifically disclose the limitations of grouping the set of memory components into a plurality of reclaim groups (RGs), each RG of the plurality of RGs comprising a subset of reclaim units (RUs).
Gorobets discloses grouping the set of memory components into a plurality of reclaim groups (RGs), each RG of the plurality of RGs comprising a subset of reclaim units (RUs) [Figs 2 – 3; Paragraphs 0027 – 0028; The blocks of memory are grouped into reclaim groups called metablocks where each metablock includes a plurality of reclaim units called pages].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Gorobets in Devendrappa in view of Sabol, because it improves parallelism which improves access performance of the memory by allowing multiple locations to be accessed in parallel [Paragraphs 0027 – 0028].
Claim(s) 6 – 7 and 16 - 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Devendrappa et al. (Pub. No.: US 2017/0115890) referred to as Devendrappa as applied to claims 1 and 11 above, and further in view of Gorobets (Pub. No.: US 2008/0082596) referred to Gorobets.
Regarding claims 6 and 16, Devendrappa teaches the one or more storage locations of the trim command comprise a first portion of a first memory block [202, Fig 2; Paragraphs 0036, 0042, 0046, and 0048; A memory block comprises pages].
However, Devendrappa may not specifically disclose the limitations of the operations comprising performing garbage collection by copying a second portion of the first memory block to a second memory block without copying the first portion to the second memory block.
Gorobets teaches the operations comprising performing garbage collection by copying a second portion of the first memory block to a second memory block without copying the first portion to the second memory block [Figs 2 – 3 and 9A – 9B; Garbage collection is performed by copying valid data in a first valid area of a metablock to another metablock without copying invalid data from a first invalid portion].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Gorobets in Devendrappa because garbage collection increases free space in storage by compacting valid data which also decreased fragmentation.
Regarding claims 7 and 17, Devendrappa teaches the one or more storage locations of the trim command [514, Fig 5] comprise a first portion of a first reclaim unit of a subset of reclaim units of a reclaim group [202, Fig 2; Paragraphs 0036, 0042, 0046, and 0048; SSD memory is comprised of blocks which are comprised of pages. Each memory device is a reclaim group. The first portion is a page of a block, the first reclaim unit is a block, and the subset of reclaim units is a grouping of blocks].
However, Devendrappa may not specifically disclose the limitations of the operations comprising performing garbage collection by copying a second portion of the first reclaim unit to a second reclaim unit of the reclaim group without copying the first portion of the first reclaim unit to the second reclaim unit [Figs 2 – 3 and 9A – 9B; Garbage collection is performed by copying valid data from a first metablock to a second metablock without copying invalid data from the first metablock to the second metablock. The data in the blocks are stored in reclaim units referred to as pages].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Gorobets in Devendrappa because garbage collection increases free space in storage by compacting valid data which also decreased fragmentation.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Devendrappa et al. (Pub. No.: US 2017/0115890) referred to as Devendrappa as applied to claims 1 above, and further in view of Porzio et al. (Pub. No.: US 2024/0036977) referred to as Porzio.
Regarding claim 8, Devendrappa teaches the data identifying the set of storage locations comprises a set of logical block addresses (LBAs) [Paragraphs 0036 – 0037, 0041, 0043, 0047 – 0051; The logical block identifiers are logical block addresses].
However, Devendrappa may not specifically disclose the limitation(s) of the operations comprise determining a time lag between receiving the data identifying the set of storage location and receiving the trim command and comparing the time lag to a threshold.
Porzio discloses the operations comprise determining a time lag between receiving the data identifying the set of storage location and receiving the trim command and comparing the time lag to a threshold [Paragraphs 0065, 0076, and 0093; The time between two commands being received is compared to a timing threshold].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Porzio in Devendrappa, because the time delay between commands can be used as an indication of future commands allowing the system to make predictions of what will occur in the future [Paragraph 0065].
Claim(s) 12 - 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Devendrappa et al. (Pub. No.: US 2017/0115890) referred to as Devendrappa as applied to claim 11 above, and further in view of Chris Sabol et al. (Hyperscale Innovation: Flexible Data Placement mode (FDP) referred to as Sabol in view of Gorobets (Pub. No.: US 2008/0082596) referred to Gorobets.
Regarding claim 12, Devendrappa teaches the memory sub-system [202, 204, and 206, Fig 2].
However, Devendrappa may not specifically disclose the limitation of memory including Flexible Data Placement (FDP) and wherein the staging activity comprises copying valid data from a block containing the invalidated data to a different block in the set of memory components.
Sabol discloses memory including Flexible Data Placement (FDP) [Slides 6 – 9].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Sabol in Devendrappa, because it reduces write amplification [Slide 9].
However, Devendrappa in view of Sabol may not specifically disclose the limitation(s) of wherein the staging activity comprises copying valid data from a block containing the invalidated data to a different block in the set of memory components.
Gorobets discloses the staging activity comprises copying valid data from a block containing the invalidated data to a different block in the set of memory components [Figs 2 – 3 and 9A – 9B; Garbage collection is performed which includes copying valid data from a block containing invalid data to another block of memory].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Gorobets in Devendrappa in view of Sabol, because it increases free space in storage by compacting valid data which also decreased fragmentation without having to wait for a block to be completely full of invalid data.
Regarding claim 13, Devendrappa teaches memory components [202, Fig 2; Paragraphs 0036, 0042, 0046, and 0048; The blocks of memory are memory components] and at least one processing device [206 and 314, Figs 3 and 5] being configured to perform operations [Figs 4 – 6; The figures show processes that are performed].
Gorobets discloses grouping the set of memory components into a plurality of reclaim groups (RGs), each RG of the plurality of RGs comprising a subset of reclaim units (RUs) [Figs 2 – 3; Paragraphs 0027 – 0028; The blocks of memory are grouped into reclaim groups called metablocks where each metablock includes a plurality of reclaim units called pages].
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Devendrappa et al. (Pub. No.: US 2017/0115890) referred to as Devendrappa as applied to claim 11 above, and further in view of Gorobets (Pub. No.: US 2008/0082596) referred to Gorobets.
Regarding claim 14, Devendrappa teaches the memory sub-system [202, 204, and 206, Fig 2] and performing staging activity for the invalidated data stored in the set of storage locations [504, Fig 5; Paragraph 0048; The setting of a flag to indicate data is invalidated is a staging activity to get ready for a trim operation].
However, Devendrappa may not specifically disclose the limitation(s) of the staging activity comprises relocating valid data stored in the set of storage locations to one or more different storage locations in the set of memory locations.
[Figs 2 – 3 and 9A – 9B; Garbage collection is performed which includes copying valid data from a block containing invalid data to another block of memory].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Gorobets in Devendrappa, because it increases free space in storage by compacting valid data which also decreased fragmentation without having to wait for a block to be completely full of invalid data.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Devendrappa et al. (Pub. No.: US 2017/0115890) referred to as Devendrappa as applied to claim 11 above, and further in view of Horspool et al. (Pub. No.: US 2021/0271757) referred to as Horspool.
Regarding claim 15, Devendrappa teaches the staging activity [504, Fig 5; Paragraph 0048] is performed during a time between receiving the data identifying the set of storage locations [502, Fig 5] and receiving the trim command [510, Fig 5; Step 504 is performed in between steps 502 and 510].
However, Devendrappa may not specifically disclose the limitation(s) of determining that a block associated with the set of storage locations impending trim operations and based on determining that the block associated with the set of storage locations has impending trim operations, deferring selection of the block as a garbage collection candidate.
Horspool discloses determining that a block associated with the set of storage locations impending trim operations and based on determining that the block associated with the set of storage locations has impending trim operations, deferring selection of the block as a garbage collection candidate [230 and 240, Fig 2; Paragraphs 0014, 0019, 0039 – 0040; Due to an impeding trim command in a ransomware attack garbage collection is halted].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Horspool in Devendrappa, because it aids in preventing the loss of data [Paragraph 0040]
Allowable Subject Matter
Claim 9 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 03/05/2026 have been fully considered but they are not persuasive.
The applicant argues on pages 7 – 8 that the claims are allowable since Devendrappa and the additional prior art fails to teach the processing device performing staging activity for the invalidated data based on the at least one processing device receiving the data from host and prior art receiving a trim command from the host. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The rejections above have been updated due to the amendments to the claims. Paragraph 0048 in Devendrappa discloses how the application 314 and controller 206 work together to perform the staging before the trim command is sent from the host. Even if the application is on the host, the staging is performed in part by the controller 206 and not application 314 alone.
The staging involves marking in a map that data at a location is invalid. The mapping where the marking is performed includes mapping between a logical block identifier and locations in memory blocks. The locations in memory blocks are physical block identifier or physical addresses. The only map between controller 206 and application 314 that contains physical address is the mapping 306. Mapping 318 in application 314 is specifically disclosed as not containing physical address in paragraph 0041. The logical block may correspond to a physical memory block. However, the mapping 218 does not maintain the mapping of the logical memory block to a corresponding physical memory block. Paragraphs 0041 and 0048 together show that the controller receives information from the host indicating which locations are to be invalidated and the mapping 306 in the controller is updated to indicate data at a logical and physical location is invalided.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER D BIRKHIMER whose telephone number is (571)270-1178. The examiner can normally be reached 8-5 Hoteling.
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/Christopher D Birkhimer/Primary Examiner, Art Unit 2138
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