Attorney’s Docket Number: 8021S-2090 (SS-72588-US)
Filing Date: 07/29/2024
Claimed Foreign Priority Date: 08/08/2023 (KR10-2023-0103697)
Applicants: Kim et al.
Examiner: William H. Amran
DETAILED ACTION
This office action responds to the application filed on 07/29/2024
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The application serial no. 18/786,824 filed on 07/29/2024 has been entered. Pending in this Office Action are claims 1-20.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KANG et al. (US 20210398923 A1).
Regarding Claim 1, KANG (see, e.g., Figs. 1 and 18) shows all aspects of the instant invention including a semiconductor package (e.g., semiconductor package 100A) comprising:
-a first substrate (e.g., redistribution structure 110)
-a first semiconductor device (e.g., semiconductor chip 130) disposed on the first substrate (see, e.g., Fig. 1)
-a dummy substrate (e.g., core structure 140) disposed on the first substrate, spaced apart from a side surface of the first semiconductor device (see, e.g., Fig. 1), and surrounding the first semiconductor device (see, e.g., Fig. 18)
-a core module (e.g., antenna substrate 120) disposed in the dummy substrate (see, e.g., Fig. 18)
-an encapsulant surrounding the first semiconductor device (e.g., encapsulant 150) and in contact with the dummy substrate (see, e.g., Fig. 18)
-wherein the core module includes a core wiring (e.g., antenna member 122, and/or through-via 123, and/or director member 125) and a module substrate (e.g., dielectric layer 121) (see, e.g., Fig. 1)
-the core module is disposed on the first substrate, and a side surface of the core module is surrounded by and spaced apart from an inner side surface of the dummy substrate (see, e.g., Fig. 18)
-the encapsulant is disposed between the dummy substrate and the side surface of the core module (see, e.g., Fig. 1)
Regarding Claim 2, KANG (see, e.g., Figs. 1 and 18) shows a plurality of core modules (e.g., antenna substrates 120-1, 120-2, 120-3, and 120-4) (see, e.g., Fig. 18), including the core module, are disposed in the dummy substrate (e.g., 140) and on the first substrate (e.g., 110) (see, e.g., Fig. 1).
Regarding Claim 3, KANG (see, e.g., Fig. 18) shows all side surfaces of each of the plurality of core modules (e.g., 120-1, 120-2, 120-3, and 120-4) are spaced apart from all inner surfaces of the dummy substrate (e.g., 140) that face the side surfaces of each of the plurality of core modules.
Regarding Claim 4, KANG (see, e.g., Fig. 1) shows an uppermost surface of the module substrate (e.g., 121) of the plurality of core modules is coplanar with an upper surface of the dummy substrate (e.g., 140).
Regarding Claim 5, KANG (see, e.g., Figs. 17 and 18, and Par. [0076]) shows
-the core wiring of a first core module (see, e.g., Fig. 17) of the plurality of core modules (see, e.g., Fig. 18 and Par. [0076]) includes a first stack of core wirings (e.g. antenna substrates)
-the core wiring of a second core module (see, e.g., Fig. 18) of the plurality of core modules (e.g., 120-1, 120-2, 120-3, and 120-4) includes a second stack of core wirings
-the first stack of core wirings (see, e.g., Fig. 17) includes a first number of core wirings different from a second number of core wirings of the second stack of core wirings (see, e.g., Fig. 18)
Regarding Claim 6, KANG (see, e.g., Figs. 1 and 18) shows the plurality of core modules (e.g., 120-1, 120-2, 120-3, and 120-4) (see, e.g., Fig. 18) include the core wiring (e.g. antenna substrates) arranged in a plurality of rows and a plurality of columns in a plan view parallel to the first substrate (e.g., 110) (see, e.g., Fig. 1).
Regarding Claim 7, KANG (see, e.g., Fig. 18 and Par. [0076]) shows at least some core modules of the plurality of core modules (see, e.g., Fig. 18 and Par. [0076]) differ from the remaining core modules of the plurality of core modules (see, e.g., Fig. 18 and Par. [0076]) in at least one of a number of the rows or the columns of the core wiring.
Regarding Claim 8, KANG (see, e.g., Figs. 17 and 18, and Par. [0076]) shows the plurality of core modules include a first core module (see, e.g., Fig. 17) and a second core module (see, e.g., Fig. 18 and Par. [0076])
-the first core module includes the core wirings (e.g. antenna substrates) arranged in N rows and N columns, where N is a natural number of 2 or more
-the second core module includes the core wirings (e.g. antenna substrates) arranged in N rows and 2N columns
Regarding Claim 9, KANG (see, e.g., Figs. 17 and 18, and Par. [0076]) shows the plurality of core modules include a first core module (see, e.g., Fig. 17) and a second core module (see, e.g., Fig. 18 and Par. [0076])
-the first core module includes the core wiring (e.g. antenna substrates) arranged in N rows, where N is a natural number of 2 or more, and M columns, where M is a natural number of 2 or more
-the second core module includes the core wiring (e.g. antenna substrates) arranged in P rows, where P is a natural number of 2 or more, and Q columns, where Q is a natural number greater than M
Regarding Claim 10, KANG (see, e.g., Fig. 1) shows the core wiring includes a core pattern (e.g., 122) and a core via (e.g., 123).
Regarding Claim 11, KANG (see, e.g., Fig. 18) shows the plurality of core modules all have a same number of stacks of the core wiring (e.g. antenna substrates).
Regarding Claim 12, KANG (see, e.g., Fig. 5) shows a second substrate (e.g., redistribution structure 160) disposed on the encapsulant (e.g., 150) and electrically connected to the core module (e.g., 120).
Regarding Claim 13, KANG (see, e.g., Fig. 1) shows the first substrate (e.g., 110) and the second substrate (e.g., 160) are each a redistribution structure.
Regarding Claim 14, KANG (see, e.g., Fig. 18) shows the plurality of core modules (e.g., 120-1, 120-2, 120-3, and 120-4) are disposed on a plurality of side surfaces of the first semiconductor device (e.g., 130).
Regarding Claim 15, KANG (see, e.g., Fig. 18) shows the first semiconductor device (e.g., 130) has a quadrangular shape, and the dummy substrate (e.g., 140) has a frame-like shape with the first semiconductor device disposed at a center portion thereof, and the first semiconductor device has four side surfaces, and the plurality of core modules (e.g., 120-1, 120-2, 120-3, and 120-4) are disposed at two or more side portions of the dummy substrate.
Regarding Claim 16, KANG (see, e.g., Figs. 1 and 18) shows all aspects of the instant invention including a semiconductor package (e.g., semiconductor package 100A) comprising:
- a first substrate (e.g., redistribution structure 110)
-a first semiconductor device (e.g., semiconductor chip 130) disposed on the first substrate (see, e.g., Fig. 1)
-a core structure (e.g., antenna substrate 120 and core structure 140) disposed on the first substrate, spaced apart from a side surface of the first semiconductor device, and surrounding the first semiconductor device (see, e.g., Fig. 18)
- an encapsulant surrounding the first semiconductor device (e.g., encapsulant 150) and in contact with the core structure (e.g., 120 and 140) (see, e.g., Fig. 18)
-wherein the core structure includes a core module (e.g., 120) and a dummy substrate (e.g.,140), the core module including a core wiring (e.g., antenna member 122, and/or through-via 123, and/or director member 125) and a module substrate (e.g., dielectric layer 121) (see, e.g., Fig. 1)
-the core module is disposed on the first substrate, a side surface of the core module is surrounded by and spaced apart from an inner side surface of the dummy substrate, and the encapsulant is disposed between the dummy substrate and the side surface of the core module, the dummy substrate facing the side surface of the core module (see, e.g., Fig. 18)
- the first semiconductor device (e.g., 130) has a quadrangular shape, and the core structure has a frame-like shape with the first semiconductor device at a center portion thereof (see, e.g., Fig. 18)
-the core module is provided on two or more side portions of the core structure that respectively face side surfaces of the first semiconductor device (see, e.g., Fig. 18)
Claims 1-9 and 11-16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by HONG et al. (US 20240250011 A1).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding Claim 1, HONG (see, e.g., 4A and 4B) shows all aspects of the instant invention including a semiconductor package (e.g., semiconductor package 100b) comprising:
-a first substrate (e.g., redistribution layer 182)
-a first semiconductor device (e.g., semiconductor die 160) disposed on the first substrate (see, e.g., Fig. 4A)
-a dummy substrate (e.g., substrate 150) disposed on the first substrate, spaced apart from a side surface of the first semiconductor device (see, e.g., Fig. 4A), and surrounding the first semiconductor device (see, e.g., Fig. 4B)
-a core module (e.g., 170 and 172) disposed in the dummy substrate (see, e.g., Fig. 4B)
-an encapsulant surrounding the first semiconductor device (e.g., filler 180) and in contact with the dummy substrate (see, e.g., Fig. 4B)
-wherein the core module includes a core wiring (e.g., through silicon vias 172) and a module substrate (e.g., dummy die 170) (see, e.g., Fig. 4A)
-the core module is disposed on the first substrate, and a side surface of the core module is surrounded by and spaced apart from an inner side surface of the dummy substrate (see, e.g., Fig. 4B)
-the encapsulant is disposed between the dummy substrate and the side surface of the core module (see, e.g., Fig. 4A)
Regarding Claim 2, HONG (see, e.g., Figs. 4A and 4B) shows a plurality of core modules (e.g., dummy dies 170) (see, e.g., Fig. 4B), including the core module, are disposed in the dummy substrate (e.g., 150) and on the first substrate (e.g., 182) (see, e.g., Fig. 4A).
Regarding Claim 3, HONG (see, e.g., Fig. 4B) shows all side surfaces of each of the plurality of core modules (e.g., 170) are spaced apart from all inner surfaces of the dummy substrate (e.g., 150) that face the side surfaces of each of the plurality of core modules.
Regarding Claim 4, HONG (see, e.g., Fig. 4A) shows an uppermost surface of the module substrate (e.g., 170) of the plurality of core modules is coplanar with an upper surface of the dummy substrate (e.g., 150).
Regarding Claim 5, HONG (see, e.g., Figs. 4B and 4C, and Par. [0073]) shows
-the core wiring of a first core module (see, e.g., Fig. 4C) of the plurality of core modules (see, e.g., Fig. 4C and Par. [0073]) includes a first stack of core wirings (e.g. through silicon vias)
-the core wiring of a second core module (see, e.g., Fig. 4B) of the plurality of core modules (e.g., 170) includes a second stack of core wirings
-the first stack of core wirings (see, e.g., Fig. 4C) includes a first number of core wirings different from a second number of core wirings of the second stack of core wirings (see, e.g., Fig. 4B)
Regarding Claim 6, HONG (see, e.g., Figs. 4A and 4B) shows the plurality of core modules (e.g., 170) (see, e.g., Fig. 4B) include the core wiring (e.g. through silicon vias) arranged in a plurality of rows and a plurality of columns in a plan view parallel to the first substrate (e.g., 182) (see, e.g., Fig. 4A).
Regarding Claim 7, HONG (see, e.g., Fig. 4C and Par. [0073]) shows at least some core modules of the plurality of core modules (see, e.g., Fig. 4C and Par. [0073]) differ from the remaining core modules of the plurality of core modules (see, e.g., Fig. 4C and Par. [0073]) in at least one of a number of the rows or the columns of the core wiring.
Regarding Claim 8, HONG (see, e.g., Figs. 4B and 4C, and Par. [0073]) shows the plurality of core modules include a first core module (see, e.g., Fig. 4B) and a second core module (see, e.g., Fig. 4C and Par. [0073])
-the first core module includes the core wirings (e.g. through silicon vias) arranged in N rows and N columns, where N is a natural number of 2 or more
-the second core module includes the core wirings (e.g. through silicon vias) arranged in N rows and 2N columns
Regarding Claim 9, HONG (see, e.g., Figs. 4B and 4C, and Par. [0073]) shows the plurality of core modules include a first core module (see, e.g., Fig. 4B) and a second core module (see, e.g., Fig. 4C and Par. [0073])
-the first core module includes the core wiring (e.g. through silicon vias) arranged in N rows, where N is a natural number of 2 or more, and M columns, where M is a natural number of 2 or more
-the second core module includes the core wiring (e.g. through silicon vias) arranged in P rows, where P is a natural number of 2 or more, and Q columns, where Q is a natural number greater than M
Regarding Claim 11, HONG (see, e.g., Fig. 4B) shows the plurality of core modules all have a same number of stacks of the core wiring (e.g. through silicon vias).
Regarding Claim 12, HONG (see, e.g., Fig. 4A) shows a second substrate (e.g., redistribution layer 184) disposed on the encapsulant (e.g., 150) and electrically connected to the core module (e.g., 160).
Regarding Claim 13, HONG (see, e.g., Fig. 4A) shows the first substrate (e.g., 182) and the second substrate (e.g., 184) are each a redistribution structure.
Regarding Claim 14, HONG (see, e.g., Fig. 4B) shows the plurality of core modules (e.g., 170) are disposed on a plurality of side surfaces of the first semiconductor device (e.g., 160).
Regarding Claim 15, HONG (see, e.g., Fig. 4B) shows the first semiconductor device (e.g., 160) has a quadrangular shape, and the dummy substrate (e.g., 150) has a frame-like shape with the first semiconductor device disposed at a center portion thereof, and the first semiconductor device has four side surfaces, and the plurality of core modules (e.g., 170) are disposed at two or more side portions of the dummy substrate.
Regarding Claim 16, HONG (see, e.g., Figs. 4A and 4B) shows all aspects of the instant invention including a semiconductor package (e.g., semiconductor package 100b) comprising:
- a first substrate (e.g., redistribution layer 182)
-a first semiconductor device (e.g., semiconductor die 160) disposed on the first substrate (see, e.g., Fig. 4A)
-a core structure (e.g., 170, 172, and 150) disposed on the first substrate, spaced apart from a side surface of the first semiconductor device, and surrounding the first semiconductor device (see, e.g., Fig. 4B)
- an encapsulant surrounding the first semiconductor device (e.g., filler 180) and in contact with the core structure (e.g., 170, 172, and 150) (see, e.g., Fig. 4B)
-wherein the core structure includes a core module (e.g., 170 and 172) and a dummy substrate (e.g.,150), the core module including a core wiring (e.g., through silicon vias 172) and a module substrate (e.g., dummy die 170) (see, e.g., Fig. 4A)
-the core module is disposed on the first substrate, a side surface of the core module is surrounded by and spaced apart from an inner side surface of the dummy substrate, and the encapsulant is disposed between the dummy substrate and the side surface of the core module, the dummy substrate facing the side surface of the core module (see, e.g., Fig. 4B)
- the first semiconductor device (e.g., 160) has a quadrangular shape, and the core structure has a frame-like shape with the first semiconductor device at a center portion thereof (see, e.g., Fig. 4B)
-the core module is provided on two or more side portions of the core structure that respectively face side surfaces of the first semiconductor device (see, e.g., Fig. 4B)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over KANG et al. (US 20210398923 A1).
Regarding Claim 19, KANG shows most aspects of the instant invention (see, e.g., paragraph 20 above), except for a horizontal width between the dummy substrate and the side surface of the core module that is about 1 micrometer (μm) to about 5 μm. Although KANG fails to specify a horizontal width between the dummy substrate and the side surface of the core module, it would be necessary to form a horizontal width between the dummy substrate and the side surface of the core module that ensures enough space to fill with encapsulant and allows enough elasticity to allow for expansion and contraction of the plurality of antenna substrates. It is also noted that the specification fails to provide teachings about the criticality of having a horizontal width between the dummy substrate and the side surface of the core module that is about 1 micrometer (μm) to about 5 μm. Differences in widths will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such widths are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph below) of the claimed horizontal width, and since KANG depicts a horizontal width known in the art, it would have been obvious to one of ordinary skill in the art to use these ratio values in the device of KANG.
CRITICALITY: The specification contains no disclosure of either the critical nature of the claimed dimensions or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1939 (Fed. Cir. 1990).
Allowable Subject Matter
Claim 20 is allowable.
Claims 17 and 18 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited disclose semiconductor assembly comprising a 3D block and component-embedded substrate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H AMRAN whose telephone number is (571)272-0950. The examiner can normally be reached Mo-Fri 9am to 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael M Fahmy can be reached at (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H AMRAN/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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