DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 8-13, 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 20190376845 A1, hereinafter Liu) in view of Hagihara (US 20120138772 A1).
Regarding claim 1, Liu discloses an image sensor device (¶0049, ¶0069, sensor 370, fig. 3, 535, fig. 5) comprising:
a pixel array including a plurality of pixels for detecting an optical signal (Each of image sensors 120a, 120b, 120c, and 120d may include a pixel array configured to generate image data representing different fields of views along different directions. – ¶0069); and
a control circuit (330, fig. 3, controller 1110, fig 11) configured to generate count information (counter count value, fig. 8, ¶0113-0118),
wherein each of the plurality of pixels is configured to:
determine a time code (third count value, ¶0058) based on a detection signal detected from the pixel, the ramp signal, and the count information (see comparator 804, takes in ramp 815 and pixel signal from node 614, and counter output 814 is latched in DAC 813, figs. 8, 9a-b; ¶0058, ¶0116-0122);
perform a reset on the pixel based on the time code and the inverse count information (¶0019, ¶0058, Moreover, the counter can be reset at the beginning of each sub-stage, which shrinks the input voltage range and/or the range of time to be quantized - ¶0141;
Moreover, as counter 808 is reset at time T1A, the input voltage range to be represented by the count values of counter 808 is shrunk, which allows counter 808 to update count values at a higher frequency (e.g., by operating with a faster clock) to reduce the quantization step and to improve the quantization resolution of the FD ADC operation, while the bit width of counter 808 (and the associated hardware circuits) needs not be expanded to support the improved quantization resolution. – ¶0149);
generate sampling data based on the ramp signal and a residual detection signal of the pixel (The processing circuits can transfer the residual charge from the photodiode to the charge storage device to develop a second voltage for a second mode of measurement. In the second mode of measurement, the processing circuits can perform another quantization process by comparing the second voltage against a second ramping threshold voltage to generate a second decision. When the second decision indicates that the first crosses the second ramping reference voltage, a second count value can be captured from the counter and stored in the memory. –
¶0057
sampling data after saturation count and/or ramp cross count in figs. 9a-b, based on decision 816. 816 is understood as residual detection, fig. 8); and
output the time code and the sampling data (¶0017, ¶0058-060).
Liu is not found disclosing expressly the limitation of inverse count information to be provided to the pixels.
However, Hagihara discloses that an up-down counter used in ADC can flexibly perform up and down count, based on operation mode. An inverse count operation can achieve same ADC performance using an up-down counter instead of up counter only (¶0085).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the invention of Liu, using an up-down counter of Hagihara, such that when the third count value is determined in case of charge amount saturates (¶0058), using the counter in down counter mode (understood as inverse count information) for subsequent ADC operations, because, simple substitution of one known element for another to obtain predictable results is obvious. Furthermore, such combination would make the mode transitions more efficient.
Regarding claim 2, Liu in view of Hagihara discloses the image sensor device of claim 1, wherein each of the plurality of pixels includes:
a photo detector (PD 602, fig. 6, ¶0106) configured to detect the optical signal and convert the detected optical signal into the detection signal (¶0106); and
a processing circuit (As shown in FIG. 6, pixel cell 600 may include a photodiode 602 as well as processing circuits including a shutter switch 604, a transfer gate 606, a reset switch 607, a charge sensing unit 608 comprising charge storage unit 608a and a buffer 608b, and a pixel ADC 610. – ¶0105) configured to generate the time code and the sampling data based on the detection signal, the ramp signal, the count information, and the inverse count information (In some examples, the processing circuits can also perform a third mode of measurement. In the third mode of measurement, the processing circuits can compare the first voltage with a static threshold voltage representing a saturation limit of the charge storage unit to generate a third decision. When the third decision indicates that the charge storage unit reaches or exceeds the saturation limit, a third count value can be captured from the counter and stored in the memory. The third count value can represent a measurement of the time it takes for the charge storage unit to become saturated, and the duration of time can be inversely proportional to the intensity of the incident light. For the rest of the disclosure, the third mode of measurement may be referred as time-to-saturation (TTS) measurement operation. In some examples, the third mode of measurement can be performed before the first mode of measurement. – ¶0058. Inverse count information is used as combined with Hagihara.).
Regarding claim 3, Liu in view of Hagihara discloses the image sensor device of claim 2, wherein the control circuit is further configured to generate a clock signal, and
wherein the processing circuit includes:
a reset control circuit configured to determine the time code based on the detection signal and the ramp signal and to generate a reset signal based on the time code and the inverse count information (¶0058, reset phase in ¶0127-0128, fig. 12);
an analog-to-digital converter (610, fig. 8) configured to generate the sampling data based on the residual detection signal, the ramp signal, and the count information (¶0105-0106, ¶0118); and
a memory circuit (810, figs. 8, 11) configured to temporarily store the time code and the sampling data (¶0058, ¶0113, ¶0138).
Regarding claim 4, Liu in view of Hagihara discloses the image sensor device of claim 3, wherein the reset control circuit includes:
a first comparator (804, fig. 8) configured to compare the detection signal (614, fig. 8) with the ramp signal (Vref 815, fig. 8) to generate a first comparison signal (decision 816, fig. 11, ¶0126);
a TC circuit configured to determine the time code based on the first comparison signal and the count information (¶0058, 011, 0117); and
a reset signal generating circuit (1116, fig. 11) configured to generate the reset signal based on the time code and the inverse count information (¶0126, ¶0129, see 1202, 1502 and 1404 reset signals for ramping reset, fig. 15).
Regarding claim 8, Liu in view of Hagihara discloses the image sensor device of claim 4, wherein the analog-to-digital converter includes a second comparator configured to compare the residual detection signal with the ramp signal to generate a second comparison signal (…at time T3, comparator 1102 compares the OF voltage against VPDSAT which, as described above, represents the voltage at the COF capacitor when it stores a quantity of residual charge that saturates the photodiode PD. If the residual charge stored in the COF capacitor is less than the saturation capacity of the photodiode PD, the voltage at the COF capacitor can be higher than VPDSAT, and the output of comparator 1102 can remain low. – ¶0138), and
wherein the memory circuit (810, fig. 11) is configured to determine the sampling data based on the second comparison signal and the count information (The selected ADC code can be stored in memory 810, and memory 810 can be locked based on a combination of the FLAG_1 and FLAG_2 signals by NOR gate 1116 to prevent subsequent measurement phases from overwriting the selected ADC code output in memory 810. At the end of the three-phase measurement process, controller 1110 can retrieve the ADC code stored in memory 810 and provide the ADC code as the digital output representing the incident light intensity. – ¶0126).
Regarding claim 9, Liu in view of Hagihara discloses the image sensor device of claim 1, wherein the time code is digital data having N bits (With the same number of bits of the counter… ¶0065), and
wherein the sampling data is digital data having M bits (The analog voltage developed at charge storage unit 608a can be sampled and digital output can be generated before the end of the exposure period – ¶0111).
Regarding claim 10, Liu in view of Hagihara a method (¶0022, 0025, figs. 9a-b, fig. 18) of operating an image sensor (¶0049, ¶0069, sensor 370, fig. 3, 535, fig. 5) including a plurality of pixels for detecting an optical signal (Each of image sensors 120a, 120b, 120c, and 120d may include a pixel array configured to generate image data representing different fields of views along different directions. – ¶0069), the method comprising:
performing a first mode (first and/or third mode, ¶0056-0058) operation of determining a time code and performing a reset in each of the plurality of pixels (The processing circuits can measure the intensity of the incident light by performing multiple modes of measurement. In a first mode of measurement, the processing circuits can perform a quantization process by comparing the first voltage against a first ramping threshold voltage to generate a first decision.- ¶0056, FD ADC,
In some examples, the processing circuits can also perform a third mode of measurement. In the third mode of measurement, the processing circuits can compare the first voltage with a static threshold voltage representing a saturation limit of the charge storage unit to generate a third decision. When the third decision indicates that the charge storage unit reaches or exceeds the saturation limit, a third count value can be captured from the counter and stored in the memory. The third count value can represent a measurement of the time it takes for the charge storage unit to become saturated, and the duration of time can be inversely proportional to the intensity of the incident light. – ¶0058
¶0056-0058); and
performing a second mode (second mode, ¶0057) operation of generating sampling data in each of the plurality of pixels (¶0057), and
wherein the first mode operation includes:
determining the time code (third count value, ¶0058) based on a detection signal of the pixel, a ramp signal, and count information (see comparator 804, takes in ramp 815 and pixel signal from node 614, and counter output 814 is latched in DAC 813, figs. 8, 9a-b; ¶0058, ¶0116-0122); and
performing the reset on the pixel based on the time code and inverse count information (¶0019, ¶0058, Moreover, the counter can be reset at the beginning of each sub-stage, which shrinks the input voltage range and/or the range of time to be quantized - ¶0141;
Moreover, as counter 808 is reset at time T1A, the input voltage range to be represented by the count values of counter 808 is shrunk, which allows counter 808 to update count values at a higher frequency (e.g., by operating with a faster clock) to reduce the quantization step and to improve the quantization resolution of the FD ADC operation, while the bit width of counter 808 (and the associated hardware circuits) needs not be expanded to support the improved quantization resolution. – ¶0149), and
wherein the second mode operation includes generating the sampling data based on the ramp signal and a residual detection signal of the pixel (A second ramping threshold voltage (labelled “second ramping VREF” in FIG. 12) can be supplied to comparator 1102 to be compared against the buffered and error-compensated version of analog voltage at the OF node (VIN). The second ramping VREF can have a voltage range between VPDSAT, which represents the voltage at COF capacitor when it stores a quantity of residual charge that saturates the photodiode PD, and VRESET. If the second ramping VREF matches the VIN (within one quantization step), the output of comparator 1102 may flip, and the count value generated by counter 808 at the time of flipping can be stored into memory 810, if the memory is not locked by the first phase of measurement (as indicated by the zero value of FLAG_1 signal) or by the second phase of measurement (as indicated by the zero value of FLAG_2 signal). – ¶0133. Also see ¶0140).
Regarding claim 11, Liu in view of Hagihara method of claim 10, wherein each of the plurality of pixels includes a photo detector and a processing circuit (PD 602, fig. 6, ¶0106), and
wherein the first mode operation includes:
detecting, by the photo detector, the optical signal and converting the detected optical signal to the detection signal;
determining, by the processing circuit (As shown in FIG. 6, pixel cell 600 may include a photodiode 602 as well as processing circuits including a shutter switch 604, a transfer gate 606, a reset switch 607, a charge sensing unit 608 comprising charge storage unit 608a and a buffer 608b, and a pixel ADC 610. – ¶0105), the time code based on the detection signal, the ramp signal, and the count information (In some examples, the processing circuits can also perform a third mode of measurement. In the third mode of measurement, the processing circuits can compare the first voltage with a static threshold voltage representing a saturation limit of the charge storage unit to generate a third decision. When the third decision indicates that the charge storage unit reaches or exceeds the saturation limit, a third count value can be captured from the counter and stored in the memory. The third count value can represent a measurement of the time it takes for the charge storage unit to become saturated, and the duration of time can be inversely proportional to the intensity of the incident light. For the rest of the disclosure, the third mode of measurement may be referred as time-to-saturation (TTS) measurement operation. In some examples, the third mode of measurement can be performed before the first mode of measurement. – ¶0058. Inverse count information is used as combined with Hagihara.); and
performing, by the processing circuit, a reset on the photo detector based on the time code and the inverse count information (¶0058, reset phase in ¶0127-0128, fig. 12).
Regarding claim 12, Liu in view of Hagihara discloses the method of claim 11, wherein the determining of the time code includes:
generating, by the processing circuit, a first comparison signal (decision 816, fig. 11, ¶0126) by comparing the detection signal (614, fig. 8) with the ramp signal (Vref 815, fig. 8); and
determining, by the processing circuit, the time code based on the first comparison signal and the count information (¶0126, ¶0129, see 1202, 1502 and 1404 reset signals for ramping reset, fig. 15).
Regarding claim 13, Liu in view of Hagihara discloses the method of claim 12, wherein a magnitude of the ramp signal is maintained uniformly in the first mode operation (evident from Vref signal in figs. 12-17).
Regarding claim 15, Liu in view of Hagihara discloses the method of claim 11, wherein the second mode operation includes:
generating, by the processing circuit, a second comparison signal by comparing the residual detection signal and the ramp signal (…at time T3, comparator 1102 compares the OF voltage against VPDSAT which, as described above, represents the voltage at the COF capacitor when it stores a quantity of residual charge that saturates the photodiode PD. If the residual charge stored in the COF capacitor is less than the saturation capacity of the photodiode PD, the voltage at the COF capacitor can be higher than VPDSAT, and the output of comparator 1102 can remain low. – ¶0138); and
generating, by the processing circuit, the sampling data based on the second comparison signal and the count information (The selected ADC code can be stored in memory 810, and memory 810 can be locked based on a combination of the FLAG_1 and FLAG_2 signals by NOR gate 1116 to prevent subsequent measurement phases from overwriting the selected ADC code output in memory 810. At the end of the three-phase measurement process, controller 1110 can retrieve the ADC code stored in memory 810 and provide the ADC code as the digital output representing the incident light intensity. – ¶0126).
Regarding claim 16, Liu in view of Hagihara discloses the method of claim 15, wherein a magnitude of the ramp signal increases at a uniform slope in the second mode operation (evident from figs. 12-17).
Regarding claim 17, Liu in view of Hagihara discloses the method of claim 11, wherein the processing circuit includes a memory circuit, and
further comprising:
storing, by the memory circuit (810), the time code (¶0058);
determining, by the memory circuit, the sampling data (¶0058); and
outputting, by the memory circuit, output data including the stored time code and the determined sampling data (The different modes of measurements can be targeted for different light intensity ranges, and the processing circuits can output one of the first, second, or third count values from the memory to represent the intensity of the incident light based on which light intensity range the incident light belongs to. – ¶0059).
Regarding claim 18, Liu in view of Hagihara discloses the method of claim 17, wherein the outputting of the output data includes:
outputting the stored time code (¶0059);
initializing the memory circuit (But as to be described below, controller 1110 will perform one more checking of the output of comparator 1102 before locking memory 810. Counter 808 can then be reset and start counting from an initial value after the FD ADC 1 operation completes. – ¶0145); and
outputting the determined sampling data (¶0147).
Regarding claim 19, Liu discloses an image sensor device (¶0049, ¶0069, sensor 370, fig. 3, 535, fig. 5) comprising:
a pixel array including a plurality of pixels (Each of image sensors 120a, 120b, 120c, and 120d may include a pixel array configured to generate image data representing different fields of views along different directions. – ¶0069);
a ramp generator (802, fig. 8) configured to generate a ramp signal in response to a ramp control signal (¶0113-0116);
a clock generator configured to generate a clock signal based on a clock control signal (812, figs. 8-9, ¶0113-0119);
a counter (808, fig. 8) configured to generate count information based on a count control signal and the clock signal (¶0113-0117);
an analog-to-digital (adc 610, fig. 8) converting array configured to generate a comparison signal by comparing a detection signal output from the pixel array with the ramp signal, and to generate sampling data based on the comparison signal and the count information (¶0113-0119);
a reset control circuit (comparator 804, fig. 8) configured to generate a time code based on the comparison signal and the count information, and to generate a reset signal based on the time code (¶0014-0019, ¶0058; Moreover, the counter can be reset at the beginning of each sub-stage, which shrinks the range of time (and the corresponding input voltage range) to be measured by the full output range of the counter. – ¶0065);
an output buffer (memory 810, fig. 8) configured to store the sampling data and the time code and to output output data including the stored sampling data and the stored time code (¶0113, ¶0115, ¶0124-0126); and
a control circuit (330, fig. 3, controller 1110, fig 11) configured to generate the ramp control signal (counter count value, fig. 8, ¶0113-0118), the clock control signal (812, figs. 8-9, ¶0113-0119), the count control signal (counter count value, fig. 8, ¶0113-0118)
Liu is not found disclosing expressly the limitation of an inverse counter configured to generate inverse count information based on an inverse count control signal and the clock signal, and control circuit configured to generate the inverse count control signal.
However, Hagihara discloses that an up-down counter used in ADC can flexibly perform up and down count, based on operation mode. An inverse count operation can achieve same ADC performance using a down counter instead of up counter only (¶0085).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the invention of Liu, using an up-down counter of Hagihara, such that when the third count value is determined in case of charge amount saturates (¶0058), using the counter in down counter mode (understood as inverse count information) for subsequent ADC operations, to obtain, an inverse counter configured to generate inverse count information based on an inverse count control signal and the clock signal, and control circuit configured to generate the inverse count control signal, because, simple substitution of one known element for another to obtain predictable results is obvious. Furthermore, such combination would make the mode transitions more efficient.
Regarding claim 20, Liu in view of Hagihara discloses the image sensor device of claim 19, wherein each of the plurality of pixels may include a photoelectric conversion element (PD 602, fig. 6, ¶0106), and
wherein the photoelectric conversion element includes any one of a CCD (Charge Coupled Devices) or a CMOS (Complementary Metal Oxide Semiconductor) (¶0030).
Allowable Subject Matter
Claims 5-7, 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Prior arts of record taken alone or in combination fails to reasonably disclose or suggest,
Regarding claim 5, wherein, during an integration time, a count value of the count information gradually increases and a count value of the inverse count information gradually decreases,
wherein the TC circuit determines the count value of the count information as the time code when a level of the first comparison signal changes, and
wherein the reset signal generating circuit generates the reset signal when the count value of the inverse count information reaches the time code.
Claims 6-7 are allowable for being dependent on allowable claim 5.
Regarding claim 14, wherein, during an integration time, a count value of the count information gradually increases and a count value of the inverse count information gradually decreases,
wherein, by the processing circuit, a count value of the count information when a level of the first comparison signal changes is determined as the time code, and
wherein, by the processing circuit, when a count value of the inverse count information reaches the time code, a reset signal is generated.
Conclusion
The prior and/or pertinent art(s) made of record and not relied upon is considered pertinent to applicant's disclosure, are – Gao et al. (US 11595602 B2), Guidash et al. (US 20160028974 A1), who disclose different ADC structures of interest.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHBAZ NAZRUL whose telephone number is (571)270-1467. The examiner can normally be reached M-Th: 9.30 am-3 pm, 6.30 pm-9 pm, F: 9.30 am-1.30 pm, 4 pm-8 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached on 571-272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAHBAZ NAZRUL/Primary Examiner, Art Unit 2638
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