DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The following is a final office action in response to applicant’s reply, filed on 08/12/2026, to the Non-Final Office Action mailed on 06/10/2026.
Claims 1, 7-11, 13, 14, 17, and 19 are amended. Claims 1-20 are pending and addressed below.
Applicant’s amendment has overcome claim objection, and rejection under 112(b), previously set forth in the non-final office action.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 17-19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claims 17 and 19 recite “a register value, set in a register of the network controller, indicating whether aggregation of the second split packets is enabled” when receiving packets. However, specification does not expressly provide a method for setting the register with a value for an operational action as disclosed in Fig. 13 and associated description. Moreover, Spec recites “register set value of each packet” (see e.g., Spec [160], [161]), however, it is not clear how register value is determined for each packet for aggregation or not. Claim 18 is subjected to the same rejected by virtue of its dependency on rejected claim 17.
Claim Rejections - 35 USC § 103
Claims 1-2, 7, and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Pandey; Sujan et al US 20240214304 A1, hereinafter Pandey, in view of IDS reference, Valk; Kenneth M.et al US 20110261837 A1, hereinafter Valk, and further in view of KIM; Donggun US 20240306037 A1, hereinafter KIM.
Regarding claims 1 and 20, Pandey teaches, a network controller (see Pandey Fig. 3) comprising:
based on error information transmitted through a plurality of data link layers and a plurality of physical layers respectively corresponding to a plurality of ports managed by one transaction layer], a port monitor circuit configured to determine a number of valid ports available among the plurality of ports by monitoring a status of the plurality of ports (“physical layers respectively corresponding to a plurality of ports” is interpreted as corresponding to communication links/lanes/channels/ports of physical layer. The limitation is understood as maintaining working or active links/lanes/channels/ports, based on fault or error associated with individual ports. See Pandey Figs.4A, 4B; [48] “the circuit architecture 200, illustrates various link partners of the communication link 106 and their associated sub blocks within the physical layer for communication between the first node 102 and the second node 104 (of FIG. 1) to facilitate a high data rate”; [9] “the logic at the communication interface is configured to periodically communicate the communication lane status of the number of communication lanes to each of the communication interface at the first end and the other communication interface at the second end of the communication link. If any fault is detected in any one lane of the number of communication lanes, the logic immediately communicates the lane failure to each of the communication interface at the first end and the other communication interface at the second end and stop sending the number of subframes of the data frame over the faulty lane. Moreover, the logic is configured to shut down the gate and buffer corresponding to the faulty lane and maintains the communication between both ends of the communication link through the remaining communication lanes, which are active at that time.”, and [46], [55], teaches maintaining active communication lanes (i.e., port) based on fault i.e., error);
a split circuit configured to split one packet one packet into split packets and to transmit the split packets to the valid ports based on the number of valid ports (Pandey [0046] “The logic 206 is further configured to store a communication lane status for each of the communication lanes 108 and when detecting that the communication lane status for a specific communication lane has changed to a determined status. … The logic 206 is further configured to split any data frame into a number of subframes corresponding to the number of communication lanes with a communication status which is not the determined status, and send each of the subframes over one distinct communication lane amongst the communication lanes with a communication status which is not the determined status. The logic 206 is configured to store the communication lane status for each of the number of communication lanes 108 in the communication link 106. For example, in a case when it is detected that the communication lane status for the specific communication lane (e.g., lane 1) has changed to the determined status (or faulty status). In that case, the logic 206 is further configured to stop sending the subframes over that specific communication lane (i.e., lane 1) … Moreover, the logic 206 is further configured to split the data frame into the number of subframes corresponding to the number of communication lanes 108, which are active at that time. The logic 206 is further configured to send each of the subframes over one distinct communication lane among the number of communication lanes 108 which are active at that time.”).
While teaching transmission thorough OAM layer, data link layer and physical layer (see Pandey [55] “The information about the changed (i.e., faulty) status of the lane 1 is communicated to the communication interface 110 at the first end 202 as well as to the other communication interface 112 at the second end 204 of the communication link 106 by use of the “common message” field of OAM message. … Additionally, the MAC layer at each of the communication interface 110 and the other communication interface 112 is notified through MAC interface (e.g., MII interface) that the link capacity will be lowered for both directions”), Pandey does not expressly teach, however, in the same field of endeavor, Valk teaches, transmitted through a plurality of data link layers and a plurality of physical layers respectively corresponding to a plurality of ports managed by one transaction layer (see Valk fig. 1D teaching, a single transport layer entity is coupled to a number of link layer and physical layer entities, [0030] "The TLs 122 provide reliable transport of packets, including recovering from [ .. ] broken links 106, 108 in the path between source and destination", [0030] "the interface switch 120 connects the 7 TLs 122 and the 26 iLinks 124 in a crossbar switch", [30] "The iLink layer protocol 124 handles link level flow control, error checking CRC generating and checking", see also Valk [9]-[10], teaching segmentation and buffering of packets).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Pandey to include the features as taught by Valk above in order to provide an effective method and circuit to implement end-to-end credit management in an interconnect system for enhanced large packet reassembly (Valk [0006]).
Pandey and Valk do not expressly teach, however, in the same field of endeavor, KIM teaches, a reorder buffer (KIM [173] “An RLC layer device may store a data segment in a buffer, … reassemble the data segments to configure complete data”) configured to sort an order of second split packets received from another network controller through the plurality of ports based on a split tag and a split identification (ID) included in a prefix of each of the second split packets, and configured to restore the second split packets to one packet (KIM Fig. 1L; [204], [206]-[207], Claim 1 “segmenting the RLC SDU into at least two segments; generating a header of each of the at least two segments, the header including information for identifying whether the RLC SDU has been segmented and sequence number information for identifying an order of the each of the at least two segments;”, Claim 13 “… receive a message including a radio resource control (RLC) protocol data unit (PDU) from a transmission device, …”, Claim 14 “wherein the information for identifying whether the RLC SDU has been segmented is a segmentation information (SI) field, wherein the SI field indicates whether the RLC SDU has not been segmented, whether a segment is a first segment of the RLC SDU, whether a segment is a last segment of the RLC SDU, or whether a segment is a segment other than the first and last segments of the RLC SDU, and wherein the sequence number information for identifying the order of the each of the at least two segments has a sequence number in ascending order according to a sequence of the at least two segments.”, teaches, reassembling segmented RLC SDUs (=packets) based on segmentation information (SI) field (=split tag) and the sequence number (SN) information (=split ID) in the header (=prefix) of each segment. Packets are received through physical layer comprising plurality of radio channels (see Fig. 1B)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Pandey and Valk to include the features as taught by KIM above, in order to reduce data processing time, provide a method which improves a header structure suitable for a hardware accelerator or a procedure such as an autonomous repeat request (ARQ) operation (KIM [0008]).
With respect to claim 20, claim recites the identical features of claim 1 for a corresponding method. Therefore, it is subjected to the same rejection.
Regarding claim 2, Pandey, in view of Valk and KIM, teaches the network controller, as outlined in the rejection of claim 1.
Pandey further teaches, wherein the error information comprises at least one of: a link training and status state machine (LTSSM) indicating a status of a link for each of the plurality of physical layers; an error message generated by an error of the one packet in the plurality of data link layers (Pandey [53] “If any fault is detected in any one lane of the number of communication lanes 108, the logic 206 immediately communicates the lane failure to each of the communication interface 110 and the other communication interface 112 by use of the “common message” of the OAM message”, teaches OAM message (i.e., error message). Satisfies “or” criteria of the claim); or transaction layer packet (TLP) information transmitted through the one transaction layer.
Regarding claim 7, Pandey, in view of Valk and KIM, teaches the network controller, as outlined in the rejection of claim 1.
Pandey further teaches, wherein the split circuit is configured to split the one packet for the valid ports into packets based on at least one of whether the one packet comprises a payload or a register value, set in a register, indicating a type of the one packet (see Pandey [0046] teaching, splitting a data frame i.e., a payload. Satisfies “or” criteria).
Regarding claim 14, Pandey, in view of Valk and KIM, teaches the network controller, as outlined in the rejection of claim 1.
KIM further teaches, wherein the reorder buffer is configured to verify whether all of the second split packets have arrived by comparing a number of split included in the prefix of each of the second split packets with the split ID, and to sort the order of the second split packets using the split tag and the split ID (Implied in KIM).
Regarding claim 15, Pandey, in view of Valk and KIM, teaches the network controller, as outlined in the rejection of claim 1.
Valk further teaches, wherein the reorder buffer is configured to increase a first counter value as the second split packets are received from the other network controller and configured to allocate the received second split packets to a way buffer according to whether the increased first counter value matches a tag value of split packets to be currently processed (see Valk [10] implying the feature of the claim).
Regarding claim 16, Pandey, in view of Valk and KIM, teaches the network controller, as outlined in the rejection of claim 15.
Valk further teaches, wherein the reorder buffer is configured to restore the second split packets to the one packet by increasing and sorting a second counter value corresponding to a number of packets that arrive at a first counter in response to the increased first counter value not matching the tag value of the split packets to be currently processed (see Valk [10] implying the feature of the claim).
Regarding claim 17, Pandey, in view of Valk and KIM, teaches the network controller, as outlined in the rejection of claim 1.
Valk further teaches, further comprising: an aggregation circuit configured to restore the second split packets to the one packet by aggregating the second split packets based on a register value, set in a register of the network controller, indicating whether aggregation of the second split packets is enabled (see Valk Fig. 5 and para [49] implying the feature of the claim. Aggregation based on a register value is interpreted, under BRI, as determining that restoring of the packet from received segmented packets is needed).
Regarding claim 18, Pandey, in view of Valk and KIM, teaches the network controller, as outlined in the rejection of claim 17.
Valk further teaches, wherein the aggregation circuit is configured to aggregate headers of the second split packets into one header and configured to aggregate payloads of the second split packets into one payload (see Valk Fig. 5 and para [49] implying the feature of the claim).
Regarding claim 19, Pandey, in view of Valk and KIM, teaches the network controller, as outlined in the rejection of claim 17.
Valk further teaches, wherein the aggregation circuit is configured to: transmit the second split packets to the reorder buffer based on whether the second split packets comprise a payload; and determine whether to aggregate the second split packets based on the register value (see Valk Fig. 5 and para [49] implying the feature of the claim).
Claims 3, 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Pandey, in view of Valk and KIM, as applied to the rejection of claim 1 above, and further in view of IDS reference JEON; Yong Tae US 20220382692 A1, hereinafter JEON.
Regarding claim 3, Pandey, in view of Valk and KIM, teaches the network controller, as outlined in the rejection of claim 2.
Pandey further teaches, wherein the port monitor circuit is configured to determine, [by the LTSSM], whether communication of a physical layer corresponding to each of the plurality of ports is possible and configured to disable an invalid port unusable among the plurality of ports based on a type of the error message transmitted through a port capable of performing communication through the physical layer (see Pandey [53] “stop sending (or receiving) the number of subframes 218 of the data frame 208 over the faulty lane. Moreover, the logic 206 is configured to shut down the gate and buffer corresponding to the faulty lane and maintains the communication between both ends of the communication link 106 through remaining communication lanes which are active at that time.”).
Pandey and Valk and KIM do not expressly teach, however, in the same field of endeavor, JEON teaches, by the LTSSM (JEON [41] “the recovery controller 122 may control the LTSSM module 130 to perform a link recovery operation with respect to the host 2000”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Pandey and Valk to include the features as taught by JEON above in order to be directed to a PCIe interface device having improved link recovery performance and an operating method thereof (JEON [0007]).
Regarding claim 4, Pandey, in view of Valk and KIM and JEON, teaches the network controller, as outlined in the rejection of claim 3.
Pandey and JEON further teach, wherein the port monitor circuit is configured to disable the invalid port (see Pandey [53] above about disabling invalid port), and then configured to train a link of the disabled invalid port (see JEON Figs. 3 and 4 teaching, recovery and Link training).
Regarding claim 6, Pandey, in view of Valk and JEON, teaches the network controller, as outlined in the rejection of claim 3.
Pandey further teaches, wherein, in response to the type of the error message indicating non-correctable errors, the port monitor circuit is configured to disable the invalid port or configured to request error handling from a root complex according to whether the non-correctable errors are fatal errors (see Pandey [53] and rejection of claim 3 above).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Pandey, in view of Valk and KIM and JEON, as applied to the rejection of claim 3 above, and further in view of Knapp; David J. US 20100188972 A1, hereinafter Knapp.
Regarding claim 5, Pandey, in view of Valk, KIM and JEON, teaches the network controller, as outlined in the rejection of claim 3.
Pandey and Valk, KIM and JEON do not expressly teach, however, in the same field of endeavor, Knapp teaches, wherein, in response to the type of the error message indicating correctable errors, the port monitor circuit is configured to count a number of the correctable errors and configured to disable the invalid port among the plurality of ports based on the number of the correctable errors (Knapp [0120] “If a link is intermittently faulty (i.e., producing coding or CRC errors), the receiving node can set some threshold of error rate and shut down the link if the threshold is exceeded. Shutting down the link means not forwarding a frame received on one port to the other port”.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Pandey and Valk and JEON and KIM to include the features as taught by Knapp above in order to provides a fault tolerant network capable of supporting the existing applications serviced (Knapp [0019]).
Allowable Subject Matter
Claims 8 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 9, 11-13 are subjected to the same objection by virtue of their dependency on the above objected claims.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/MAHBUBUL BAR CHOWDHURY/Primary Examiner, Art Unit 2475
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