DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 1 and 20 are objected to because expression “split and transmit one packet to the valid ports based on the number of valid ports” does not expressly recite split packets of the one packet, not the one packet itself, are transmitted to the valid ports, in line with the disclosure
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-13 and 17-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 expression “the split circuit is configured to broadcast the one packet to the valid ports” lacks clarity. It is not clear whether the one packet or split packets of the one packet are broadcast. Claim 1, upon which claim 8 depends, recites the one packet is split into smaller packets. Claim 9 is subjected to the same rejection for reciting identical limitation.
Claims 7, 8, 9, 10, 13, 17 and 19 recite expression “register set value” which is not understood. It is not clear from the claims what it represents or signifies for an associated packet. Claims 11, 12 and 18 are subjected to the same rejection because of their dependency on above rejected claims 9 and 17.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 7, 10 and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Pandey; Sujan et al US 20240214304 A1, hereinafter Pandey, in view of IDS reference, Valk; Kenneth M.et al US 20110261837 A1, hereinafter Valk.
Regarding claims 1 and 20, Pandey teaches, a network controller (see Pandey Fig. 3) comprising:
based on error information [transmitted through a plurality of data link layers and a plurality of physical layers respectively corresponding to a plurality of ports managed by one transaction layer], a port monitor circuit configured to determine a number of valid ports available among the plurality of ports by monitoring a status of the plurality of ports (“physical layers respectively corresponding to a plurality of ports” is interpreted as corresponding to communication links/lanes/channels/ports of physical layer. The limitation is understood as maintaining working or active links/lanes/channels/ports, based on fault or error associated with individual ports. See Pandey Figs.4A, 4B; [48] “the circuit architecture 200, illustrates various link partners of the communication link 106 and their associated sub blocks within the physical layer for communication between the first node 102 and the second node 104 (of FIG. 1) to facilitate a high data rate”; [9] “the logic at the communication interface is configured to periodically communicate the communication lane status of the number of communication lanes to each of the communication interface at the first end and the other communication interface at the second end of the communication link. If any fault is detected in any one lane of the number of communication lanes, the logic immediately communicates the lane failure to each of the communication interface at the first end and the other communication interface at the second end and stop sending the number of subframes of the data frame over the faulty lane. Moreover, the logic is configured to shut down the gate and buffer corresponding to the faulty lane and maintains the communication between both ends of the communication link through the remaining communication lanes, which are active at that time.”, and [46], [55], teaches maintaining active communication lanes (i.e., port) based on fault i.e., error);
a split circuit configured to split and transmit one packet to the valid ports based on the number of valid ports (Pandey [0046] “The logic 206 is further configured to store a communication lane status for each of the communication lanes 108 and when detecting that the communication lane status for a specific communication lane has changed to a determined status. … The logic 206 is further configured to split any data frame into a number of subframes corresponding to the number of communication lanes with a communication status which is not the determined status, and send each of the subframes over one distinct communication lane amongst the communication lanes with a communication status which is not the determined status. The logic 206 is configured to store the communication lane status for each of the number of communication lanes 108 in the communication link 106. For example, in a case when it is detected that the communication lane status for the specific communication lane (e.g., lane 1) has changed to the determined status (or faulty status). In that case, the logic 206 is further configured to stop sending the subframes over that specific communication lane (i.e., lane 1) … Moreover, the logic 206 is further configured to split the data frame into the number of subframes corresponding to the number of communication lanes 108, which are active at that time. The logic 206 is further configured to send each of the subframes over one distinct communication lane among the number of communication lanes 108 which are active at that time.”); and
a reorder buffer configured to sort an order of second split packets received from another network controller through the plurality of ports and configured to restore the second split packets (Pandey [49] “the logic 206 is further configured to cooperate with the communication interface 112 at the second end 204 of the communication link 106 to receive a data frame from the second end 204 over the communication lanes 108. A received data frame being split into a number of received subframes corresponding to the number of communication lanes 108, where receiving the data frame includes receiving each of the subframes over one distinct communication lane amongst said communication lanes and merging the received subframes into a received data frame, [0051] FEC decoded data goes to each buffer of the number of buffers 226 corresponding to a specific communication lane”. “second split packet” is interpreted as a received split packet).
While teaching transmission thorough OAM layer, data link layer and physical layer (see Pandey [55] “The information about the changed (i.e., faulty) status of the lane 1 is communicated to the communication interface 110 at the first end 202 as well as to the other communication interface 112 at the second end 204 of the communication link 106 by use of the “common message” field of OAM message. … Additionally, the MAC layer at each of the communication interface 110 and the other communication interface 112 is notified through MAC interface (e.g., MII interface) that the link capacity will be lowered for both directions”), Pandey does not expressly teach, however, in the same field of endeavor, Valk teaches, transmitted through a plurality of data link layers and a plurality of physical layers respectively corresponding to a plurality of ports managed by one transaction layer (see Valk fig. 1D teaching, a single transport layer entity is coupled to a number of link layer and physical layer entities, [0030] "The TLs 122 provide reliable transport of packets, including recovering from [ .. ] broken links 106, 108 in the path between source and destination", [0030] "the interface switch 120 connects the 7 TLs 122 and the 26 iLinks 124 in a crossbar switch", [30] "The iLink layer protocol 124 handles link level flow control, error checking CRC generating and checking", see also Valk [9]-[10], teaching segmentation and buffering of packets).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Pandey to include the features as taught by Valk above in order to provide an effective method and circuit to implement end-to-end credit management in an interconnect system for enhanced large packet reassembly (Valk [0006]).
With respect to claim 20, claim recites the identical features of claim 1 for a corresponding method. Therefore, it is subjected to the same rejection.
Regarding claim 2, Pandey, in view of Valk, teaches the network controller, as outlined in the rejection of claim 1.
Pandey further teaches, wherein the error information comprises at least one of: a link training and status state machine (LTSSM) indicating a status of a link for each of the plurality of physical layers; an error message generated by an error of the one packet in the plurality of data link layers (Pandey [53] “If any fault is detected in any one lane of the number of communication lanes 108, the logic 206 immediately communicates the lane failure to each of the communication interface 110 and the other communication interface 112 by use of the “common message” of the OAM message”, teaches OAM message (i.e., error message). Satisfies “or” criteria of the claim); or transaction layer packet (TLP) information transmitted through the one transaction layer.
Regarding claim 7, Pandey, in view of Valk, teaches the network controller, as outlined in the rejection of claim 1.
Pandey further teaches, wherein the split circuit is configured to split the one packet for the valid ports into packets based on at least one of whether the one packet comprises a payload or a register set value of the one packet (see Pandey [0046] teaching, splitting a data frame i.e., a payload).
Regarding claim 10, Pandey, in view of Valk, teaches the network controller, as outlined in the rejection of claim 7.
Pandey further teaches, wherein the split circuit is configured to transmit the one packet to the valid ports by splitting the one packet into packets (see Pandey [0046] for splitting the one packet to valid ports. Satisfies “or” criteria of the claim), or configured to transmit the one packet to the valid ports by interleaving the one packet in a round-robin manner based on at least one of a processing capacity of the valid ports or the register set value of the one packet in response to the one packet comprising the payload.
Regarding claim 14, Pandey, in view of Valk, teaches the network controller, as outlined in the rejection of claim 1.
Pandey further teaches, wherein the reorder buffer is configured to sort the order of the second split packets using a prefix of the second split packets (see Valk [10] “restores order of the received packets using ETE sequence numbers”).
Regarding claim 15, Pandey, in view of Valk, teaches the network controller, as outlined in the rejection of claim 1.
Valk further teaches, wherein the reorder buffer is configured to increase a first counter value as the second split packets are received from the other network controller and configured to allocate the received second split packets to a way buffer according to whether the increased first counter value matches a tag value of split packets to be currently processed (see Valk [10] implying the feature of the claim).
Regarding claim 16, Pandey, in view of Valk, teaches the network controller, as outlined in the rejection of claim 15.
Valk further teaches, wherein the reorder buffer is configured to restore the second split packets to the one packet by increasing and sorting a second counter value corresponding to a number of packets that arrive at a first counter in response to the increased first counter value not matching the tag value of the split packets to be currently processed (see Valk [10] implying the feature of the claim).
Regarding claim 17, Pandey, in view of Valk, teaches the network controller, as outlined in the rejection of claim 1.
Valk further teaches, further comprising: an aggregation circuit configured to restore the second split packets to the one packet by aggregating the second split packets based on a register set value of the second split packets (see Valk Fig. 5 and para [49] implying the feature of the claim).
Regarding claim 18, Pandey, in view of Valk, teaches the network controller, as outlined in the rejection of claim 17.
Valk further teaches, wherein the aggregation circuit is configured to aggregate headers of the second split packets into one header and configured to aggregate payloads of the second split packets into one payload (see Valk Fig. 5 and para [49] implying the feature of the claim).
Regarding claim 19, Pandey, in view of Valk, teaches the network controller, as outlined in the rejection of claim 17.
Valk further teaches, wherein the aggregation circuit is configured to: transmit the second split packets to the reorder buffer based on whether the second split packets comprise a payload; and determine whether to aggregate the second split packets based on the register set value of the second split packets (see Valk Fig. 5 and para [49] implying the feature of the claim).
Claims 3, 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Pandey, in view of Valk, as applied to the rejection of claim 1 above, and further in view of IDS reference JEON; Yong Tae US 20220382692 A1, hereinafter JEON.
Regarding claim 3, Pandey, in view of Valk, teaches the network controller, as outlined in the rejection of claim 2.
Pandey further teaches, wherein the port monitor circuit is configured to determine, [by the LTSSM], whether communication of a physical layer corresponding to each of the plurality of ports is possible and configured to disable an invalid port unusable among the plurality of ports based on a type of the error message transmitted through a port capable of performing communication through the physical layer (see Pandey [53] “stop sending (or receiving) the number of subframes 218 of the data frame 208 over the faulty lane. Moreover, the logic 206 is configured to shut down the gate and buffer corresponding to the faulty lane and maintains the communication between both ends of the communication link 106 through remaining communication lanes which are active at that time.”).
Pandey and Valk do not expressly teach, however, in the same field of endeavor, JEON teaches, by the LTSSM (JEON [41] “the recovery controller 122 may control the LTSSM module 130 to perform a link recovery operation with respect to the host 2000”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Pandey and Valk to include the features as taught by JEON above in order to be directed to a PCIe interface device having improved link recovery performance and an operating method thereof (JEON [0007]).
Regarding claim 4, Pandey, in view of Valk and JEON, teaches the network controller, as outlined in the rejection of claim 3.
Pandey and JEON further teach, wherein the port monitor circuit is configured to disable the invalid port (see Pandey [53] above about disabling invalid port), and then configured to train a link of the disabled invalid port (see JEON Figs. 3 and 4 teaching, recovery and Link training).
Regarding claim 6, Pandey, in view of Valk and JEON, teaches the network controller, as outlined in the rejection of claim 3.
Pandey further teaches, wherein, in response to the type of the error message indicating non-correctable errors, the port monitor circuit is configured to disable the invalid port or configured to request error handling from a root complex according to whether the non-correctable errors are fatal errors (see Pandey [53] and rejection of claim 3 above).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Pandey, in view of Valk and JEON, as applied to the rejection of claim 3 above, and further in view of Knapp; David J. US 20100188972 A1, hereinafter Knapp.
Regarding claim 5, Pandey, in view of Valk and JEON, teaches the network controller, as outlined in the rejection of claim 3.
Pandey and Valk and JEON do not expressly teach, however, in the same field of endeavor, Knapp teaches, wherein, in response to the type of the error message indicating correctable errors, the port monitor circuit is configured to count a number of the correctable errors and configured to disable the invalid port among the plurality of ports based on the number of the correctable errors (Knapp [0120] “If a link is intermittently faulty (i.e., producing coding or CRC errors), the receiving node can set some threshold of error rate and shut down the link if the threshold is exceeded. Shutting down the link means not forwarding a frame received on one port to the other port”.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Pandey and Valk and JEON to include the features as taught by Knapp above in order to provides a fault tolerant network capable of supporting the existing applications serviced (Knapp [0019]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Pandey, in view of Valk, as applied to the rejection of claim 1 above, and further in view of Numakura, Keiko et al US 20050025188 A1, hereinafter Numakura.
Regarding claim 8, Pandey, in view of Valk, teaches the network controller, as outlined in the rejection of claim 7.
Pandey and Valk do not expressly teach, however, in the same field of endeavor, Numakura teaches, wherein the split circuit is configured to broadcast the one packet to the valid ports or configured to transmit the one packet to the valid ports by interleaving the one packet in a round-robin manner according to the register set value of the one packet in response to the one packet not comprising the payload (Numakura [112] ”In Embodiment 1 set forth above, a mobile communication system is described wherein packets, […], are transmitted through a plurality of transport channels; however, in Embodiment 2, a single packet is divided into a plurality of packet segments, and then the same identification number is added to each packet segment so as to re-synthesize the packet segments into the single packet; “, suggests, packet can be sent without segmentation over multiple transport channels (i.e., in broadcast manner). Satisfies “or” criteria of the claim).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Pandey and Valk to include the features as taught by Numakura above in order to provide a method for selecting transfer quality depending on the importance of transmission data and to mobile terminals therefore (Numakura [0001]).
Conclusion
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/MAHBUBUL BAR CHOWDHURY/Primary Examiner, Art Unit 2475
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