DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive.
Applicant argues: The Office Action cites Zhang as teaching a DPU that provides a media stream comprising only image sections to the GPU. Applicant respectfully submits that Zhang cannot teach or suggest this limitation, because Zhang's DPU is not positioned to provide anything to the GPU. Zhang is directed to physical subpixel rendering for display, and its DPU (124) is a display processing unit located within the display (122) at the end of the processing pipeline. Zhang's pipeline proceeds from the CPU, to the GPU, to the frame buffer, and only then to the DPU and the display panel (Zhang, Figs. 1-2). Zhang's DPU receives already-rendered image frames from the GPU/frame buffer and converts them into analog signals that operate the physical pixels of the display panel (Zhang [0026]-[0027]). Zhang's DPU therefore receives data from the GPU and outputs to the display; it never provides image data to the GPU. This is the opposite of the dataflow required by claim 1, and Zhang neither discloses nor suggests any reconfiguration that would reverse it. Moreover, the passage cited for the DPU limitation does not describe the DPU at all. In rejecting claim 1, the Office Action maps the recited DPU limitation to Zhang [0016]. However, [0016] describes the CPU, not the DPU: "The CPU 102... receives input data... and provides the input data to the graphics subsystem 110 for rendering" (Zhang [0016]). This passage describes a CPU providing input to the graphics subsystem, which is a different component performing a different function than the claimed DPU that provides only image sections to the GPU. Accordingly, the cited disclosure does not teach a DPU that receives captured image data and provides a media stream of only image sections to the GPU, and the claimed limitation was not located in Zhang.
The Examiner respectfully disagrees. Claim 1 of instant application recites a data processing unit (DPU) without definition, and the Specification fails to define the scope of a DPU. Giving the term its broadest reasonable interpretation, any processor which processes data could be interpreted as a data processing unit. Prior art Zhang discloses a CPU performing all the functions of the claimed DPU in claim 1, and Zhang’s CPU is a processor that processes data. Therefore, the CPU of Zhang is interpreted as a data processing unit, which teaches the claimed features. In fact, the Specification of instant application explicitly discloses an embodiment that a CPU component can be used as the DPU element and to perform corresponding functions. See the Specification [0069] “Therefore, the at least one execution unit 408 may be a circuit of at least one processor 402 to be associated with a system for separating image sections from images in support of performing content layer processing of only image sections. The association may be such that the at least one execution unit 408 of at least one processor 402 can perform at least aspects of a GPU, aspects of a DPU, or aspects of a CPU.” [0070] “Further, at least one execution unit 408 may be a circuit of at least one processor 402 that may be a CPU, a DPU, or a GPU, as in FIGS. 1-3, to perform aspects of separating image sections from images in support of performing content layer processing of only image sections.”
Furthermore, prior art LIU discloses an image signal processor (ISP) which also teaches the claimed data processing unit. See the response to arguments below.
Applicant argues: To the extent the Office Action characterizes Liu's image signal processor (ISP) as corresponding to the claimed DPU, Applicant respectfully disagrees. Liu itself treats the ISP (410) and the DPU (414) as separate and distinct components performing different functions: the ISP performs frontend image-signal processing such as Bad Pixel Correction, lens-shading correction, and demosaicing on the image data (Liu [0032], [0083]), whereas the DPU (414) performs downstream scaling, blending, and composition of the final image for the display (Liu [0085]). Because Liu expressly distinguishes these two components, Liu's ISP cannot be relabeled as the claimed "DPU" without reading the recited DPU limitation out of the claim.
The Examiner respectfully disagrees. Liu’s implementation of DPU 414 does not prevent Liu’s ISP 410 being interpreted as another data processing unit in the system. The names given to the circuitry components may be different, but the scope of the claimed DPU is defined by its structure and/or functions, rather than its name (unless the name itself suggests/restricts some specific structures and/or functions). Liu’s ISP (410) is a processor which processes image data received from image sensors and provides processed image data to the GPU 412 (see Liu’s Fig. 4 and [0083]). Zhang’s CPU performs similar functions. The combined teachings of Zhang and Liu therefore teach all of the DPU functions in claim 1 and render the claimed DPU component obvious, even when Zhang and Liu give different names to the particular circuit components.
Applicant argues: Moreover, even setting the label aside, Liu's ISP does not perform the claimed function of providing "a media stream comprising only image sections from the images to the GPU." Liu's ISP processes and passes along image data to the GPU (Liu [0083]); it does not select and forward only image sections.
The Examiner respectfully disagrees. First, the Office Action relied on Zhang (not Liu) to teach the claimed “image sections”. One cannot attack references individually when the rejection is based on a combination of references. Applicant presented no arguments regarding Zhang’s teaching of “image sections”. Second, the claim and specification of instant application do not define the scope of “image sections”. Giving the term its broadest reasonable interpretation, Liu’s image data 406 and image data 408 can be interpreted as two “image sections”.
Applicant argues: Applicant further submits that the claimed arrangement is not a mere rearrangement of known components. The upstream position of the claimed DPU produces benefits that the downstream, display-side DPUs of Zhang and Liu cannot provide.
The Examiner notes that the claimed DPU is taught by Zhang’s CPU and Liu’s ISP. Zhang and Liu explicitly teach the CPU/ISP providing processed data to the GPU, and rearrangement is not needed.
Examiner further notes that the data processing unit (DPU) in claim 1 essentially refers to an electric circuit performing a few claimed functions, and there is no limitation involving the structure of the data processing unit. Zhang and Liu disclose electric circuits (i.e., Zhang’s CPU and Liu’s ISP) performing the required functions. Therefore, the combined teachings of Zhang and Liu teach the claimed feature or at least render it obvious. Although Zhang and Liu disclose some other circuit components also named DPU, those components are not relied upon by the Office Action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 10-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 20250014140 A1), in view of LIU (US 20250104379 A1).
Regarding Claim 1, Zhang discloses a system for distributed image processing comprising a graphics processing unit (GPU) (Fig. 1, 112) and a data processing unit (DPU) (Fig. 1, 102), wherein the DPU is to receive image data ([0016] “The CPU 102 (also referred to as a processor or a main processor) receives input data, which is image data intended for display on the display 122 in the form of video frames.”) and is to provide a media stream comprising only image sections ([0016] “…in the form of video frames…”) from the images to the GPU ([0016] “The CPU 102 performs initial processing on the input data and provides the input data to the graphics subsystem 110 for rendering.”), and wherein the GPU is to perform content layer processing for the image sections of the images ([0018] “The GPU 112 is a specialized processor configured to accelerate graphics rendering. The GPU 112 is configured to process many pieces of image data simultaneously, compose image frames, and convey the image frames to the display 122 via the frame buffer 116.”).
Zhang does not expressly disclose the input image data is associated with captured images.
However, in the same field of endeavor, LIU discloses the DPU is to receive image data associated with captured images ([0079] “For example, an image sensor 404 may capture image data 406 and image data 408….By processing image data 406 and image data 408 at ISP 410, GPU 412, and/or DPU 414 (rather than processing an image representing the field of view of image data 408 at the resolution of image data 406), system 400 may conserve power, bandwidth, and/or processing time.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the system of Zhang with the feature of receiving image data associated with captured images. Doing so could “process a captured image or video for certain effects”, as taught by LIU.
Regarding Claim 2, Zhang-LIU discloses the system of claim 1, further comprising: an image sensor to capture the images (LIU [0079] “an image sensor 404 may capture image data 406 and image data 408”); and a field programmable gate array (FPGA) to receive the images and to perform physical layer processing for the image to provide the image data for the DPU (LIU [0177] “The program code may be executed by a processor, which may include one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, an application specific integrated circuits (ASICs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuitry.”).
Regarding Claim 3, Zhang-LIU discloses the system of claim 2, wherein the physical layer processing comprises processing associated with symbols or floating point representation of the images (LIU [0032] “For example, the frontend portion may perform one or more operations related to Bad Pixel Correction (BPC), lens correction, lens-shading correction, phase-detection pixel correction, demosaicing, lateral chromatic aberration correction, Bayer filtering, adaptive Bayer filtering, tone mapping, noise reduction, etc.” Examiner notes the “tone mapping” teaches or implies converting floating point image data to integer data. For example, see Roever (US 20220392414 A1) [0034] “…such as tone-mapping where floating point data is converted to integer data…”), and wherein the content layer processing comprises processing associated with pixels or metadata representation of the images (LIU [0129] “FIG. 10 is an illustrative example of a neural network 1000 (e.g., a deep-learning neural network) that can be used to implement machine-learning based feature segmentation, implicit-neural-representation generation, rendering, classification, object detection, image recognition (e.g., face recognition, object recognition, scene recognition, etc.), feature extraction, authentication, gaze detection, gaze prediction, and/or automation.”).
Regarding Claim 4, Zhang-LIU discloses the system of claim 2, wherein the physical layer processing comprises one or more of channel equalization, analog-to-digital conversion (ADC), noise estimation, error correction, or timestamping (LIU [0032] “For example, the frontend portion may perform one or more operations related to Bad Pixel Correction (BPC), lens correction, lens-shading correction, phase-detection pixel correction, demosaicing, lateral chromatic aberration correction, Bayer filtering, adaptive Bayer filtering, tone mapping, noise reduction, etc.”), and wherein the content layer processing comprises one or more of pattern recognition, object recognition, feature extraction, feature characterization, or image segmentation (LIU [0129] “FIG. 10 is an illustrative example of a neural network 1000 (e.g., a deep-learning neural network) that can be used to implement machine-learning based feature segmentation, implicit-neural-representation generation, rendering, classification, object detection, image recognition (e.g., face recognition, object recognition, scene recognition, etc.), feature extraction, authentication, gaze detection, gaze prediction, and/or automation.”).
Regarding Claim 5, Zhang-LIU discloses the system of claim 2, wherein the physical layer processing comprises one or more operations which are oblivious to content of the images or which are performed only considering raw pixel data associated with the images (LIU [0032] “The image-capture device (or portion) may stream raw image data to the frontend portion of the image-processing device (or portion). The frontend portion may perform one or more operations on the raw image data (e.g., as the raw image data is received).”).
Regarding Claim 6, Zhang-LIU discloses the system of claim 2, wherein the content layer processing comprises one or more operations which are to consider a content of the images or which are performed on raw pixel data with respect to content within the images (LIU [0129] “FIG. 10 is an illustrative example of a neural network 1000 (e.g., a deep-learning neural network) that can be used to implement machine-learning based feature segmentation, implicit-neural-representation generation, rendering, classification, object detection, image recognition (e.g., face recognition, object recognition, scene recognition, etc.), feature extraction, authentication, gaze detection, gaze prediction, and/or automation.”).
Regarding Claim 7, Zhang-LIU discloses the system of claim 2, wherein the physical layer processing is independent or agnostic of an application requirement (LIU [0076] “For example, in some implementations, the components of the image-processing system 300 can include and/or can be implemented using electronic circuits or other electronic hardware, which can include one or more programmable electronic circuits (e.g., microprocessors, GPUs, DSPs, CPUs, and/or other suitable electronic circuits), and/or can include and/or be implemented using computer software, firmware, or any combination thereof, to perform the various operations described herein.” Examiner notes that at least the firmware implementation is independent of an application requirement.).
Regarding Claim 8, Zhang-LIU discloses the system of claim 1, further comprising a GPU kernel (Zhang [0042] “A binning module 202 of a GPU 112”) to interface with the DPU to indicate only the image sections to be received for the content layer processing in the GPU (Zhang [0043] “In some implementations, the binning module 202 obtains the physical subpixel information (including the pixel layout corresponding to the display architecture of the display) as part of the method 600.”).
Regarding Claim 10, Zhang-LIU discloses the system of claim 1, wherein the DPU is further to provide only the image sections for local access by the GPU (Zhang [0043] “In other implementations, the physical subpixel information (including the pixel layout corresponding to the display architecture of the display) is stored locally at the graphics subsystem 110 prior to the method 600 being executed. In such implementations, the binning module 202 has access to the physical subpixel information when method 600 begins.”).
Regarding Claim 11, it recites similar limitations of claim 1. The rationale of claim 1 rejection is applied to reject claim 11.
Regarding Claim 12, it recites similar limitations of claim 2. The rationale of claim 2 rejection is applied to reject claim 12.
Regarding Claim 13, it recites similar limitations of claim 3. The rationale of claim 3 rejection is applied to reject claim 13.
Regarding Claim 14, it recites similar limitations of claim 4. The rationale of claim 4 rejection is applied to reject claim 14.
Regarding Claim 15, it recites similar limitations of claim 5 and claim 6. See rejections to claims 5 and 6 above, for detailed mappings.
Regarding Claim 16, it recites similar limitations of claim 1. The rationale of claim 1 rejection is applied to reject claim 16.
Regarding Claim 17, it recites similar limitations of claim 2. The rationale of claim 2 rejection is applied to reject claim 17.
Regarding Claim 18, it recites similar limitations of claim 3. The rationale of claim 3 rejection is applied to reject claim 18.
Regarding Claim 19, it recites similar limitations of claim 4. The rationale of claim 4 rejection is applied to reject claim 19.
Regarding Claim 20, it recites similar limitations of claim 5 and claim 6. See rejections to claims 5 and 6 above, for detailed mappings.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 20250014140 A1), in view of LIU (US 20250104379 A1), further in view of Roever (US 20220392414 A1).
Regarding Claim 9, Zhang-LIU discloses the system of claim 1. In the same field of endeavor, Roever discloses wherein the GPU is further to communicate with the DPU using a peripheral component interconnect express (PCIe) bus ([0046] “The interconnect system 602 may include one or more bus or link types, such as an industry standard architecture (ISA) bus, an extended industry standard architecture (EISA) bus, a video electronics standards association (VESA) bus, a peripheral component interconnect (PCI) bus, a peripheral component interconnect express (PCIe) bus, and/or another type of bus or link.”) to receive only the image sections and wherein the GPU is further to perform the content layer processing absent of intervention by a central processing unit (CPU) ([0020] “The GPU(s) 106— and/or other processing unit type(s)—may execute a 3D engine 108, a frame buffer 110, a display interface 114A, and/or a frame analyzer 112A.” [0026] “In some embodiments, the frame analysis may be executed using the GPU(s) 106— and/or other processing unit types—in parallel with existing post-processing steps (e.g., tone mapping, such that no or minimal additional delay is introduced by frame analysis (other than the transmission delay of transmitting the peak pixel value data) as compared to existing systems.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the system of Zhang-LIU with the features of connecting the GPU with the DPU using a PCIe bus and performing the content processing by the GPU absent of intervention by a CPU. Doing so could process the data in parallel and improve the efficiency as taught by Roever.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHONG WU whose telephone number is (571)270-5207. The examiner can normally be reached MON-FRI: 9AM-5PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Xiao Wu can be reached at 571-272-7761. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHONG WU/Primary Examiner, Art Unit 2613
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