DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Application Status
This office action is responsive to the amendments filed on 06/15/2026.
Claims 1-23 are pending and presented for examination.
The previous 35 USC 112 rejection has been withdrawn in view of the Applicant’s amendments.
This action has been made FINAL.
Response to Arguments
The Applicant alleged the following: “The cited combination fails to disclose one or more limitations "to provide sequence numbers for the payload to represent only image sections of the images, and to provide only the image sections in a shared buffer for access by a graphics processing unit (GPU) to enable the GPU to process the payload representing only the image sections using the sequence numbers," as in claim 1.” The examiner is not persuaded. Because "applicants may amend claims to narrow their scope, a broad construction during prosecution creates no unfairness to the applicant or patentee." In re ICON Health and Fitness, Inc., 496 F.3d 1374, 1379 (Fed. Cir. 2007) (citing In re Am. Acad. of Sci. Tech Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004)). The combination of Liu and Martel discloses provide sequence numbers in Paragraphs 0013; 0015-0016 of Martel. Liu discloses for the payload to represent only image sections of the images in Paragraphs 0105-0108 of Liu. Martell goes on to disclose provide only the image sections in a shared buffer in Paragraphs 0013; 0015-0016; 0043; 0048. Liu goes on to disclose for access by a graphics processing unit (GPU) to enable the GPU to process the payload in Paragraphs 0105-0108 of Liu. Martel discloses representing only the image sections using the sequence numbers in Paragraphs 0013; 0015-0016. Moreover, Martell’s Paragraph 0015 recites “a single shared media stream (i.e. images) buffer having at least a pair of separate memory banks according to the determined sequence number indexes.” MPEP § 2106 states Office personnel are to give claims their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023, 1027-28 (Fed Cir. 1997).
Regarding the arguments related to “obviousness,” the Applicant’s response is merely a citation of case law and fails to provide any explanation of how it is relevant to the examiner’s rejection. MPEP 710.01 discusses applicant responses that fail to point out the examiner’s supposed errors and therefore do not comply with 37 CFR 1.111(b). Accordingly, the examiner maintains the rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-23 are rejected under 35 U.S.C. 103 as being unpatentable over Liu, US 20250104379 in view of Martel, US 20180070126.
Claim 1:
Liu discloses a system (See Liu Abstract & Summary of the Invention) but failed to disclose sequence numbers. Martel discloses this feature in paragraphs 0013; 0015-0016. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have further modified Liu by the teachings of Martel to enable improved management of media streams, more effectively (See Martel Abstract).
As modified:
The combination of Liu and Martel discloses the following:
a data processing unit (DPU) to (See Liu Figure 4 Paragraphs 0079; 0084-0085);
receive image data associated with captured images (See Liu Figure 4; Paragraphs 0079; 0084-0085) of at least one media stream (See Liu Paragraphs 0032; 0062; 0164), the image data comprising payload and headers (See Liu Paragraphs 0105-0108), the DPU (See Liu Figure 4 Paragraphs 0079; 0084-0085) further to
separate the headers from the payload (See Liu Paragraphs 0105-0108), to provide sequence numbers (See Martel Paragraphs 0013; 0015-0016) for the payload (See Liu Paragraphs 0105-0108) to represent only image sections of the images (See Liu Paragraphs 0105-0108), and to
provide only the image sections in a shared buffer (See Martell Paragraphs 0013; 0015-0016; 0043; 0048) for access by a graphics processing unit (GPU) to enable the GPU to process the payload (See Liu Paragraphs 0105-0108) representing only the image sections using the sequence numbers (See Martel Paragraphs 0013; 0015-00161).
Claim 2:
The combination of Liu and Martel discloses an image sensor to capture the images (See Liu Paragraph 0029); and a field programmable gate array (FPGA) (See Liu Paragraph 0177) to receive the images (See Liu Paragraphs 0105-0108) and to provide the image data as concurrent media streams of the at least one media stream (See Liu Paragraph 0032; 0062; 0164).
Claim 3:
The combination of Liu and Martel discloses wherein the DPU (See Liu Figure 4 Paragraphs 0079; 0084-0085) is further to store the headers for the payload (See Liu Paragraphs 0105-0108) of a first one of the concurrent media stream (See Liu Paragraphs 0032; 0062; 0164) and additional headers for additional payload (See Liu Paragraphs 0105-0108) of a second one of the concurrent media streams (See Liu Paragraphs 0032; 0062; 0164) in different ones of a plurality of buffers that are distinct from the shared buffer (See Martell Paragraphs 0013; 0015-0016; 0043; 0048), wherein the DPU (See Liu Figure 4 Paragraphs 0079; 0084-0085) is further to arrange the payload and the additional payload (See Liu Paragraphs 0105-0108), belonging to the image sections and to additional image sections of the images (See Liu Paragraphs 0105-0108), in contiguous ones of designated locations of the shared buffer (See Martell Paragraphs 0013; 0015-0016; 0043; 0048), and wherein the arrangement of the payload and the additional payload (See Liu Paragraphs 0105-0108) enables the GPU (See Liu Paragraphs 0083-0085) to stitch the image sections and the additional image sections (See Liu Figure 4 Paragraphs 0079; 0084-0085) together for use by at least one application (See Liu Paragraph 0044; 0050) or for further processing by the GPU (See Liu Paragraphs 0083-0085).
Claim 4:
The combination of Liu and Martel discloses wherein the shared buffer (See Martell Paragraphs 0013; 0015-0016; 0043; 0048) is local to the GPU (See Liu Paragraphs 0083-0085) and wherein the plurality of buffers (See Martell Paragraphs 0013; 0015-0016; 0043; 0048) are local to a central processing unit (CPU) (See Liu Paragraph 0051) of a host machine (See Liu Paragraph 0071) or the DPU (See Liu Figure 4 Paragraphs 0079; 0084-0085).
Claim 5:
The combination of Liu and Martel discloses wherein the shared buffer (See Martell Paragraphs 0013; 0015-0016; 0043; 0048) is on a GPU (See Liu Paragraphs 0083-0085) card which comprises the GPU (See Liu Paragraphs 0083-0085) and wherein the plurality of buffers are in the host machine (See Liu Paragraph 0071) or the DPU (See Liu Figure 4 Paragraphs 0079; 0084-0085).
Claim 6:
The combination of Liu and Martel discloses wherein the shared buffer (See Martell Paragraphs 0013; 0015-0016; 0043; 0048) is on an accelerator card or a converged card (See Liu Paragraph 0055) which comprises the GPU (See Liu Paragraphs 0083-0085) and the DPU (See Liu Figure 4 Paragraphs 0079; 0084-0085) and wherein the plurality of buffers (See Martell Paragraphs 0013; 0015-0016; 0043; 0048) are in the host machine (See Liu Paragraph 0071) or the DPU (See Liu Figure 4 Paragraphs 0079; 0084-0085).
Claim 7:
The combination of Liu and Martel discloses wherein the DPU (See Liu Figure 4 Paragraphs 0079; 0084-0085) is further to discard other payload (See Liu Paragraphs 0105-0108) that are other than the image sections following the arrangement of the payload (See Liu Paragraphs 0105-0108) representing only the image sections for the GPU (See Liu Paragraphs 0083-0085).
Claim 8:
The combination of Liu and Martel discloses wherein the image sensor (See Liu Paragraph 0029) comprises a multi-array sensor (See Liu Paragraph 0029), and wherein different sensors (See Liu Paragraph 0029) of the multi-array sensor (See Liu Paragraph 0029) provide different and concurrent media streams of the at least one media stream (See Liu Paragraphs 0032; 0062; 0164).
Claim 9:
The combination of Liu and Martel discloses wherein the image sensor (See Liu Paragraph 0029) is further to communicate concurrent media streams (See Liu Paragraphs 0032; 0062; 0164) of the at least one media stream (See Liu Paragraphs 0032; 0062; 0164) to the FPGA (See Liu Paragraph 0177), and wherein the concurrent media streams (See Liu Paragraphs 0032; 0062; 0164) are associated with different User Datagram Protocol (UDP) ports of the FPGA (See Liu Paragraph 0177).
Claim 10:
The combination of Liu and Martel discloses wherein the at least one media stream includes two media streams (See Liu Paragraphs 0032; 0062; 0164), wherein the headers (See Liu Paragraphs 0105-0108) are associated with a first one of the two media streams (See Liu Paragraphs 0032; 0062; 0164) and are provided in a first buffer (See Martell Paragraphs 0013; 0015-0016; 0043; 0048) for access by a host machine (See Liu Paragraph 0071) comprising a central processing unit (CPU) (See Liu Paragraph 0051), wherein additional headers (See Liu Paragraphs 0105-0108) are associated with a second one of the two media streams (See Liu Paragraphs 0032; 0062; 0164), and wherein the additional headers (See Liu Paragraphs 0105-0108) are provided for in a second buffer for separate access (See Martell Paragraphs 0013; 0015-0016; 0043; 0048), relative to the headers (See Liu Paragraphs 0105-0108) associated with the first one of the two media streams (See Liu Paragraphs 0032; 0062; 0164), by the host machine (See Liu Paragraph 0071).
Claim 11:
The combination of Liu and Martel discloses wherein the CPU (See Liu Paragraph 0051) or the GPU (See Liu Paragraphs 0083-0085) is to use information from an application (See Liu Paragraph 0044; 0050) to inform the DPU (See Liu Figure 4 Paragraphs 0079; 0084-0085) of the payload (See Liu Paragraphs 0105-0108) representing only the image sections of the images (See Liu Paragraphs 0105-0108) to be provided by the DPU (See Liu Figure 4 Paragraphs 0079; 0084-0085) to the GPU (See Liu Paragraphs 0083-0085).
Claim 12:
The combination of Liu and Martel discloses wherein the at least one media stream includes two media streams (See Liu Paragraphs 0032; 0062; 0164), wherein the payload (See Liu Paragraphs 0105-0108) are associated with a first one of the two media streams (See Liu Paragraphs 0032; 0062; 0164), representing only the image sections of the first one of the two media streams (See Liu Paragraphs 0032; 0062; 0164), and are provided in the shared buffer (See Martell Paragraphs 0013; 0015-0016; 0043; 0048) for access by the GPU (See Liu Paragraphs 0083-0085), and wherein additional payload (See Liu Paragraphs 0105-0108) are associated with a second one of the two media streams (See Liu Paragraphs 0032; 0062; 0164), representing only additional image sections of the second one of the two media streams (See Liu Paragraphs 0032; 0062; 0164), and are provided in the shared buffer (See Martell Paragraphs 0013; 0015-0016; 0043; 0048) or a different buffer for contiguous access (See Martell Paragraphs 0013; 0015-0016; 0043; 0048), with the payload (See Liu Paragraphs 0105-0108) associated with the first one of the two media streams (See Liu Paragraphs 0032; 0062; 0164), by the GPU (See Liu Paragraphs 0083-0085).
Claim 13:
The combination of Liu and Martel discloses a central processing unit (CPU) (See Liu Paragraph 0051) of a host machine (See Liu Paragraph 0071), the CPU to use information from an application (See Liu Paragraph 0044; 0050) to cause the GPU (See Liu Paragraphs 0083-0085) to process the payload (See Liu Paragraphs 0105-0108) representing only the image sections of the images (See Liu Paragraphs 0105-0108).
Claim 14:
The combination of Liu and Martel discloses wherein the headers (See Liu Paragraphs 0105-0108) are received for local access using a central processing unit (CPU) of a host machine (See Liu Paragraphs 0051; 0071), wherein the CPU enables the DPU (See Liu Figure 4 Paragraphs 0079; 0084-0085) to provide the payload (See Liu Paragraphs 0105-0108) representing only the image sections for local access by the GPU (See Liu Paragraphs 0083-0085), and wherein the CPU enables the GPU (See Liu Paragraphs 0083-0085) to process the payload (See Liu Paragraphs 0105-0108) representing only the image sections based in part on the sequence numbers (See Martel Paragraphs 0013; 0015-0016).
Claim 15:
The combination of Liu and Martel discloses wherein the DPU (See Liu Figure 4 Paragraphs 0079; 0084-0085) is to control provision of the payload (See Liu Paragraphs 0105-0108) over a stream bit rate and burst size (See Liu Paragraphs 0105; 0164) which are associated with predictable workloads at a known consumption rate for the GPU (See Liu Paragraphs 0083-0085).
Claim 16:
Liu discloses a plurality of circuits (See Liu Abstract & Summary of the Invention) but failed to disclose sequence numbers. Martel discloses this feature in paragraphs 0013; 0015-0016. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have further modified Liu by the teachings of Martel to enable improved management of media streams, more effectively (See Martel Abstract).
As modified:
The combination of Liu and Martel discloses the following:
at least a data processing unit (DPU) (See Liu Figure 4; Paragraphs 0079; 0084-0085) to
receive image data associated with captured images (See Liu Figure 4; Paragraphs 0079; 0084-0085) of at least one media stream (See Liu Paragraphs 0032; 0062; 0164), the image data comprising payload and headers (See Liu Paragraphs 0105-0108),
the DPU (See Liu Figure 4; Paragraphs 0079; 0084-0085) further to separate the headers from the payload (See Liu Paragraphs 0105-0108),
to provide sequence numbers (See Martel Paragraphs 0013; 0015-0016) for the payload (See Liu Paragraphs 0105-0108) to represent only image sections of the images (See Liu Figure 4; Paragraphs 0079; 0084-0085),
and to provide only the image sections in a shared buffer (See Martell Paragraph 0013) for access by a graphics processing unit (GPU) to enable the GPU (See Liu Paragraphs 0083-0085) to process the payload (See Liu Paragraphs 0105-0108) representing only the image sections (See Liu Figure 4; Paragraphs 0079; 0084-0085) using the sequence numbers (See Martel Paragraphs 0013; 0015-00162).
Claim 17:
The combination of Liu and Martel discloses an image sensor (See Liu Paragraph 0029) to capture the images (See Liu Paragraphs 0105-0108), the image sensor (See Liu Paragraph 0029) comprising a multi-array sensor (See Liu Paragraph 0029), wherein different sensors of the multi-array sensor (See Liu Paragraph 0029) provide different and concurrent media streams of the at least one media stream (See Liu Paragraphs 0032; 0062; 0164); and a field programmable gate array (FPGA) (See Liu Paragraph 0177) to receive the images (See Liu Paragraphs 0105-0108) and to provide the image data as the different and concurrent media streams of the at least one media stream (See Liu Paragraphs 0032; 0062; 0164).
Claim 18:
The combination of Liu and Martel discloses wherein the shared buffer (See Martell Paragraphs 0013; 0015-0016; 0043; 0048) is one of: local to the GPU (See Liu Paragraphs 0083-0085), on a GPU card which comprises the GPU (See Liu Paragraphs 0083-0085), or on an accelerator card or a converged card (See Liu Paragraph 0055) which comprises the GPU and the DPU (See Liu Figure 4 Paragraphs 0079; 0084-0085).
Claim 19:
The combination of Liu and Martel discloses wherein the headers (See Liu Paragraphs 0105-0108) are to be stored in a first one of a plurality of buffers (See Martell Paragraphs 0013; 0015-0016; 0043; 0048), wherein the plurality of buffers are distinct from the shared buffers (See Martell Paragraphs 0013; 0015-0016; 0043; 0048) and are local to a central processing unit (CPU) of a host machine (See Liu Paragraphs 0051; 0071) or the DPU (See Liu Figure 4 Paragraphs 0079; 0084-0085) or are in the host machine (See Liu Paragraph 0071) or the DPU (See Liu Figure 4 Paragraphs 0079; 0084-0085), wherein the headers are for the payload (See Liu Paragraphs 0105-0108) of a first one of concurrent media streams of the at least one media stream (See Liu Paragraphs 0032; 0062; 0164), and wherein additional headers for additional payload (See Liu Paragraphs 0105-0108) of a second one of the concurrent media streams (See Liu Paragraphs 0032; 0062; 0164) are in second one of a plurality of buffers (See Martell Paragraphs 0013; 0015-0016; 0043; 0048).
Claim 20:
Liu discloses a method for image processing (See Liu Abstract & Summary of the Invention) but failed to disclose sequence numbers. Martel discloses this feature in paragraphs 0013; 0015-0016. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have further modified Liu by the teachings of Martel to enable improved management of media streams, more effectively (See Martel Abstract).
As modified:
The combination of Liu and Martel discloses the following:
receiving, in a data processing unit (DPU) image data (See Liu Figure 4; Paragraphs 0079; 0084-0085) associated with captured images of at least one media stream (See Liu Paragraphs 0032; 0062; 0164), the image data comprising payload and headers (See Liu Paragraphs 0105-0108),
separating, by the DPU (See Liu Figure 4; Paragraphs 0079; 0084-0085), the headers from the payload (See Liu Paragraphs 0105-0108);
providing sequence numbers (See Martel Paragraphs 0013; 0015-0016) for the payload to represent only image sections of the images (See Liu Paragraphs 0105-0108);
and providing only the image sections in a shared buffer (See Martell Paragraph 0013) for access by a graphics processing unit (GPU) to enable the GPU (See Liu Paragraphs 0083-0085) to process the payload (See Liu Paragraphs 0105-0108) representing only the image sections using the sequence numbers (See Martel Paragraphs 0013; 0015-00163).
Claim 21:
The combination of Liu and Martel discloses capturing the images (See Liu Paragraphs 0105-0108) using an image sensor (See Liu Paragraph 0029), the image sensor (See Liu Paragraph 0029) comprising a multi-array sensor (See Liu Paragraph 0029), and wherein different sensors of the multi-array sensor (See Liu Paragraph 0029) provide different and concurrent media streams of the at least one media stream (See Liu Paragraphs 0032; 0062; 0164); receiving the images (See Liu Paragraphs 0105-0108) in a field programmable gate array (FPGA) (See Liu Paragraph 0177); and providing, from the FPGA (See Liu Paragraph 0177), the image data as the different and concurrent media streams of the at least one media stream (See Liu Paragraphs 0032; 0062; 0164).
Claim 22:
The combination of Liu and Martel discloses wherein the shared buffer (See Martell Paragraphs 0013; 0015-0016; 0043; 0048) is one of: local to the GPU (See Liu Paragraphs 0083-0085), on a GPU card which comprises the GPU (See Liu Paragraphs 0083-0085), or on an accelerator card or a converged card (See Liu Paragraph 0055) which comprises the GPU and the DPU (See Liu Figure 4 Paragraphs 0079; 0084-0085).
Claim 23:
The combination of Liu and Martel discloses storing, by the DPU (See Liu Figure 4 Paragraphs 0079; 0084-0085), the headers for the payload (See Liu Paragraphs 0105-0108) of a first one of the concurrent media stream (See Liu Paragraphs 0032; 0062; 0164) and additional headers for additional payload (See Liu Paragraphs 0105-0108) of a second one of the concurrent media streams (See Liu Paragraphs 0032; 0062; 0164) in different ones of a plurality of buffers (See Martell Paragraphs 0013; 0015-0016; 0043; 0048) that are distinct from the shared buffer (See Martell Paragraphs 0013; 0015-0016; 0043; 0048); arranging, by the DPU (See Liu Figure 4 Paragraphs 0079; 0084-0085) the payload and the additional payload (See Liu Paragraphs 0105-0108), belonging to the image sections and to additional image sections of the images (See Liu Paragraphs 0105-0108), in contiguous ones of designated locations of the shared buffer (See Martell Paragraphs 0013; 0015-0016; 0043; 0048); and enabling, using the arrangement of the payload and the additional payload (See Liu Paragraphs 0105-0108), the GPU (See Liu Paragraphs 0083-0085) to stitch the image sections and the additional image sections (See Liu Figure 4 & Paragraphs 0079; 0084-0085) together for use by at least one application (See Liu Paragraph 0044; 0050) or for further processing by the GPU (See Liu Paragraphs 0083-0085).
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20140139513 relates generally to methods and apparatus for enhanced processing of 3D graphics data.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEREE N BROWN whose telephone number is (571)272-4229. The examiner can normally be reached M-F 5:30-2:00 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, SAID BROOME can be reached at (571) 272-2931. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHEREE N BROWN/Primary Examiner, Art Unit 2612 August 3, 2026
1 Martell’s Paragraph 0015 recites “a single shared media stream buffer having at least a pair of separate memory banks according to the determined sequence number indexes.”
2 Martell’s Paragraph 0015 recites “a single shared media stream buffer having at least a pair of separate memory banks according to the determined sequence number indexes.”
3 Martell’s Paragraph 0015 recites “a single shared media stream buffer having at least a pair of separate memory banks according to the determined sequence number indexes.”
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