DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim(s) 1-9, the claim feature or are dependent upon claims which feature the limitation “the active layer comprises two active layers”. The use of the same term “active layer” for both a part and its sub-parts makes it unclear whether later limitations reciting “the active layer” refer to the set of active layers or one or more of the “two active layers”. Further, it is unclear whether the “two active layers” inherit any limitations referring to “the active layer”, which would also raise an issue of recursion, where each of the “two active layers” would then comprise two active layers themselves. For the purpose of examination, the examiner interprets the instances of “the active layer” as referring only to the first recited active layer while any instances of “the two active layers” refers to the set of the “two active layers”. Additionally, the “two active layers” are interpreted as not necessarily inheriting limitations referring to “the active layer” or vice versa.
Regarding claim(s) 10-15, the claim feature or are dependent upon claims which feature the limitation “…the first portion covering the protrusion are equal to each other”. There is insufficient antecedent basis for this limitation in the claim. The first portion is not previously limited in such a way that it must cover the protrusion, as claimed, and a “first portion covering the protrusion” has not been previously recited. Additionally, it is unclear whether the “covering the protrusion” is a further limitation to “the first portion” or if it merely refers to a subset of “the first portion” which is “covering the protrusion”. For the purpose of examination, the examiner interprets the claim as reciting “a portion of the first portion , wherein the portion of the first portion is covering the protrusion”.
Regarding claim(s) 12-15, the claim feature or are dependent upon claims which feature the limitation “forming an inner region by removing the sacrificial layer and by exposing the second portion by the inner region”. It is unclear how “by” is used in “the second portion by the inner region” in this limitation. It may be interpreted as either indicating a positional relationship between the second portion and the inner region or as indicating that the inner region is what performs the “exposing the second portion”. Additionally, it is unclear how the inner region can take part in a limitation regarding the process of forming said inner region. How can “forming an inner region” be done “by” (in either interpretation) “the inner region”, when said inner region is yet to be formed. For the purpose of examination, the examiner interprets the claim as reciting “forming an inner region by removing the sacrificial layer and by exposing the second portion
Regarding claim(s) 16-20, the claim feature or are dependent upon claims which feature the limitation “a first highest level of the body portion is equal to a second highest level of the silicon layer covering the protrusion”. It is unclear if "second" is used merely to distinguish between this "highest level of the silicon layer…” and the previous "first highest level of the body portion" or to indicate that the level described is at a height of the silicon layer which comes second to the highest level of the silicon layer. For the purpose of examination, the examiner interprets the claim according to the former interpretation, where the terms “first” and “second” are used herein solely to distinguish between highest levels of different features rather than an indication of a relationship to other highest levels of the same feature.
Further regarding claim(s) 16-20, the claim feature or are dependent upon claims which feature the limitation “the silicon layer covering the protrusion”. There is insufficient antecedent basis for this limitation in the claim. The silicon layer is not previously limited in such a way that it must cover the protrusion, as claimed, and a “silicon layer covering the protrusion” has not been previously recited. Additionally, it is unclear whether the “covering the protrusion” is a further limitation to “the silicon layer” or if it merely refers to a subset of “the silicon layer” which is “covering the protrusion”. For the purpose of examination, the examiner interprets the claim as reciting “a portion of the silicon layer, wherein the portion of the silicon layer is covering the protrusion”.
Regarding claim(s) 17, the claim feature or are dependent upon claims which feature the limitation “a first thickness of the side insulating layer is equal to a second thickness of the silicon layer”. It is unclear if "second" is used merely to distinguish between this "thickness of the silicon layer…” and the previous "first thickness of the side insulating layer" or to indicate that the thickness described is a second of at least two thicknesses of the silicon layer. For the purpose of examination, the examiner interprets the claim according to the former interpretation, where the terms “first” and “second” are used herein solely to distinguish between thicknesses of different features rather than an indication of a relationship to other thicknesses of the same feature.
Regarding claim(s) 19, the claim feature or are dependent upon claims which feature the limitation “a first lowest level of the body portion is equal to a second lowest level of the silicon layer covering the protrusion”. It is unclear if "second" is used merely to distinguish between this "lowest level of the silicon layer…” and the previous "first lowest level of the body portion" or to indicate that the level described is at a level of the silicon layer which comes second to the lowest level of the silicon layer. For the purpose of examination, the examiner interprets the claim according to the former interpretation, where the terms “first” and “second” are used herein solely to distinguish between lowest levels of different features rather than an indication of a relationship to other lowest levels of the same feature.
Further regarding claim(s) 19, the claim feature or are dependent upon claims which feature the limitation “the silicon layer covering the protrusion”. There is insufficient antecedent basis for this limitation in the claim. The silicon layer is not previously limited in such a way that it must cover the protrusion, as claimed, and a “silicon layer covering the protrusion” has not been previously recited. Additionally, it is unclear whether the “covering the protrusion” is a further limitation to “the silicon layer” or if it merely refers to a subset of “the silicon layer” which is “covering the protrusion”. For the purpose of examination, the examiner interprets the claim as reciting “the portion of the silicon layer”, which has antecedent basis in the interpretation of 16, as described above.
Regarding claim(s) 20, the claim feature or are dependent upon claims which feature the limitation “the gate insulating layer comprises a first material different from a second material of the inner spacer”. It is unclear if "second" is used merely to distinguish between this "material of the inner spacer” and the previous "first material" of the gate insulating layer or to indicate that the material described is a second of at least two materials of the inner spacer. For the purpose of examination, the examiner interprets the claim according to the former interpretation, where the terms “first” and “second” are used herein solely to distinguish between materials of different features rather than an indication of a relationship to other materials of the same feature.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Chuang et al. (US 20230065208 A1, hereinafter C1).
Regarding independent claim 1, C1 discloses in C1 FIG. 2A-8 and associated text A method of manufacturing a semiconductor device, the method comprising: forming a stacked pattern (multi-layer stack 25) comprising an active layer (first semiconductor layers 21/nanostructures 22) and a sacrificial layer (second semiconductor layers 23/nanostructures 24) stacked on a substrate (25 is on substrate 110), wherein the active layer comprises two active layers vertically adjacent to each other (22 comprises nano structures 22A and 22B, which are vertically adjacent to each other), and the sacrificial layer is interposed between the two active layers (24 is between 22A and 22B); forming a recess by etching the stacked pattern (openings 550 formed by etching 22 and 24 (C1 [0053])); forming an indent by etching a portion of the sacrificial layer exposed by the recess (recesses 64 formed by etching portions of 24 which are exposed by 550 (C1 [0054])); forming a silicon layer on an inner surface of the recess (liner layer 78, which is silicon (C1 [0029]), is formed on surfaces in 64); forming an inner spacer in the indent (inner spacers 74 are in 64); forming an inner region by removing the sacrificial layer (24 is removed, exposing the second portion, as interpreted above; the region in which 24 was previously present are considered the inner region); and forming a gate insulating layer in the inner region (interfacial layer 210 is formed in the inner region, as interpreted above), wherein the forming the gate insulating layer comprises forming an oxide layer by performing an oxidation process on the silicon layer exposed by the inner region (210 is formed by oxidizing vertical portions of 78 (C1 [0070]), which are exposed by the inner region, as interpreted above, where the oxide layer is interpreted as said vertical portions of 78).
Regarding dependent claim 2, C1 further discloses in C1 FIG. 2A-8 and associated text The method of claim 1, wherein the oxide layer is in direct contact with the inner spacer (vertical portions of 78, which are interpreted as the oxide layer, as interpreted above, are in direct contact with 74).
Regarding dependent claim 3, C1 further discloses in C1 FIG. 2A-8 and associated text The method of claim 1, wherein the forming the silicon layer comprises performing an epitaxial growth process on the sacrificial layer and on semiconductor patterns exposed by the recess (78 is epitaxially grown on 22 and 24 exposed by 550 (C1 [0056])).
Regarding dependent claim 4, C1 further discloses in C1 FIG. 2A-8 and associated text The method of claim 1, further comprising forming a semiconductor pattern from the active layer (nanostructures 22 are interpreted as semiconductor patterns, and are formed from 21 (C1 [0042])), wherein the silicon layer comprises a first portion on the semiconductor pattern (portion of 78 on 22) and a second portion on the sacrificial layer (portion of 78 on 24), and wherein the oxidation process is selectively performed in the second portion through the inner region (the oxidation is of the exposed portion of 78 corresponding to the second portion, as interpreted above (C1 [0070])).
Regarding dependent claim 5, C1 further discloses in C1 FIG. 2A-8 and associated text The method of claim 4, further comprising: oxidizing a top surface and a bottom surface of the semiconductor pattern by the oxidation process (the oxidation process for forming 210 comprises oxidation of exposed surfaces of 22, which include top and bottom surfaces (C1 [0070])), and forming the gate insulating layer on the top surface and the bottom surface of the semiconductor pattern (210 is formed on said top and bottom surfaces).
Regarding dependent claim 6, C1 further discloses in C1 FIG. 2A-8 and associated text The method of claim 4, wherein a thickness of the semiconductor pattern in a vertical direction is reduced by the oxidation process (Oxidation processes bind oxygen to a material, which converts the material to an oxide in its place. In the instant case, the material of exposed surfaces of 22 is oxidized (C1 [0070]), after which, the oxide is considered to be part of 210 rather than 22, thereby reducing the thickness of 22 along the z-axis, which is considered the vertical direction).
Regarding dependent claim 7, C1 further discloses in C1 FIG. 2A-8 and associated text The method of claim 1, further comprising forming the inner spacer and forming a source/drain pattern in the recess (210 and source/drain features 82 are formed in 550).
Regarding dependent claim 8, C1 further discloses in C1 FIG. 2A-8 and associated text The method of claim 1, further comprising sequentially forming a high dielectric layer (gate dielectric layer 600 is a high-k dielectric material (C1 [0072])) and a gate electrode (metal fill layer 290) in the inner region (600 and 290 are formed sequentially within the inner region, as interpreted above (C1 [0071]-[0073])).
Regarding dependent claim 9, C1 further discloses in C1 FIG. 2A-8 and associated text The method of claim 1, wherein the forming the silicon layer comprises selectively growing silicon on the sacrificial layer exposed by the recess (Embodiments of the disclosure include a silicon liner (78), which may be selectively grown on the silicon nanosheets and SiGe surfaces (corresponding to “sacrificial layer” 23/24, which is Si Ge in an exemplary embodiment (C1 [0039])) after source/drain region SiGe recessing (C1 [0010])).
Regarding independent claim 10, C1 discloses in C1 FIG. 2A-8 and associated text A method of manufacturing a semiconductor device, the method comprising: forming a stacked pattern (multi-layer stack 25) comprising a semiconductor pattern (first semiconductor layers 21/nanostructures 22) and a sacrificial layer (second semiconductor layers 23/nanostructures 24) stacked on a substrate (25 is on substrate 110); forming a recess by etching the stacked pattern (openings 550 formed by etching 22 and 24 (C1 [0053])); forming an indent by etching a portion of the sacrificial layer exposed by the recess (recesses 64 formed by etching portions of 24 which are exposed by 550 (C1 [0054])); forming a silicon layer on an inner surface of the recess (liner layer 78, which is silicon (C1 [0029]), is formed on surfaces in 64), the silicon layer comprising a first portion on the semiconductor pattern (portion of 78 on 22) and a second portion on the sacrificial layer (portion of 78 on 24); forming an inner spacer in the indent (inner spacers 74 are in 64); and forming a source/drain pattern in the recess (source/drain features 82 are in 550), wherein the semiconductor pattern comprises a body portion (portion of 22 overlapping 24 along the z-axis in C1 FIG. 6E) and a protrusion protruding from the body portion toward the source/drain pattern (portions of 22 which protrude outward from sidewalls of 24 in C1 FIG. 6E), and wherein a highest level of the body portion and a highest level of a portion of the first portion are equal to each other, wherein the portion of the first portion is covering the protrusion (the highest level of the body portion of 22A and the highest level of 78 are equal, as shown in C1 FIG. 6G).
Regarding dependent claim 11, C1 further discloses in C1 FIG. 6F-6G and associated text The method of claim 10, wherein the forming the first portion comprises performing an epitaxial growth process on the protrusion (78 is epitaxially grown on exposed portions of 22 and 24 (C1 [0056]), which includes the protrusions, as interpreted above).
Regarding dependent claim 12, C1 further discloses in C1 FIG. 2A-8 and associated text The method of claim 10, further comprising: forming an inner region by removing the sacrificial layer and by exposing the second portion (24 is removed, exposing the second portion, as interpreted above; the region in which 24 was previously present are considered the inner region), and forming a gate insulating layer by performing an oxidation process on the exposed second portion (interfacial layer 210 is a gate insulating layer which is formed by oxidizing exposed surfaces of 78 corresponding to the second portion, as interpreted above (C1 [0070])).
Regarding dependent claim 13, C1 further discloses in C1 FIG. 2A-8 and associated text The method of claim 12, wherein the forming the gate insulating layer comprises performing the oxidation process on a top surface and a bottom surface of the semiconductor pattern exposed by the inner region (the oxidation process for forming 210 comprises oxidation of exposed surfaces of 22, which include top and bottom surfaces (C1 [0070])).
Regarding dependent claim 14, C1 further discloses in C1 FIG. 2A-8 and associated text The method of claim 12, further comprising sequentially forming a high dielectric layer (gate dielectric layer 600 is a high-k dielectric material (C1 [0072])) and a gate electrode (metal fill layer 290) in the inner region (600 and 290 are formed sequentially within the inner region, as interpreted above (C1 [0071]-[0073])).
Regarding dependent claim 15, C1 further discloses in C1 FIG. 2A-8 and associated text The method of claim 12, wherein a thickness of the semiconductor pattern in a vertical direction is reduced by the oxidation process (Oxidation processes bind oxygen to a material, which converts the material to an oxide in its place. In the instant case, the material of exposed surfaces of 22 is oxidized (C1 [0070]), after which, the oxide is considered to be part of 210 rather than 22, thereby reducing the thickness of 22 along the z-axis, which is considered the vertical direction).
Regarding independent claim 16, C1 discloses in C1 FIG. 1A-1F and 2A-8 and associated text A semiconductor device comprising: a substrate comprising an active pattern (substrate 110 comprises fins 32, which are interpreted as active patterns); a first semiconductor pattern and a second semiconductor pattern stacked on the active pattern and vertically spaced apart from each other (nanostructures 22A and 22B are stacked on 32 and vertically spaced apart from each other); a source/drain pattern connected to the first semiconductor pattern and the second semiconductor pattern (source/drain features 82 are connected to 22A and 22B); a silicon layer between the first semiconductor pattern and the source/drain pattern (liner layer 78, which is silicon (C1 [0029]), is between 22A and 82); a gate electrode between the first semiconductor pattern and the second semiconductor pattern (metal fill layer 290 is a gate electrode between 22A and 22B); a gate insulating layer between the gate electrode and the source/drain pattern (interfacial layer 210 is a gate insulating layer between 290 and 82); a high dielectric layer surrounding the gate electrode (gate dielectric layer 600 is a high-k dielectric material (C1 [0072]), which surrounds 290); and an inner spacer between the gate insulating layer and the source/drain pattern (inner spacer 74 is between 210 and 82), wherein the first semiconductor pattern comprises a body portion (portion of 22 overlapping 24 along the z-axis in C1 FIG. 6E) and a protrusion protruding from the body portion toward the source/drain pattern (portions of 22 which protrude outward from sidewalls of 24 in C1 FIG. 6E), and wherein a first highest level of the body portion is equal to a second highest level of a portion of the silicon layer, wherein the portion of the silicon layer is covering the protrusion (the highest level of the body portion of 22A and the highest level of the portion of 78 covering the protrusion are equal, as shown in C1 FIG. 6G).
Regarding dependent claim 17, C1 further discloses in C1 FIG. 1A-1F and 2A-8 and associated text The semiconductor device of claim 16, wherein the gate insulating layer comprises a side insulating layer interposed between the high dielectric layer and the inner spacer (portion of 210 between 600 and 74), and wherein a first thickness of the side insulating layer is equal to a second thickness of the silicon layer (210 has thickness of about 5 to 50 Angstroms (C1 [0020]), while 78 has thickness in a range of about 0.5 nm to 2 nm (C1 [0029]), which overlaps in the range of 5-20 Angstroms).
Regarding dependent claim 18, C1 further discloses in C1 FIG. 1A-1F and 2A-8 and associated text The semiconductor device of claim 16, wherein the gate insulating layer comprises a silicon oxide layer (210 may be silicon oxide (C1 [0070]), thus comprising a silicon oxide layer).
Regarding dependent claim 19, C1 further discloses in C1 FIG. 1A-1F and 2A-8 and associated text The semiconductor device of claim 16, wherein a first lowest level of the body portion is equal to a second lowest level of the portion of the silicon layer covering the protrusion (the lowest level of the body portion of 22A and the lowest level of the portion of 78 covering the protrusion are equal, as shown in C1 FIG. 6G).
Regarding dependent claim 20, C1 further discloses in C1 FIG. 1A-1F and 2A-8 and associated text The semiconductor device of claim 16, wherein the gate insulating layer comprises a first material different from a second material of the inner spacer (210 may be silicon oxide (C1 [0070]) while 74 may be SiOCN, SiON, SiN, or SiOC (C1 [0026])).
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US 20240006496 A1, pertaining to methods of forming inner spacers in a nanosheet transistor structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571) 272-9559. The examiner can normally be reached Mon - Thu 8:30 am - 6:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/EVERETT T RIRIE/Examiner, Art Unit 2897
