DETAILED ACTION
This action is responsive to the following communications: the Application filed July 29, 2024.
Claims 1-20 are pending. Claims 1, 11 and 18 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4 and 7-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over SON et al. (US 2022/0044758) in view of Ham et al. (US 12, 518,840).
Regarding independent claim 1, SON et al. disclose a memory system, comprising a memory and a memory controller (200, figure 1), wherein the memory controller is coupled with the memory (figure 1); and the memory controller is configured to: send an erase operation instruction to the memory (see Abstract discloses: A fail detecting method of a memory system including a nonvolatile memory device and a memory controller, the fail detecting method including: counting, by the memory controller, the number of erases of a word line connected to a pass transistor; issuing a first erase command, by the memory controller) , the erase operation instruction including information of a memory block having data to be erased in the memory; and the memory is configured to: in response to the erase operation instruction (see para.[0006] discloses: the plurality of word lines, a memory block that is included in the memory cell array; a voltage generator included in the peripheral region and configured to generate a plurality of voltages provided to the memory cell array and the pass transistor; and a control logic included in the peripheral region and configured to decrease, based on a first erase command, a gate-source potential difference of the pass transistor to detect a leakage current of a word line in the memory block, wherein the memory controller is configured to count the number of erases of the memory block, issue the first erase command when the number of erases reaches a reference value, and detect the leakage current).
However, SON et al. are silent with respect to set a dummy word line coupled with the memory block to a floating state when a bit line voltage or a source line voltage of the memory block rises to a first voltage, wherein the first voltage is related to an erase count of the memory block.
Ham et al. disclose set a dummy word line coupled with the memory block to a floating state (see para.(97) below) when a bit line voltage or a source line voltage of the memory block rises to a first voltage (see para.[45) below, also see figures 5 and 6), wherein the first voltage is related to an erase count of the memory block (see figure 7 below).
(97) Referring to FIG. 6, in the GIDL erase operation, the erase voltage Vers may be provided to the common source line CSL. During the step-up period, the first GIDL line GIDL1a, the ground selection line GSLa, and the dummy word line DWL may each be floated. Accordingly, holes (+) may not be generated at the lower end of the first string STR1, or only the small amount or number of holes may be generated at the lower end thereof. Also, because the dummy word line DWL is in the floating state during the step-up period, a potential difference may not occur between a junction region “d” of the common source line CSL and the vertical channel layer 12 and a vertical channel layer “e” adjacent to the dummy word line DWL, or a small potential difference may occur therebetween. Accordingly, the injection of the holes (+) of the junction region “d” into the vertical channel layer 12 may be blocked.
(45) The voltage generator 1160 may generate the erase voltage Vers and row line voltages Vrow that may be used in the erase operation. For example, the erase voltage Vers may be provided to the common source line and/or the bit line in the GIDL erase operation. In the GIDL erase operation, the row line voltages Vrow may be provided to row lines such as a word line, a dummy word line, a ground selection line, a string selection line, and a GIDL line. The voltage generator 1160 may generate the erase voltage Vers and the row line voltages Vrow in a step-up manner, for example, so as to stepwise increase to a target voltage.
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Since SON et al. and Ham et al. are both from the same field of endeavor, the purpose disclosed by Ham et al. would have been recognized in the pertinent art of SON et al.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of SON et al. to teaching of Ham et al. for purpose of using the control logic is configured to change a slope of the erase voltage and a floating time of a lease one row lime among the row lines depending on a program/erase cycle.
Regarding claim 2, SON et al. and Ham et al. disclose the limitation of claim 1.
wherein the memory is further configured to send erase information to the memory controller (see Abstract), the erase information indicating the erase count corresponding to the memory block (see para.[0006] discloses: wherein the memory controller is configured to count the number of erases of the memory block, issue the first erase command when the number of erases reaches a reference value, and detect the leakage current).
Regarding claim 3, the combination of SON et al. and Ham et al. disclose the limitation of claim 1.
Ham et al. further disclose wherein the memory controller is configured to: determine the first voltage based on the erase count; and send the erase operation instruction to the memory, the erase operation instruction further including information of the first voltage (see figures 7 and 31 below)
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Regarding claim 4, the combination of SON et al. and Ham et al. disclose the limitation of claim 1.
SON et al. further disclose wherein the first voltage is smaller when the erase count is larger (see figure 8 below. At T2: VERS1>VGS2).
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Regarding claim 7, the combination of SON et al. and Ham et al.
Ham et al. further disclose wherein the memory is further configured to, in response to the erase operation instruction, apply an erase voltage to a bit line coupled with the memory block or a source line coupled with the memory block (see rejection of claim 1), the erase voltage being greater than the first voltage (see figure 8 above).
Regarding claim 8, the combination of SON et al. and Ham et al. disclose the limitation of claim 1.
Ham et al. further disclose wherein the memory is further configured to, in response to the erase operation instruction, apply a second voltage (figure 20 below) to the dummy word line coupled with the memory block before the bit line voltage (see rejection of claim 1) or the source line voltage of the memory block rises to the first voltage (see figure 20 below).
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Regarding claim 9, the combination of SON et al. and Ham et al. disclose the limitation of claim 1.
Ham et al. further disclose wherein the memory is further configured to, in response to the erase operation instruction (figure 2), apply a second voltage to a word line coupled with the memory block (figure 20 above).
Regarding claim 10, Ham et al. disclose the limitation of claim 8.
Ham et al. further disclose wherein the second voltage (V2, figure 20) includes a ground voltage ((52) The address decoder 1130 may be connected with the memory cell array 1110 through row lines RLs. The row lines RLs may include string selection lines SSLs, ground selection lines GSLs, word lines WLs, dummy word lines DWLs, and GIDL lines GIDLs.).
Regarding claim 11. A memory, comprising a peripheral circuit and a memory array, wherein the peripheral circuit is coupled with the memory array, and the peripheral circuit is configured to: in response to an erase operation instruction, when a bit line voltage or a source line voltage of a memory block having data to be erased in the memory array rises to a first voltage, set a dummy word line coupled with a memory block to a floating state, wherein the first voltage is related to an erase count of the memory block (see rejection of claim 1).
Regarding claim 12. The memory of claim 11, wherein the first voltage is smaller when the erase count is larger (see rejection of claim 4).
Regarding claim 13. The memory of claim 11, wherein the peripheral circuit is further configured to: in response to the erase operation instruction, apply an erase voltage to a bit line coupled with the memory block or a source line coupled with the memory block, the erase voltage being greater than the first voltage (see rejection of claim 7).
Regarding claim 14. The memory of claim 11, wherein the peripheral circuit is further configured to, in response to the erase operation instruction, apply a second voltage to the dummy word line coupled with the memory block before the bit line voltage or the source line voltage of the memory block rises to the first voltage (see rejection of claim 8).
Regarding claim 15. The memory of claim 11, wherein the peripheral circuit is further configured to, in response to the erase operation instruction, apply a second voltage to a word line coupled with the memory block (see rejection of claim 9).
Regarding claim 16. The memory of claim 14, wherein the second voltage includes a ground voltage (see rejection of claim 10).
Regarding claim 17. The memory of claim 11, wherein the peripheral circuit is further configured to send erase information to a memory controller, the erase information indicating the erase count corresponding to the memory block (see rejection of claim 2).
Regarding independent claim 18. An operation method of a memory, comprising: in response to an erase operation instruction, when a bit line voltage or a source line voltage of a memory block having data to be erased rises to a first voltage, setting a dummy word line coupled with the memory block to a floating state, wherein the first voltage is related to an erase count of the memory block (see rejection of claim 1).
Regarding claim 19. The operation method of claim 18, wherein the first voltage is smaller when the erase count is larger (see rejection of claim 4).
Regarding claim 20. The operation method of claim 18, further including, in response to the erase operation instruction, applying an erase voltage to a bit line coupled with the memory block or a source line coupled with the memory block, the erase voltage being greater than the first voltage (see rejection of claim 7).
Allowable Subject Matter
Claims 5 and are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein the memory controller is configured to: determine the first voltage based on a preset formula V1= Vfresh – nxVoffse according to the erase count, wherein V1 is the first voltage, Vfresh is a preset initial first voltage, n is the erase count, and Voffset is a preset offset voltage in combination with the other limitations thereof as is recited in the claim.
Regarding claim 6, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein the memory controller is configured to determine the first voltage by querying a preset mapping table according to the erase count, wherein the preset mapping table includes a mapping relationship between the erase count and the first voltage in combination with the other limitations thereof as is recited in the claim.
Conclusion
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/MINH D DINH/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827