Prosecution Insights
Last updated: October 26, 2026
Application No. 18/787,724

WEAR LEVELING START-GAP ALGORITHM USING MULTIPLE GAP LOCATIONS

Final Rejection §102
Filed
Jul 29, 2024
Priority
May 02, 2024 — provisional 63/641,667
Examiner
VERBRUGGE, KEVIN
Art Unit
2132
Tech Center
2100 — Computer Architecture & Software
Assignee
Micron Technology Inc.
OA Round
4 (Final)
89%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
522 granted / 587 resolved
+33.9% vs TC avg
Minimal -3% lift
Without
With
+-2.7%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
10 currently pending
Career history
600
Total Applications
across all art units

Statute-Specific Performance

§101
5.3%
-34.7% vs TC avg
§103
39.1%
-0.9% vs TC avg
§102
20.8%
-19.2% vs TC avg
§112
8.3%
-31.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 587 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Request for Reconsideration This final Office action is in response to the Request for Reconsideration filed 9/25/26. No claims were amended. Claims 1-4 and 6-20 remain pending. All objections and rejections not repeated below are withdrawn. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 6-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent 11,823,725 to WILKERSON et al. Regarding claim 1, WILKERSON shows the claimed memory array in Fig. 1A as FE memory 101. He shows the claimed controller as controller logic 102. He specifically shows that his controller performs wear leveling for a pool of locations in memory using plural gap locations in the same pool in Fig. 12, described at column 17, lines 4-34. WILKERSON’s region 1 anticipates the claimed pool of memory locations since it has three gap locations in the same pool (region of memory). Regarding claim 6, WILKERSON teaches that his gap pointers are stored in registers, as claimed, in column 10, lines 44-45. Regarding claim 7, WILKERSON teaches that his start pointers are stored in registers, as claimed, in column 10, lines 44-45. Regarding claim 8, WILKERSON’s device operates as claimed, using a first gap location to determine a second gap location as shown in Fig. 2A for example. Allowable Subject Matter Claims 2-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 9-20 are allowed. Response to Arguments Applicant's arguments filed 9/25/26 have been fully considered but they are not persuasive. Regarding claim 1, Applicant is challenging the Examiner’s assertion that “WILKERSON’s region 1 anticipates the claimed pool of memory locations since it has three gap locations in the same pool (region of memory).” Applicant argues at page 1 of the remarks, first paragraph of the remarks after recitation of the claim, that the wear leveling of claim 1 “uses multiple gap locations in the same pool.” The Examiner has interpreted “same pool” to be anticipated by WILKERSON’s Region 1. So the dispute centers around whether WILKERSON’s Region 1 can be interpreted as a pool of memory locations. There is nothing in the claim that characterizes the term “pool” other than the phrase “of memory locations in the memory array.” WILKERSON’s Region 1 certainly comprises memory locations in a memory array. WILKERSON’s Fig. 12 shows at least 10 memory locations in Region 1, not including gap pointer 202-b and start pointer 201-b, so WILKERSON’s Region 1 anticipates the broad term “pool.” Nothing in the claim makes this interpretation inappropriate, so the term “pool” is given its normal meaning of “a group.” Therefore, Applicant’s argument is not persuasive. On page 1, last two paragraphs, Applicant argues that Regions 1, 2, and 3 are operated independently of each other since each region has its own start and gap pointers. This is a moot point since nothing in the claim precludes WILKERSON’s arrangement. All that is required by the claim is wear leveling in a pool of memory locations using a plurality of gap locations in a same pool. WILKERSON certainly anticipates that language because WILKERSON’s pool shown as Region 1 uses three gap locations in the same pool (group of memory locations). WILKERSON’s Region 2 Level 2 gap location may be restricted to a subregion of Region 1, but it is shown and understood to be in Region 1. Similarly, WILKERSON’s Region 3 Level 2 gap location may be restricted to a subregion of Region 1, but it is shown and understood to be in Region 1. Finally, WILKERSON’s Level 1 gap location is a third gap location in Region 1 and is permitted to move throughout Region 1, so there are three gap locations in Region 1, clearly meeting the claim language of “a plurality of gap locations in a same pool.” The claim requires nothing more. Applicant’s argument that “The person of ordinary skill recognizes that each region corresponds to a single gap” ignores WILKERSON’s clear teaching that Region 1 is an overlay of logical Regions 2 and 3 onto a single physical group of memory locations as clearly taught by WILKERSON (see column 2, lines 20-25; column 17, lines 4-5, 16-19, and 35-37). As clearly taught at column 17, lines 16-19, “the level 1 wear leveling rotates cache lines throughout the entire memory while the level 2 wear leveling is region-based with 2 regions.” Fig. 12 shows the “entire memory” as Region 1 having 10 memory locations. It is managed with a Level 1 wear leveling technique that rotates the Level 1 gap through all 10 locations. It is also managed as two separate regions (Regions 2 and 3) that could more accurately be described as sub-regions since they are part of Region 1. In other words, the Level 1 gap rotates through all 10 locations, moving from the bottom to the top one location at a time, then jumping back to the bottom and moving up one location at a time, etc. The two sub-regions 2 and 3 are managed with their own Level 2 gaps that move up and down through their sub-regions only. So Region 1 has three gaps that move through the 10 locations of Region 1 independently, but since Region 1 is really just a group of physical locations (what WILKERSON calls the entire memory), this group of locations can be considered a pool. Furthermore, since this pool or group of memory locations uses a plurality of gap locations to perform wear leveling, it meets the limitations of the claim. On page 2, second paragraph, Applicant argues that “multiple different wear leveling schemes are described. This does not teach or suggest a single wear leveling scheme using multiple gap locations in the same pool, as claimed.” First of all, nothing in the claim requires use of only a single wear leveling scheme for the pool of memory locations. The broad language of the claim merely requires “wear leveling for a pool of memory locations.” This wear leveling could be accomplished by a single scheme or by plural schemes working together. As such, the claim is met by WILKERSON’s plural schemes working together. For these reasons, Applicant’s arguments are not persuasive and the rejections are maintained and made final. Note It is noted that any citations to specific pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this Office action should be directed to the Examiner by phone at (571) 272-4214. Any response to this Office action should be labeled appropriately (including serial number, Art Unit 2132, and type of response) and mailed to Commissioner for Patents, P.O. Box 1450, Alexandria, VA 22313-1450; hand-carried or delivered to the Customer Service Window at the Knox Building, 501 Dulany Street, Alexandria, VA 22314; faxed to (571) 273-8300; or filed electronically using the Patent Center. Information regarding the status of published or unpublished applications may be obtained from the Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about the Patent Center and visit https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Kevin Verbrugge/ Kevin Verbrugge Primary Examiner Art Unit 2132
Read full office action

Prosecution Timeline

Show 2 earlier events
Nov 25, 2025
Response Filed
Dec 19, 2025
Final Rejection mailed — §102
Feb 17, 2026
Response after Non-Final Action
Jun 17, 2026
Request for Continued Examination
Jun 21, 2026
Response after Non-Final Action
Jun 26, 2026
Non-Final Rejection mailed — §102
Sep 25, 2026
Response Filed
Oct 08, 2026
Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12769470
MEASUREMENT OF REPRESENTATIVE CHARGE LOSS IN A BLOCK TO DETERMINE CHARGE LOSS STATE
1y 9m to grant Granted Oct 20, 2026
Patent 12762036
Resolving Capacity Recovery Across Multiple Components of a Storage System
3y 9m to grant Granted Oct 13, 2026
Patent 12743651
System and method for memory reallocation for micro applications using quantum computing
3y 1m to grant Granted Sep 22, 2026
Patent 12737299
FINE-GRAINED DIRTY PAGE TRACKING OF IOMMU SECOND-STAGE LARGE PAGES
3y 9m to grant Granted Sep 15, 2026
Patent 12737120
RELINKING SCHEME FOR SUB-BLOCKS OF GROWN BAD MEMORY BLOCKS
2y 2m to grant Granted Sep 15, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

5-6
Expected OA Rounds
89%
Grant Probability
86%
With Interview (-2.7%)
2y 1m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 587 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month