DETAILED ACTION
This action is responsive to the restriction election filed 13 Mar 2026 and the Information Disclosure Statement filed 29 Jul 2024. Claims 1-20 are pending.
Applicant elected claims 1-12 and 19-20 for examination. Claims 13-18 have been withdrawn.
Claims 1 and 19 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
In the letter dated 13 Mar 2026, the applicant elected claims 1-12 and 19-20 for examination. Claims 13-18 have been withdrawn.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 29 Jul 2024 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Application Title
The Examiner proposes the below Application Title change in accordance with MPEP 606.01 and MPEP 1302.04(a) to improve the descriptive nature of the title. The Applicant can suggest an alternative title if desired. The Application Title should be changed to the following:
“STEP PROGRAMMING NON-VOLATILE MEMORY WITH COARSE AND FINE THRESHOLD VOLTAGE DISTRIBUTIONS”
No action is required by the applicant. If an allowance is processed, the Examiner will change the name as part of the Examiner’s Amendment process.
Allowable Subject Matter
Claims 5 – 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 2, 8 – 12, 19, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin, et al, U.S. Patent Application Publication 2020/0234768 (“Lin”).
Regarding claim 1, Lin teaches:
A non-volatile storage apparatus, comprising: a plurality of non-volatile memory cells; bit lines connected to the plurality of non-volatile memory cells; and a control circuit connected to the plurality of non-volatile memory cells and the bit lines, (Lin, fig 1, “[0052] Memory system 100 includes one or more memory dies 108… Memory structure 126 is addressable by word lines via a row decoder 124 and by bit lines via a column decoder 132. [0054] Control circuitry 110 cooperates with the read/ write circuits 128 to perform memory operations ( e.g., write, read, erase and others) on memory structure 126, and includes state machine 112, an on-chip address decoder 114, a power control circuit 116, and a storage location for one or more tables of bit line (BL) program enable/inhibit voltages 117.”; a memory system with a controller 122, memory structures 126 addressable via bit lines and word lines, that the BLs can be used with enable and inhibit voltages).
the control circuit is configured to apply doses of a programming signal to a set of the non-volatile memory cells that are being programming to a target condition, the target condition is associated with an intermediate condition, (Lin, fig 7A/B, 11, 12A/B, “[0054] In one embodiment the table(s) of bit line (BL) program enable/inhibit voltages 117 is used during state adaptive predictive programming. Tables 117 may store one or more of table 1250… and/or table 2250. [0149] FIGS. 7A and 7B described one example of a multi-pass programming process, referred to as Foggy-Fine Programming.”; that different levels of programming can be used using pulses and the intermediate levels of figure 7A to program multi-level cells. (MLC)).
during a particular dose of the programming signal the control circuit is configured to: apply a program enable voltage to bit lines connected to memory cells of the set that have not yet reached the intermediate condition, (Lin, fig 5, 6A/B, 7A/B, 11 12A/B, “[0128] FIG. 5 is a flowchart describing one embodiment of a process 500 for programming NAND strings of memory cells organized into an array. [0132] In step 546, a program pulse of the program signal Vpgm is applied to the selected word line (the word line selected for programming). If a memory cell on a NAND string should be programmed, then the corresponding bit line is biased at a program enable voltage, in one embodiment. [0181] The process 1200 is one embodiment of step 1110 of process 1100. The process is used during the foggy program phase of a foggy-fine program scheme, in one embodiment. [0185] Step 1202 includes applying a state dependent number of program pulses to memory cells with a full program enable voltage (e.g., OV) applied to the bit lines.”; a programming process of 12B comprising multiple steps and pulses; that each of the cell states of fig 12B are executing step 1110 because the cell has been verified below a threshold level; that the voltages of fig 12B are applied to achieve different states in that cell; that as part of 12B, each of the selected cell states (CP+1 to CP+3) can be programmed with the BL set to a “program enable voltage” in at least one programming pulse as described in step 1202 to enable full programming voltage for at least one programming pulse (or during the claimed particular dose). Note: As stated in claim 11 below, a “particular dose” can comprise 1 programming pulse or multiple programming pulses. Unless further limited, a “particular dose” has been interpreted to include any range of programming pulses for memory cells to be one pulse or multiple pulses as described in Lin figs 5 - 23 as a “particular dose”; likewise a “first portion” and “second portion” of “a particular dose” can be one or multiple programming pulses).
apply a program inhibit voltage to bit lines connected to memory cells of the set that have reached the target condition, (Lin, fig 5, 6A/B, 7A/B, “[0130] For example, when data is written to a set of memory cells, some of the memory cells will need to store data associated with state S0 (see FIG. 6) so they will not be programmed. Additionally, as memory cells reach their intended target data state, they will be inhibited from further programming.”; that different levels of programming can be used using pulses and the intermediate levels of figure 7A to program multi-level cells. (MLC); that the cells already at their intended target data state are inhibited from further programming).
apply a program slowing voltage to bit lines connected to memory cells of the set that have reached the intermediate condition due to a prior dose of the programming signal that was immediately prior to the particular dose of the programming signal, and (Lin, fig 11, 16A/B, “[0205] The process 1600 is one embodiment of step 1112 of process 1100. Thus, process 1600 is one embodiment of predictive programming of memory cells having a Vt of greater then VH when the memory cell first reaches its checkpoint state.”; that step 1112 of fig 11 is used after a cell has achieved a threshold state; that the cells then progress to a different programming embodiment as shown in figs 13, 16 and 17; that immediately prior to executing figs 13, 16 or 17 that the cell was being programmed according to step 1110; that after achieving the threshold state, the cell is then programmed according to step 1112, in this case using fig 16A/B).
apply to bit lines connected to memory cells of the set that have reached the intermediate condition before the prior dose of the programming signal the program slowing voltage for a first portion of the particular dose of the programming signal and (Lin, fig 11, 16A/B, “[0206] Table 1650 is for memory cells having a Vt above a verify high reference level (VH) when the memory cell first reaches the checkpoint state. Table 1650 refers to a voltage “PE_max”, which is the highest magnitude program enable voltage in table 1650. … The parameter beta (~) refers to an increment from one program pulse to the next. In table 1650, the program enable voltages increase by beta (~) each program pulse. [0209] Step 1606 includes applying a program pulse to a memory cell with the initial weak program enable voltage applied to the bit line coupled to the memory cell.”; that immediately after passing the threshold, the cell is programmed to one of the states CP+1 to CP+3; that in each case, the first step takes the PE_max and subtracts a voltage beta, that subtracting the voltage beta slows the programming of that cell).
the program inhibit voltage for a second portion of the particular dose of the programming signal. (Lin, fig 11, 16A/B, “[0212] Table 1650 shows that program inhibit voltages may be applied to bit lines afterwards to keep the memory cells from being over-programmed.”; that at lest two of the desired states CP+1 and CP+2 have an inhibit voltage applied for at least one portion of the four programming pulses of fig 16).
Regarding claim 2, Lin teaches The non-volatile storage apparatus of claim 1, wherein: the first portion of the particular dose is a fixed percentage of the particular dose; and the second portion of the particular dose is a fixed percentage of the particular dose. (Lin, fig 19, 20, “[0232] FIG. 20 depicts voltages waveforms for one embodiment in which the time for which weak program enable voltages are applied to the bit line is managed. The time for which a full program enable is applied to the bit line may also be managed. [0241] With reference to FIG. 20, the time between t3a and t3b is equal to -i:, in one embodiment. With reference to FIG. 20, the time between t3b and t3c is equal to -i:, in one embodiment.”; that during the predictive programming loops of steps 1110 and 1112, the BL voltage (slowing voltage) can be applied for a fixed, known time - which would be a fixed, known percentage of the Programming Pulse applied to the WL).
Regarding claim 8, Lin teaches The non-volatile storage apparatus of claim 1, wherein: the control circuit is configured to apply the program slowing voltage to bit lines connected to memory cells of the set that have reached the intermediate condition by applying the program slowing voltage to bit lines connected to memory cells of the set that have reached the intermediate condition for an entire duration of only one dose of the programming signal. (Lin, fig 5, “[0138] In step 554, the memory system also determines whether the non-checkpoint memory cells have completed programming. In one embodiment, a non-checkpoint memory cells is considered to have reached its target threshold voltage distribution after it has received a predetermined number of program pulses after reaching the checkpoint for that memory cell. [0150] Note that memory cells in the erased state E that are to be in data state SO, are inhibited from programming.”; that the programming of step 1112 of fig 11 is checked in step of 554 of fig 5; the process is halted when the individual cell reaches its target threshold; the cells reaching their target value, whether after “one dose” or twenty doses is halted).
Regarding claim 9, Lin teaches:
The non-volatile storage apparatus of claim 1, further comprising: a plurality of word lines connected to the plurality of non-volatile memory cells and the control circuit, the plurality of non-volatile memory cells are arranged as NAND strings, the plurality of word lines (Lin, fig 2, 4C, “[0045] Each NAND string comprises a number of memory cells connected in series between one or more drain end select gate transistors (referred to as SGD transistors), on a drain end of the NAND string which is connected to a bit line, A set of word lines extends from the source side of a block to the drain side of a block.”; that NAND strings form memory cells, that memory cells are typically associated with a BL and WL).
includes a selected word line connected to the set of non-volatile memory cells that are being programming to the target condition, the bit lines are each connected to different NAND strings, the control circuit applies the doses of the programming signal to the selected word line. (Lin, fig 2, 4C, “[0129] Typically, the program voltage applied to the control gates (via a selected word line) during a program operation is applied as a series of program pulses. [0132] In step 546, a program pulse of the program signal Vpgm is applied to the selected word line (the word line selected for programming).”; that word lines are typically set to a Vpgm level during a program operation).
Regarding claim 10, Lin teaches:
The non-volatile storage apparatus of claim 1, wherein: the target condition is a data state associated with a threshold voltage distribution and a target threshold voltage; and (Lin, fig 8A, 11, “[0155] FIG. 8A shows that memory cells are first programmed from SO to a threshold voltage reference level at a lower tail of one of four checkpoint states (CPA, CPB, CPC, CPD). [0160] A verify low (e.g., VclA) and a verify high (VchA) verify reference level is used to determine what voltage to apply to the bit line.”; that the memory cells are first checked to see if they exceed VclA, if not, they receive programming 1110).
the intermediate condition is a predetermined threshold voltage that is lower than the target threshold voltage. (Lin, fig 8A, 11, “[0161] If the memory cell’s Vt is between the verify low reference level and the verify high program level, the memory cell receives “weak programming” on the next program loop.”; that the memory cells are first checked to see if they exceed VclA, if the cells exceed VclA, they are programmed to at least the VchA, which is higher than Vcla).
Regarding claim 11, Lin teaches The non-volatile storage apparatus of claim 1, wherein: the doses of the programming signal are program voltage pulses. (Lin, fig 20, 21, “[0233] FIG. 20 shows timing for a waveform 2002 applied to the selected word line (WL_sel), and four different waveforms (2004, 2006, 2008, 2010) for voltages applied to a bit line of a memory cell being predictively programmed.”; that the undefined “doses” can be any number of the undefined “programming signals”. Note: a potential limitation (requiring further examination) might be “wherein: a single dose is defined as the duration of a single programming pulse”).
Regarding claim 12, Lin teaches:
The non-volatile storage apparatus of claim 1, wherein: the program slowing voltage is greater than the program enable voltage; and (Lin, fig 12, “[0181] Table 1250 illustrates the program enable voltage type/level used for memory cells having a Vt between a verify low reference level (VL) and a verify high reference level (VH) when the memory cell first reaches the checkpoint state.”; that different voltages are applied to the BL to have different effects on programming memory cells).
the program inhibit voltage is greater than the program slowing voltage. (Lin, fig 12, “[0162] The program inhibit voltage cuts off the NAND channel from the bit line to allow the boosting voltages to raise the NAND channel potential, in one embodiment. The program inhibit voltage is VDD (about 2 V), in one embodiment. The QPW voltage is larger than the full program enable voltage, but smaller than the program inhibit voltage, in one embodiment.”; that the fur enable voltage is typically lower than the intermediate “slowing voltage”; that the “slowing voltage” is smaller than the program inhibit applied to fully programmed BLs).
Regarding claim 19, Lin teaches:
A non-volatile storage apparatus, comprising: a plurality of non-volatile memory cells; and (Lin, fig 1, “[0052] Memory system 100 includes one or more memory dies 108… Memory structure 126 is addressable by word lines via a row decoder 124 and by bit lines via a column decoder 132. [0054] Control circuitry 110 cooperates with the read/ write circuits 128 to perform memory operations ( e.g., write, read, erase and others) on memory structure 126, and includes state machine 112, an on-chip address decoder 114, a power control circuit 116, and a storage location for one or more tables of bit line (BL) program enable/inhibit voltages 117.”; a memory system with a controller 122, memory structures 126 addressable via bit lines and word lines, that the BLs can be used with enable and inhibit voltages).
means for programming the non-volatile memory cells that slows down programming using a first technique for slowing programming after a memory cell reaches an intermediate condition and (Lin, fig 5, 6A/B, 7A/B, 16A/B, “[0130] For example, when data is written to a set of memory cells, some of the memory cells will need to store data associated with state S0 (see FIG. 6) so they will not be programmed. Additionally, as memory cells reach their intended target data state, they will be inhibited from further programming. [0205] The process 1600 is one embodiment of step 1112 of process 1100. Thus, process 1600 is one embodiment of predictive programming of memory cells having a Vt of greater then VH when the memory cell first reaches its checkpoint state.”; that different levels of programming can be used using pulses and the intermediate levels of figure 7A to program multi-level cells. (MLC); that the cells already at their intended target data state are inhibited from further programming).
using a second technique for slowing programming after using the first technique and prior to inhibiting programming for the memory cell. (Lin, fig 11, 16A/B, “[0206] Table 1650 is for memory cells having a Vt above a verify high reference level (VH) when the memory cell first reaches the checkpoint state. [0212] Table 1650 shows that program inhibit voltages may be applied to bit lines afterwards to keep the memory cells from being over-programmed.”; that immediately after passing the threshold, the cell is programmed to one of the states CP+1 to CP+3; that in each case, the first step takes the PE_max and subtracts a voltage beta, that subtracting the voltage beta slows the programming of that cell; that an inhibit voltage can also be applied to the BL; that the “2nd technique” can include both a slowing step and an inhibiting step).
Regarding claim 20, Lin teaches:
The non-volatile storage apparatus of claim 19, wherein: the means for programming applies a series of program voltage pulses to the non-volatile memory cells that increase in voltage magnitude pulse-to-pulse; (Lin, fig 11, 16A/B, “[0179] If the Vt is between the verify low reference level and the verify high reference level, then the memory cell is predictively programmed to its target state using what is referred to as a lower tail process, in step 1110. [0180] If the Vt is between the verify low reference level and the verify high reference level, then the memory cell is predictively programmed to its target state using what is referred to as an upper tail process, in step 1112.”; that cells can be programmed with at least two programming loops comprising steps 1110 and 1112 of figure 11).
the first technique for slowing programming comprises applying a program slowing voltage to a bit line connected to the non-volatile memory cell during an entire time of applying one program voltage pulse of the program voltage pulses; and (Lin, fig 11, 16A/B, “[0206] The table 1650 covers three non-CP states, which are defined based on their Vt relative to the checkpoint state. [0207] Step 1602 includes setting a state dependent pulse count for the memory cell. With reference to table 1650, the count is set to n+l, in one embodiment. For example, the count may be set to two for CP+l, three for CP+2, and four for CP+3.”; that to achieve a state of CP+3, an “slowing voltage” is applied to the relevant Bl for the entire step of 1112).
the second technique for slowing programming comprises applying to the bit line connected to the non-volatile memory cell the program slowing voltage for a first portion of a subsequent program voltage pulse of the program voltage pulses and (Lin, fig 11, 16A/B, “[0206] Table 1650 is for memory cells having a Vt above a verify high reference level (VH) when the memory cell first reaches the checkpoint state. Table 1650 refers to a voltage “PE_max”, which is the highest magnitude program enable voltage in table 1650. … The parameter beta (~) refers to an increment from one program pulse to the next. In table 1650, the program enable voltages increase by beta (~) each program pulse. [0209] Step 1606 includes applying a program pulse to a memory cell with the initial weak program enable voltage applied to the bit line coupled to the memory cell.”; that immediately after passing the threshold, the cell is programmed to one of the states CP+1 to CP+3; that in each case, the first step takes the PE_max and subtracts a voltage beta, that subtracting the voltage beta slows the programming of that cell).
a program inhibit voltage for a second portion of the subsequent program voltage pulse, (Lin, fig 11, 16A/B, “[0212] Table 1650 shows that program inhibit voltages may be applied to bit lines afterwards to keep the memory cells from being over-programmed.”; that at lest two of the desired states CP+1 and CP+2 have an inhibit voltage applied for at least one portion of the four programming pulses of fig 16).
the subsequent program voltage pulse is applied after the one program voltage pulse, the program inhibit voltage is greater in voltage magnitude than the program slowing voltage. (Lin, fig 12, “[0162] The program inhibit voltage cuts off the NAND channel from the bit line to allow the boosting voltages to raise the NAND channel potential, in one embodiment. The program inhibit voltage is VDD (about 2 V), in one embodiment. The QPW voltage is larger than the full program enable voltage, but smaller than the program inhibit voltage, in one embodiment.”; that the fur enable voltage is typically lower than the intermediate “slowing voltage”; that the “slowing voltage” is smaller than the program inhibit applied to fully programmed BLs).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Lin, ibid. (“Lin-2”).
Regarding claim 3, Lin teaches the non-volatile storage apparatus of claim 1.
Lin teaches wherein: the first portion (Lin, fig 19, 20, “[0232] FIG. 20 depicts voltages waveforms for one embodiment in which the time for which weak program enable voltages are applied to the bit line is managed. The time for which a full program enable is applied to the bit line may also be managed. [0241] With reference to FIG. 20, the time between t3a and t3b is equal to -i:, in one embodiment. With reference to FIG. 20, the time between t3b and t3c is equal to -i:, in one embodiment.”; that during the predictive programming loops of steps 1110 and 1112, the BL voltage (slowing voltage) can be applied for a fixed, known time - which would be a fixed, known percentage of the Programming Pulse applied to the WL).
Lin does not explicitly teach of the particular dose is 50% of the particular dose; and the second portion of the particular dose is 50% of the particular dose..
Lin-2 teaches of the particular dose is 50% of the particular dose; and the second portion of the particular dose is 50% of the particular dose. (Lin-2, fig 20, 21, “[0246] Step 2112 includes incrementing a length of the weak program enable voltage. The increment is the previously discussed tau (-i:), in one embodiment. In one embodiment, the increment is the same for each program pulse. However, in one embodiment, the increment is different for at least one of the pulses. In one embodiment, the increment is the same for each state. However, in one embodiment, the increment is different for at least one of the states.”; that the “tau” can be increased for programming pulses, or for programming states; since fig 20 shows 1tau, 2tau, 3tau and t_max as nearly equal then; Note: by claiming 50%, applicant is actually claiming all percentages from 45-55%, which is a range).
In view of the teachings of Lin-2 it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lin-2 to Lin before the effective filing date of the claimed invention in order to teach memory cell programming. The teachings of Lin-2, in the same or in a similar field of endeavor with Lin, can combine Lin-2’s continuous function from 0-100 percent with Lin’s implied, set function of figure 21. The static “tau” and the “variable tau” merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 4, Lin teaches the non-volatile storage apparatus of claim 1.
Lin teaches wherein: the first portion of the particular dose (Lin, fig 19, 20, “[0232] FIG. 20 depicts voltages waveforms for one embodiment in which the time for which weak program enable voltages are applied to the bit line is managed. The time for which a full program enable is applied to the bit line may also be managed. [0241] With reference to FIG. 20, the time between t3a and t3b is equal to -i:, in one embodiment. With reference to FIG. 20, the time between t3b and t3c is equal to -i:, in one embodiment.”; that during the predictive programming loops of steps 1110 and 1112, the BL voltage (slowing voltage) can be applied for a fixed, known time - which would be a fixed, known percentage of the Programming Pulse applied to the WL).
Lin does not explicitly teach is a changeable percentage of the particular dose; and the second portion of the particular dose is a changeable percentage of the particular dose..
Lin-2 teaches is a changeable percentage of the particular dose; and the second portion of the particular dose is a changeable percentage of the particular dose. (Lin-2, fig 20, 21, “[0246] Step 2112 includes incrementing a length of the weak program enable voltage. The increment is the previously discussed tau (-i:), in one embodiment. In one embodiment, the increment is the same for each program pulse. However, in one embodiment, the increment is different for at least one of the pulses. In one embodiment, the increment is the same for each state. However, in one embodiment, the increment is different for at least one of the states.”; that the “tau” can be increased for programming pulses, or for programming states; since fig 20 shows 1tau, 2tau, 3tau and t_max as nearly equal then; Note: by claiming 50%, applicant is actually claiming all percentages from 45-55%, which is a range).
In view of the teachings of Lin-2 it would have been obvious for a person of ordinary skill in the art to apply the teachings of Lin-2 to Lin before the effective filing date of the claimed invention in order to teach memory cell programming. The teachings of Lin-2, in the same or in a similar field of endeavor with Lin, can combine Lin-2’s continuous function from 0-100 percent with Lin’s implied, set function of figure 21. The static “tau” and the “variable tau” merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONALD H.B. BRASWELL whose telephone number is (469)295-9119. The examiner can normally be reached on 7-5 Central Time (Dallas).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Donald HB Braswell/ Primary Examiner, Art Unit 2825