DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/22/2026 has been entered.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
Such claim limitation(s) is/are: “a power management unit (PMU) that dynamically provides different power-supply voltages for the drivers respectively during a line scan period or a frame scan period” in claim 1.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. The specification fails to provide any disclosure describing the structure for the claimed power management unit and power generator. However, for the purpose of examination, examiner interprets power management unit as circuit for generating voltages signals.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gray et al (US Pub 2021/0343231) in view of OH et al (US Pub 2023/0005416).
With respect to claim 1, Gray discloses a display system, (fig. 1; electronic device 100) comprising: a display panel divided into a plurality of display blocks arranged in rows and columns, (fig. 1; device array 105 includes plurality of zones) each display block including a plurality of micro-light-emitting diodes (microLEDs) driven by a corresponding driver disposed in a corresponding display block (par 0031; discloses The device array 105 comprises an array of zone integrated circuits (ICs) 120. In a display device the zone ICs 120 may each include one or more LEDs in an LED zone and associated driver circuitry for driving the LED zone; par 0032; discloses The LEDs of each zone IC 120 may be micro light emitting diodes (micro-LEDs) (e.g., having a size of less than 100 micrometers),); a power management unit (PMU) that provides different power-supply voltages for the drivers respectively during a line scan period or a frame scan period (fig. 2; power line communication driver (PLC) 220; par 0064; discloses During the operational mode 870, the power line communication signal provides control data (Con Data) as digital data modulated onto the supply voltage. The Con Data may be updated with each image frame or video frame. The operational mode 870 continues until the power line communication signal transitions from high to low; par 0037; discloses each PLC driver circuit 220 comprises a ramp generator 222 and a buffer circuit 224. The ramp generator 222 generates a ramp signal 226 that encodes the control signal 212 by switching between a high voltage level and a low (non-zero) voltage level. For example, the ramp generator 220 may switch its output between 5.0V and 4.5V to encode the control signal 212); and a timing controller that determines the different power-supply voltages for the PMU according to content of data to be display on the display panel (fig. 2; timing controller 210; par 0035; discloses the timing controller 210 generates respective control signals 212 encoding commands or data for communicating to the zone ICs 120. In a display device, the control signals 212 may include, for example, values for driving pixels of the display device 100, timing for driving the pixels, commands for controlling operating parameters of the zone ICs 120, requests for feedback from the zone ICs 120 or other control information. The PLC drivers 220 each drive a group of zone ICs 120 coupled to one of the PLC lines 115 based on the respective control signals 212. The PLC drivers 220 encode the respective control signals 212 as a PLC signal that is output to respective PLC lines 115 by modulating the control signal 212 onto a supply voltage; see par 0066 as well);
Gray doesn’t expressly disclose wherein the PMU dynamically provides said different power-supply voltages according to content of corresponding data to be displayed on the display panel;
In the same field of endeavor, OH discloses display apparatus and driving method (see abstract); OH discloses wherein the PMU dynamically provides said different power-supply voltages according to content of corresponding data to be displayed on the display panel (par 0094; discloses the driver ICs 200-1, 200-2, . . . , 200-n may generate a data signal for representing gradation of an image based on image data transferred from the timing controller 500. The data signal may include a data voltage that is input to a pixel circuit 131P (see FIG. 5), par 0131; discloses a data signal provided from the driver IC 200 is input to the PWM control circuit 131PWM and the PAM control circuit 131PAM, the data signal may include a first voltage for controlling an amplitude of driving current and a second voltage for controlling a pulse width of driving current. Hereinafter, the first voltage is also referred to as a PAM data voltage, and the second voltage is also referred to as a PWM data voltage; par 0166; discloses The timing controller 500 or the main controller 300 may determine whether to enter the power saving mode or to return to the normal mode, and the driver IC 200 may apply different magnitudes of PAM data voltages to the display panel 100 according to whether the display apparatus 1 operates in the normal mode or in the power saving mode; see par 0168-0170 as well);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Gray to incorporate the teachings of OH to dynamically change the voltages supplied to the pixel drivers based on the control of the timing controller such that brightness of the displayed content is adjusted in real-time based on different situations such as ambient condition, time of the day, etc.
With respect to claim 2, Gray as modified by OH discloses wherein the PMU comprises: a power generator that generates the different power-supply voltages (Gray; par 0037; discloses each PLC driver circuit 220 comprises a ramp generator 222 and a buffer circuit 224. The ramp generator 222 generates a ramp signal 226 that encodes the control signal 212 by switching between a high voltage level and a low (non-zero) voltage level).
With respect to claim 3, Gray as modified by OH discloses wherein the drivers of the display panel are arranged into groups (Gray; par 0034; discloses the zone ICs 120 may be arranged in groups that share a common PLC line 115. In the illustrated embodiment of FIG. 1, each row of the display device corresponds to a group of zone ICs 120 that shares a common PLC line 115).
With respect to claim 4, Gray as modified by OH discloses wherein each power-supply voltage is determined according to total current required by a corresponding group of drivers during the line scan period or the frame scan period; such that a corresponding power-supply voltage with least value can afford the required total current for the corresponding group of drivers (Gray; par 0035; discloses the PLC drivers 220 each drive a group of zone ICs 120 coupled to one of the PLC lines 115 based on the respective control signals 212. The PLC drivers 220 encode the respective control signals 212 as a PLC signal that is output to respective PLC lines 115 by modulating the control signal 212 onto a supply voltage; par 0038; discloses the buffer circuit 224 comprises a wide bandwidth, slew rate controlled buffer that operates with unity gain and can both sink and source sufficient current to drive the group of zone ICs 120. In an embodiment, the sourcing function of the buffer circuit 224 may be larger than its sinking function to meet the DC power specifications of the group of zone ICs 120));
With respect to claim 9, Gray as modified by OH discloses wherein the drivers are grounded group by group respectively (Gray; par 0051; discloses the ground pin 628 is configured to provide a path to a ground line for the driver circuit 620, which may be common to the corresponding LED zone 630).
With respect to claim 10, Gray as modified by OH discloses wherein the drivers are grounded together (Gray; par 0050; discloses the GND lines provide a path to ground for the LED zones 630 and the driver circuits 620.).
With respect to claim 11, Gray as modified by OH discloses wherein the driver comprises: a first circuit that turns on at least one row of corresponding microLEDs at a time; and a second circuit that provides PWM data signals to the turned-on row of microLEDs (Gray; fig. 13; discloses drive circuit includes first circuit Demux and second circuit DC1; par 0084; discloses The driver circuit layer 1140 includes a plurality of driver circuits (e.g., DC1, DC2, . . . DCn) and a demultiplexer DeMux. The control signal instructs the demultiplexer DeMux which row or rows of LEDs are to be enabled and supplied with power using the VLED lines. Thus, a particular LED in the LED layer 1170 is activated when power (VLED) is supplied on its associated row and the driver current is supplied to its associated column); wherein a duty cycle of each PWM data signal is proportional to brightness of corresponding data to be displayed on the display panel (Gray; par 0071; discloses During the operational mode, the PWM clock selection signal PWMCLK_sel 1056 specifies a duty cycle for controlling PWM dimming by the PWM dimming circuit 1070. Based on the selected duty cycle, the PWM dimming circuit 1070 controls timing of an on-state and an off-state of the transistor 1075. During the on-state of the transistor 1075, a current path is established from the output pin 626 (coupled to the LED zones 630) to the ground pin 628 through the transistor 1075 and the brightness control circuit 1080 sinks the driver current through the LEDs of the LEDs zones 630. During an off-state of the transistor 1075, the current path is interrupted to block current from flowing through the LED zones 630. The brightness control circuit 1080 receives the maximum current signal Max. Current 358 from the control logic 1050 and controls the current level that flows through the LEDs (from the output pin 626 to the ground pin 628) when the transistor 1075 is in the on-state. During the operational mode, the control logic 1050 controls the duty cycle of the PWM dimming circuit 1070 and the maximum current Max. Current 1058 of the brightness control circuit 1080 to set the LED zones 630 to the desired brightness.).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gray et al (US Pub 2021/0343231) in view of OH et al (US Pub 2023/0005416) and Chou et al (US Pub 2023/0269845).
With respect to claim 5, Gray as modified by OH doesn’t expressly disclose wherein the timing controller determines the total current required by the corresponding group of drivers according to duty cycles of pulse-width modulation (PWM) data signals during the line scan period or the frame scan period;
In the same field of endeavor, Chou discloses display device and driving method (see abstract); Chou discloses determining the total current required by the corresponding group of drivers according to duty cycles of pulse-width modulation (PWM) data signals during the line scan period or the frame scan period (par 0050; discloses the average driving current is determined based on the duty cycle of the PWM signal and the magnitude of the input voltage. In an embodiment, the pulses of the PWM signal may be scrambled. Therefore, the pulses of multiple PWM signals for different current regulators are scattered with small variations, so that the loading of the power converter may be reduced and the EMI problem may be mitigated. In another embodiment, the duty cycle of the PWM signal may be well controlled and modified, and the value of the input voltage may be adjusted accordingly, to generate a target average driving current capable of generating desired brightness);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Gray as modified by OH to incorporate the teachings of Chou to update the PWM signal based on the target current in order to display image with desired brightness with larger degree of duty cycle adjustment.
Claim(s) 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gray et al (US Pub 2021/0343231) in view of OH et al (US Pub 2023/0005416), Chou et al (US Pub 2023/0269845), Nam et al (US Pub 2023/0237952) and Matsuura (US Pub 2012/0313979).
With respect to claim 6, Gray as modified by OH and Chou don’t expressly disclose wherein the power-supply voltage is obtained by multiplying the total current by a total equivalent resistance plus voltage drop of a microLED;
In the same field of endeavor, Nam discloses a display device and driving method thereof (see abstract); Nam discloses wherein the power-supply voltage is obtained by multiplying the total current by a total equivalent resistance (par 0057; discloses the controller 121 may generate the first voltage, which is used to compensate for a voltage drop according to the load current and the resistance R(CNT+PCB) caused by the printed circuit board PCB including the connector CNT, to supply a constant voltage to the input terminal 213 of the display driver IC 110. In an example, as a magnitude of the load current and the resistance of the printed circuit board PCB including the connector CNT increases, the controller 121 may increase and generate the first voltage, with a magnitude corresponding to the increased magnitude of the load current, and output the first voltage through the output terminal 211);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Gray as modified by OH and Chou to incorporate the teachings of Nam to generate the voltage by taking into account for the resistance and voltage drop in the line in order to provide stable constant voltage to the display driver such that display quality is maintained;
Gray as modified by OH, Chou and Nam don’t expressly disclose wherein the power-supply voltage is obtained taking in to account voltage drop of a microLED;
In the same field of endeavor, Matsuura discloses wherein the power-supply voltage is obtained taking in to account voltage drop of a microLED (par 0029; discloses When the light source is LED, the voltage adjusting circuit adjusts the output voltage in accordance with the forward direction voltage drop of LED which fluctuates depending on the driving current of each LED. It is assumed that the output voltage also fluctuates depending on the number of LEDs connected in series. In the case of any light source other than LED, it is assumed that the light source driving unit 14 generates the current and the voltage required when each of the light sources is turned ON (lighted) at a desired luminance);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Gray as modified by OH, Chou and Nam to incorporate the teachings of Matsuura to generate the output voltage by taking into account for the voltage drop caused by the microLED in order to provide stable constant voltage to the display driver such that desired luminance is generated;
With respect to claim 7, Gray as modified by OH, Chou, Nam and Matsuura disclose compensating the voltages for voltage drop (Gray; par 0038; disclose the buffer circuit 224 buffers the ramp signal 226 to prevent or reduce voltage drop on the PLC line 115 even when the zone ICs 120 draw significant current);
Gray as modified by OH, Chou, Nam and Matsuura don’t expressly disclose wherein the total equivalent resistance comprises the following series-connected resistances: resistance of an external conductive wire between an input power pad of the driver and an output power pad of the PMU that provides the power-supply voltage; equivalent internal resistance associated with the input power pad of the driver; equivalent internal resistance associated with a common power pad of the driver; and resistance of an external conductive wire between the common power pad of the driver and a common node;
Nam discloses wherein the total equivalent resistance comprises the following series-connected resistances: resistance of an external conductive wire between an input power pad of the driver and an output power pad of the PMU that provides the power-supply voltage; equivalent internal resistance associated with the input power pad of the driver; equivalent internal resistance associated with a common power pad of the driver; and resistance of an external conductive wire between the common power pad of the driver and a common node; (Nam; par 0057; disclose In an example, the controller 121 may generate the first voltage, which is used to compensate for a voltage drop according to the load current and the resistance R(CNT+PCB) caused by the printed circuit board PCB including the connector CNT, to supply a constant voltage to the input terminal 213 of the display driver IC 110);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Gray as modified by OH, Chou, Nam and Matsuura to incorporate the teachings of Nam to generate the output voltage by taking into account for the resistance and voltage drop in the line and components of the circuit in order to provide stable constant voltage to the display driver such that display quality is maintained;
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gray et al (US Pub 2021/0343231) in view of OH et al (US Pub 2023/0005416) and Lee et al (US Pub 2016/0307490).
With respect to claim 8, Gray as modified by OH doesn’t expressly disclose wherein the timing controller determines the total current required by the corresponding group of drivers according to data signals, and each power-supply voltage of a corresponding group of drivers is determined according to the determined total current;
In the same field of endeavor, Lee discloses a display device and driving method thereof (see abstract); Lee discloses determining the total current required by the corresponding group of drivers according to data signals, (par 0068; discloses the target current determiner 400 can determine a magnitude of a target current ITARGET based on the input image data IDATA. Thus, the target current determiner 400 can determine the magnitude of the target current ITARGET to maintain a total amount of current flowing through the display panel 100) and each power-supply voltage of a corresponding group of drivers is determined according to the determined total current (par 0069; discloses the power supply 500 can adjust a voltage level of a power source to provide the power source corresponding to the target current ITARGET to the display panel 100 through a power line);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Gray as modified OH to incorporate the teachings of Lee to update the voltage level based on the target current determined using the image data in order to maintain the total amount of current flowing thereby preventing the luminance degradation or luminance changing.
Response to Arguments
Applicant's arguments filed with respect to claim 1 have been fully considered However they are moot as they do not apply to new reference being used in the current rejection.
Conclusion
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/SUJIT SHAH/Examiner, Art Unit 2624