Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “first transistor” of claim 14, line 1, and “second transistor” of Claim 14, line 3, must be shown or the features canceled from the claim. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Boucher (US 20100090766 A1) hereafter referred to as “Boucher”.
Regarding claim 1, in the embodiment of Figure 5, Li discloses:
An operational amplifier (OPA) (complete amplifier system as shown in Fig. 1), comprising:
an output stage (Fig. 5, Typical Rail-to-Rail Output Stage) composed of a P-type output transistor (PMOS_DRIVER_1) and an N-type output transistor (NMOS_DRIVER_1) connected in series between a power supply (V_AMP) and ground (G_AMP), the N- type output transistor being controlled by a first control voltage (gate voltage NGATE) and the P-type output transistor being controlled by a second control voltage (gate voltage PGATE);
a first leakage eliminating circuit (NMOS_1) configured to prevent a sinking current through the N-type output transistor from entering the ground when an input voltage rises from a low voltage level to a high voltage level (paragraph [0038] lines 1-7, NGATE controls the flow of current to the driver (i.e. NMOS_DRIVER_1) and pulled down by NMOS_1, thereby turning off the corresponding driver); and
a second leakage eliminating circuit (PMOS_1) configured to prevent a sourcing current through the P-type output transistor from entering a load (external load resistor RLOAD) when the input voltage falls from the high voltage level to the low voltage level (paragraph [0038] lines 1-10, PGATE is pulled up by PMOS_1, thereby turning off the corresponding driver (i.e. PMOS_DRIVER_1) and during this disabled condition no current will flow to or from the external load resistor).
Regarding claim 2, in the embodiment of Figure 5, Li discloses:
the first leakage eliminating circuit turns off the N-type output transistor when the input voltage rises from the low voltage level to the high voltage level (paragraph [0038] lines 1-7, NMOS_1 pulls down NGATE and disables the corresponding driver (i.e. NMOS_DRIVER_1)), and
the second leakage eliminating circuit turns off the P-type output transistor when the input voltage falls from the high voltage level to the low voltage level (paragraph [0038] lines 1-7, paragraph [0038] lines 1-10, PMOS_1 pulls up PGATE and disables the corresponding driver (i.e. PMOS_DRIVER_1)).
Regarding claim 3, in the embodiment of Figure 5, Li discloses:
the first leakage eliminating circuit pulls the first control voltage to the ground when the input voltage rises from the low voltage level to the high voltage level (paragraph [0038] lines 5-7, NGATE is pulled down to G_AMP by NMOS_1), and
the second leakage eliminating circuit pulls the second control voltage to the power supply when the input voltage falls from the high voltage level to the low voltage level (paragraph [0038] lines 5-7, PGATE is pulled up to V_AMP by PMOS_1).
Regarding claim 4, in the embodiment of Figure 5, Li discloses:
a source of the P-type output transistor is connected to the power supply (PMOS_DRIVER_1 source is connected to V_AMP, as shown in Figure 5) and a source of the N-type output transistor is connected to the ground (NMOS_DRIVER_1 source is connected to G_AMP, as shown in Figure 5).
Regarding claim 5, in the embodiment of Figure 5, Li discloses:
an interconnected node between the P-type output transistor and the N-type output transistor (node between PMOS_DRIVER_1 AND NMOS_DRIVER_1 outputted to VOUT) is used as an output node, at which an output voltage (VOUT) is generated.
Regarding claim 6, in the embodiment of Figure 5, Li discloses:
the output node is directly connected to an inverting input node (Fig. 1, GME representing the output stage analogous to Figure 5, output of GM3 is connected to negative input as known in the art as the inverting input node in output stage GM3), and a non-inverting input node (positive input, as known in the art as a non-inverting input of GM3) is coupled to receive an input voltage (via GM1, shown in Fig. 1).
Regarding claim 7, in the embodiment of Figures 1 and 5, Li discloses:
an input stage (GM1, as shown in Fig. 1) that generates the first control voltage and the second control voltage for controlling the N-type output transistor and the P-type output transistor respectively (e.g. the gate voltages PGATE and NGATE in Fig. 5).
Regarding claim 8, in the embodiment of Figures 1 and 5, Li discloses:
the input stage comprises a class-AB amplifier (paragraph [0020], Class AB output the gate voltages PGATE and NGATE).
Regarding claim 11, in the embodiment of Figures 1 and 5, Li discloses:
a gate of the N-type output transistor is controlled by the first control signal, and a gate of the P-type output transistor is controlled by the second control signal (Fig. 5, gates of NMOS_DRIVER_1 and PMOS_DRIVER_1 are controlled by gate voltages NGATE and PGATE).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 is rejected under 35 U.S.C. 103 as being unpatentable over Boucher (US 20100090766 A1) in view of Li (US 20160204752 A1), hereafter referred to as “Boucher” and “Li”, respectively.
Regarding claim 9, in the embodiment of Figures 1 and 5, Boucher discloses:
increasing a sinking current when the input voltage falls and increasing a sourcing current when the input voltage rises (paragraph [0033] lines 10-15, A2 controls flow of leakage current of PMOS_DRIVER_1 in response to an input to the amplifier). However, Boucher is silent in teaching a first and second slew rate enhance circuit.
Li teaches:
a first and second slew rate enhance circuit (Figs. 5a, 6, 7, and 8, first slew-rate adjuster 426 and 424) configured to increase a sinking current when the input voltage falls and to increase a sourcing current when the input voltage rises (paragraph [0004], first and second slew-rate adjuster depends on the direction of a change of the input signal increases the voltage at the input at the input transistor for reducing leakage current in a push-pull circuit).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention for the output stage as taught by Boucher (Fig. 5) to further include a first and second slew rate enhance circuit, as taught by Li (Fig. 5a) to switch the first and second transistor based on an input signal (Li, paragraphs [0009]-[0010]), thereby suggesting the obviousness of such a combination.
Allowable Subject Matter
Claims 10, and 12-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 10 and 12-14:
the cited prior art of record, Boucher (US 20100090766 A1), either singly or in proper combination, does not teach or make obvious, along with the other claimed features, “the first slew rate enhance circuit is connected between an output node and a node that provides the first control voltage, and the second slew rate enhance circuit is connected between the output node and a node that provides the second control voltage” per claim 10, and
“the first leakage eliminating circuit comprises a first switch connected between the gate of the N-type output transistor and the ground, and the second leakage eliminating circuit comprises a second switch connected between the gate of the P-type output transistor and the power supply” per claim 12.
claims 13-14 are objected to for dependence on objected claim 12.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALANE LIENG whose telephone number is (571)272-5739. The examiner can normally be reached Monday-Friday 6:30 - 4:00 CST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Baltzell can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Malane Lieng/ Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/ Supervisory Patent Examiner, Art Unit 2843
